: A generic class used by the Network-Transport-Stack (NTS) to to transfer a chunk of data over an AXI4-Stream interface. More...

#include <cassert>
#include <iostream>
#include <hls_stream.h>
#include "ap_int.h"

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Classes
class	AxisRaw

Macros
#define	AXIS_RAW_WIDTH_AT_10GE 64

#define	ARW AXIS_RAW_WIDTH_AT_10GE

#define	TLAST 1

Typedefs
typedef ap_uint< 64 >	LE_tData

typedef ap_uint< 64/2 >	LE_tDataHalf

typedef ap_uint< 64/8 >	LE_tKeep

typedef ap_uint< 1 >	LE_tLast

typedef ap_uint< 64 >	tData

typedef ap_uint< 64/2 >	tDataHalf

typedef ap_uint< 64/8 >	tKeep

typedef ap_uint< 64/16 >	tKeepHalf

typedef ap_uint< 1 >	tLast

Functions
template<class TypeIn , class TypeOut >
void	pAxisRawCast (hls::stream< TypeIn > &si, hls::stream< TypeOut > &so)
	AxisRaw cast - Casts an AxisRaw stream to/from an AxisRaw derived class. More...

Detailed Description

: A generic class used by the Network-Transport-Stack (NTS) to to transfer a chunk of data over an AXI4-Stream interface.

System: : cloudFPGA Component : Shell, Network Transport Stack (NTS) Language : Vivado HLS

Warning: : The order of the bytes of the 'tdata' member is aligned with the format generated by the 10GbE MAC of Xilinx which organizes its two 64-bit Rx and Tx interfaces into 8 lanes (see PG157). The result of this division into lanes happens to store the 'tdata' member into LITTLE-ENDIAN (LE) order instead of the initial BID-ENDIAN (BE) order used to transmit bytes over the physical media. As an example, consider the 16-bit field "EtherType" of the ETH frame which value is '0x0800' when the Ethernet frame contains an IPv4 packet. This field will be transmitted on the media in big-endian order .i.e, a '0x08' byte followed by a '0x00' byte. However, this field will end up being ordered in little-endian mode (.i.e, 0x0080) by the AXI4-Stream interface of the 10GbE MAC.

Therefore, the mapping of a network stream of bytes onto a 64-bits AXIS_RAW interface in LITTLE-ENDIAN is as follows:

   6                   5                   4                   3                   2                   1                   0

3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | B[07] | B[06] | B[05] | B[04] | B[03] | B[02] | B[01] | B[00] | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | B[15] | B[14] | B[13] | B[12] | B[11] | B[10] | B[09] | B[08] | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+

@info: What's this Little-Endian(LE) vs Big-Endian(BE) anyhow. FYI - The original source from Xilinx (available at: https://github.com/Xilinx/HLx_Examples/tree/master/Acceleration/tcp_ip) is entirely coded with respect to the above mapping of the media network stream over a 64-bits interface in little-endian oder. This makes the initial code particularly difficult to read, maintain and test. Therefore, this class implements a few methods to access the AXIS data streams as if they were encoded in the expected big-endian order. All of this headache could have been avoided if the original code had swapped the 64-bits bus to/from the Ethernet MAC. This enhancement will be implemented if/when we will move to a higher data rate (.e.g 25GE or 100GE). Until then, here is a graphical helper to visualize the LE<->BE relation:

             Lower-Half                     Higher-Half
  +---------------+---------------+---------------+---------------+

LITTLE |63 (L-L) 48|47 (L-H) 32|31 (H-L) 16|15 (H-H) 0| +------------—+------------—+------------—+------------—+ /|\ /|\ /|\ /|\ +------------—|------------—|------------—|-+ +------------—|-+ | | +----------—+ | | | +------------—|------------—|----------—+ | |/ |/ |/ |/ +------------—+------------—+------------—+------------—+ BIG |63 (H-H) 48|47 (H-L) 32|31 (L-H) 16|15 (L-L) 0| +------------—+------------—+------------—+------------—+ Higher-Half Lower-Half

     +---------------+---------------+---------------+---------------+

LITTLE |63 Lower-Half 32|31 Higher-Half 0| +------------—+------------—+------------—+------------—+ /|\ /|\ +------------------------—|–+ +--------------------------—+ | |/ |/ +------------—+------------—+------------—+------------—+ BIG |63 Higher-Half 32|31 Lower-Half 0| +------------—+------------—+------------—+------------—+

Definition in file AxisRaw.hpp.

Classes

Macros

Typedefs

Functions

Detailed Description