cloudFPGA (cF) API  1.0
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AxisUdp.hpp File Reference
cF » cFSphere » cFDK » SHELL Library » NTS

: A class to access UDP header fields within data chunks transmitted over an AXI4-Stream interface. More...

#include "AxisRaw.hpp"
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Classes

class  AxisUdp
 

Macros

#define UDP_HEADER_LEN   8
 

Typedefs

typedef ap_uint< 16 > LE_UdpSrcPort
 
typedef ap_uint< 16 > LE_UdpDstPort
 
typedef ap_uint< 16 > LE_UdpPort
 
typedef ap_uint< 16 > LE_UdpLen
 
typedef ap_uint< 16 > LE_UdpCsum
 
typedef LE_tData LE_UdpData
 
typedef ap_uint< 16 > UdpSrcPort
 
typedef ap_uint< 16 > UdpDstPort
 
typedef ap_uint< 16 > UdpPort
 
typedef ap_uint< 16 > UdpLen
 
typedef ap_uint< 16 > UdpCsum
 
typedef tData UdpData
 
typedef tDataHalf UdpDataHi
 
typedef tDataHalf UdpDataLo
 
typedef ap_uint< 16 > UdpDgmLen
 
typedef ap_uint< 16 > UdpDatLen
 

Detailed Description

: A class to access UDP header fields within data chunks transmitted over an AXI4-Stream interface.

System: : cloudFPGA Component : Shell, Network Transport Stack (NTS) Language : Vivado HLS

: The User Datagram Protocol (UDP) fields defined in this class refer to the format generated by the 10GbE MAC of Xilinx which organizes its two 64-bit Rx and Tx interfaces into 8 lanes (see PG157). The result of this division into lanes, is that the UDP fields end up being stored in LITTLE-ENDIAN order instead of the initial BIG-ENDIAN order used to transmit bytes over the physical media. As an example, assume that the 16 bits of the UDP "Checksum" datagram has a value of '0xA1B2'. This field will be transmitted on the media in big-endian order .i.e, a '0xA1' followed by '0xB2'. However, this field will end up being ordered in little-endian mode (.i.e, 0xB2A1) by the AXI4-Stream interface of the 10GbE MAC.

Therefore, the format of a UDP datagram transferred over an AXI4-Stream interface of quadwords is done in LITTLE-ENDIAN and is mapped as follows: 

   6                   5                   4                   3                   2                   1                   0

3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | Checksum | Length | Destination Port | Source Port | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | Data | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+

@info: What's this Little-Endian(LE) vs Big-Endian(BE) anyhow. FYI - The original source from Xilinx (available at: https://github.com/Xilinx/HLx_Examples/tree/master/Acceleration/tcp_ip) is entirely coded with respect to the above mapping of the media network stream over a 64-bits interface in little-endian oder. This makes the initial code particularly difficult to read, maintain and test. Therefore, this class implements a set of methods to hide this complexity by accessing a raw Axis data streams as if it was encoded in the expected big-endian order.

Warning
: This class is to be used when a UDP datagram is aligned to a 64-bit quadword. Refer to the methods of 'AxisIp4.hpp' to access the fields of a UDP datagram that is embedded into an IPv4 packet, or the the methods of 'AxisEth.hpp' to access the fields of an UDP datagram that is embedded into an IPv4 packet further embedded into an Ethernet frame.

Definition in file AxisUdp.hpp.