cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
Role.vhdl
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2 -- * Copyright 2016 -- 2021 IBM Corporation
3 -- *
4 -- * Licensed under the Apache License, Version 2.0 (the "License");
5 -- * you may not use this file except in compliance with the License.
6 -- * You may obtain a copy of the License at
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9 -- *
10 -- * Unless required by applicable law or agreed to in writing, software
11 -- * distributed under the License is distributed on an "AS IS" BASIS,
12 -- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 -- * See the License for the specific language governing permissions and
14 -- * limitations under the License.
15 -- *******************************************************************************
16 
17 
18 -- *
19 -- * cloudFPGA
20 -- * =============================================
21 -- * Created: Apr 2019
22 -- * Authors: FAB, WEI, NGL
23 -- *
24 -- * Description:
25 -- * ROLE template for Themisto SRA
26 -- *
27 
28 library IEEE;
29 use IEEE.std_logic_1164.all;
30 use IEEE.numeric_std.all;
31 
32 library UNISIM;
33 use UNISIM.vcomponents.all;
34 
35 -- library XIL_DEFAULTLIB;
36 -- use XIL_DEFAULTLIB.all;
37 
38 
39 --******************************************************************************
40 --** ENTITY ** FMKU60 ROLE
41 --******************************************************************************
42 
43 entity Role_Themisto is
44  port (
45 
46  --------------------------------------------------------
47  -- SHELL / Global Input Clock and Reset Interface
48  --------------------------------------------------------
49  piSHL_156_25Clk : in std_ulogic;
50  piSHL_156_25Rst : in std_ulogic;
51  -- LY7 Enable and Reset
52  piMMIO_Ly7_Rst : in std_ulogic;
53  piMMIO_Ly7_En : in std_ulogic;
54 
55  ------------------------------------------------------
56  -- SHELL / Role / Nts0 / Udp Interface
57  ------------------------------------------------------
58  ---- Input AXI-Write Stream Interface ----------
59  siNRC_Udp_Data_tdata : in std_ulogic_vector( 63 downto 0);
60  siNRC_Udp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
61  siNRC_Udp_Data_tvalid : in std_ulogic;
62  siNRC_Udp_Data_tlast : in std_ulogic;
63  siNRC_Udp_Data_tready : out std_ulogic;
64  ---- Output AXI-Write Stream Interface ---------
65  soNRC_Udp_Data_tdata : out std_ulogic_vector( 63 downto 0);
66  soNRC_Udp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
67  soNRC_Udp_Data_tvalid : out std_ulogic;
68  soNRC_Udp_Data_tlast : out std_ulogic;
69  soNRC_Udp_Data_tready : in std_ulogic;
70  -- Open Port vector
71  poROL_Nrc_Udp_Rx_ports : out std_ulogic_vector( 31 downto 0);
72  -- ROLE <-> NRC Meta Interface
73  soROLE_Nrc_Udp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
74  soROLE_Nrc_Udp_Meta_TVALID : out std_ulogic;
75  soROLE_Nrc_Udp_Meta_TREADY : in std_ulogic;
76  soROLE_Nrc_Udp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
77  soROLE_Nrc_Udp_Meta_TLAST : out std_ulogic;
78  siNRC_Role_Udp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
79  siNRC_Role_Udp_Meta_TVALID : in std_ulogic;
80  siNRC_Role_Udp_Meta_TREADY : out std_ulogic;
81  siNRC_Role_Udp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
82  siNRC_Role_Udp_Meta_TLAST : in std_ulogic;
83 
84  ------------------------------------------------------
85  -- SHELL / Role / Nts0 / Tcp Interface
86  ------------------------------------------------------
87  ---- Input AXI-Write Stream Interface ----------
88  siNRC_Tcp_Data_tdata : in std_ulogic_vector( 63 downto 0);
89  siNRC_Tcp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
90  siNRC_Tcp_Data_tvalid : in std_ulogic;
91  siNRC_Tcp_Data_tlast : in std_ulogic;
92  siNRC_Tcp_Data_tready : out std_ulogic;
93  ---- Output AXI-Write Stream Interface ---------
94  soNRC_Tcp_Data_tdata : out std_ulogic_vector( 63 downto 0);
95  soNRC_Tcp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
96  soNRC_Tcp_Data_tvalid : out std_ulogic;
97  soNRC_Tcp_Data_tlast : out std_ulogic;
98  soNRC_Tcp_Data_tready : in std_ulogic;
99  -- Open Port vector
100  poROL_Nrc_Tcp_Rx_ports : out std_ulogic_vector( 31 downto 0);
101  -- ROLE <-> NRC Meta Interface
102  soROLE_Nrc_Tcp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
103  soROLE_Nrc_Tcp_Meta_TVALID : out std_ulogic;
104  soROLE_Nrc_Tcp_Meta_TREADY : in std_ulogic;
105  soROLE_Nrc_Tcp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
106  soROLE_Nrc_Tcp_Meta_TLAST : out std_ulogic;
107  siNRC_Role_Tcp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
108  siNRC_Role_Tcp_Meta_TVALID : in std_ulogic;
109  siNRC_Role_Tcp_Meta_TREADY : out std_ulogic;
110  siNRC_Role_Tcp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
111  siNRC_Role_Tcp_Meta_TLAST : in std_ulogic;
112 
113 
114  --------------------------------------------------------
115  -- SHELL / Mem / Mp0 Interface
116  --------------------------------------------------------
117  ---- Memory Port #0 / S2MM-AXIS ----------------
118  ------ Stream Read Command ---------
119  soMEM_Mp0_RdCmd_tdata : out std_ulogic_vector( 79 downto 0);
120  soMEM_Mp0_RdCmd_tvalid : out std_ulogic;
121  soMEM_Mp0_RdCmd_tready : in std_ulogic;
122  ------ Stream Read Status ----------
123  siMEM_Mp0_RdSts_tdata : in std_ulogic_vector( 7 downto 0);
124  siMEM_Mp0_RdSts_tvalid : in std_ulogic;
125  siMEM_Mp0_RdSts_tready : out std_ulogic;
126  ------ Stream Data Input Channel ---
127  siMEM_Mp0_Read_tdata : in std_ulogic_vector(511 downto 0);
128  siMEM_Mp0_Read_tkeep : in std_ulogic_vector( 63 downto 0);
129  siMEM_Mp0_Read_tlast : in std_ulogic;
130  siMEM_Mp0_Read_tvalid : in std_ulogic;
131  siMEM_Mp0_Read_tready : out std_ulogic;
132  ------ Stream Write Command --------
133  soMEM_Mp0_WrCmd_tdata : out std_ulogic_vector( 79 downto 0);
134  soMEM_Mp0_WrCmd_tvalid : out std_ulogic;
135  soMEM_Mp0_WrCmd_tready : in std_ulogic;
136  ------ Stream Write Status ---------
137  siMEM_Mp0_WrSts_tdata : in std_ulogic_vector( 7 downto 0);
138  siMEM_Mp0_WrSts_tvalid : in std_ulogic;
139  siMEM_Mp0_WrSts_tready : out std_ulogic;
140  ------ Stream Data Output Channel --
141  soMEM_Mp0_Write_tdata : out std_ulogic_vector(511 downto 0);
142  soMEM_Mp0_Write_tkeep : out std_ulogic_vector( 63 downto 0);
143  soMEM_Mp0_Write_tlast : out std_ulogic;
144  soMEM_Mp0_Write_tvalid : out std_ulogic;
145  soMEM_Mp0_Write_tready : in std_ulogic;
146 
147  --------------------------------------------------------
148  -- SHELL / Mem / Mp1 Interface
149  --------------------------------------------------------
150  moMEM_Mp1_AWID : out std_ulogic_vector(7 downto 0);
151  moMEM_Mp1_AWADDR : out std_ulogic_vector(32 downto 0);
152  moMEM_Mp1_AWLEN : out std_ulogic_vector(7 downto 0);
153  moMEM_Mp1_AWSIZE : out std_ulogic_vector(2 downto 0);
154  moMEM_Mp1_AWBURST : out std_ulogic_vector(1 downto 0);
155  moMEM_Mp1_AWVALID : out std_ulogic;
156  moMEM_Mp1_AWREADY : in std_ulogic;
157  moMEM_Mp1_WDATA : out std_ulogic_vector(511 downto 0);
158  moMEM_Mp1_WSTRB : out std_ulogic_vector(63 downto 0);
159  moMEM_Mp1_WLAST : out std_ulogic;
160  moMEM_Mp1_WVALID : out std_ulogic;
161  moMEM_Mp1_WREADY : in std_ulogic;
162  moMEM_Mp1_BID : in std_ulogic_vector(7 downto 0);
163  moMEM_Mp1_BRESP : in std_ulogic_vector(1 downto 0);
164  moMEM_Mp1_BVALID : in std_ulogic;
165  moMEM_Mp1_BREADY : out std_ulogic;
166  moMEM_Mp1_ARID : out std_ulogic_vector(7 downto 0);
167  moMEM_Mp1_ARADDR : out std_ulogic_vector(32 downto 0);
168  moMEM_Mp1_ARLEN : out std_ulogic_vector(7 downto 0);
169  moMEM_Mp1_ARSIZE : out std_ulogic_vector(2 downto 0);
170  moMEM_Mp1_ARBURST : out std_ulogic_vector(1 downto 0);
171  moMEM_Mp1_ARVALID : out std_ulogic;
172  moMEM_Mp1_ARREADY : in std_ulogic;
173  moMEM_Mp1_RID : in std_ulogic_vector(7 downto 0);
174  moMEM_Mp1_RDATA : in std_ulogic_vector(511 downto 0);
175  moMEM_Mp1_RRESP : in std_ulogic_vector(1 downto 0);
176  moMEM_Mp1_RLAST : in std_ulogic;
177  moMEM_Mp1_RVALID : in std_ulogic;
178  moMEM_Mp1_RREADY : out std_ulogic;
179 
180  ---- [APP_RDROL] -------------------
181  -- to be use as ROLE VERSION IDENTIFICATION --
182  poSHL_Mmio_RdReg : out std_ulogic_vector( 15 downto 0);
183 
184  --------------------------------------------------------
185  -- TOP : Secondary Clock (Asynchronous)
186  --------------------------------------------------------
187  piTOP_250_00Clk : in std_ulogic; -- Freerunning
188 
189  ------------------------------------------------
190  -- FMC Interface
191  ------------------------------------------------
192  piFMC_ROLE_rank : in std_logic_vector(31 downto 0);
193  piFMC_ROLE_size : in std_logic_vector(31 downto 0);
194 
195  ------------------------------------------------
196  -- DEBUG PORTS (see UG909)
197  ------------------------------------------------
198  dpBSCAN_drck : in std_logic;
199  dpBSCAN_shift : in std_logic;
200  dpBSCAN_tdi : in std_logic;
201  dpBSCAN_update : in std_logic;
202  dpBSCAN_sel : in std_logic;
203  dpBSCAN_tdo : out std_logic;
204  dpBSCAN_tms : in std_logic;
205  dpBSCAN_tck : in std_logic;
206  dpBSCAN_runtest : in std_logic;
207  dpBSCAN_reset : in std_logic;
208  dpBSCAN_capture : in std_logic;
209  dpBSCAN_bscanid_en : in std_logic;
210 
211  poVoid : out std_ulogic
212 
213  );
214 
215 end Role_Themisto;
216 
217 
218 -- *****************************************************************************
219 -- ** ARCHITECTURE ** APP of ROLE_THEMISTO
220 -- *****************************************************************************
221 
222 architecture App of Role_Themisto is
223 
224  --============================================================================
225  -- DEBUG SIGNALS ATTRIBUTE DECLARATIONS (see UG909)
226  --============================================================================
227  attribute X_INTERFACE_INFO : string;
228  attribute DEBUG : string;
229  attribute X_INTERFACE_INFO of dpBSCAN_drck: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN drck";
230  attribute DEBUG of dpBSCAN_drck: signal is "true";
231  attribute X_INTERFACE_INFO of dpBSCAN_shift: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN shift";
232  attribute DEBUG of dpBSCAN_shift: signal is "true";
233  attribute X_INTERFACE_INFO of dpBSCAN_tdi: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN tdi";
234  attribute DEBUG of dpBSCAN_tdi: signal is "true";
235  attribute X_INTERFACE_INFO of dpBSCAN_update: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN update";
236  attribute DEBUG of dpBSCAN_update: signal is "true";
237  attribute X_INTERFACE_INFO of dpBSCAN_sel: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN sel";
238  attribute DEBUG of dpBSCAN_sel: signal is "true";
239  attribute X_INTERFACE_INFO of dpBSCAN_tdo: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN tdo";
240  attribute DEBUG of dpBSCAN_tdo: signal is "true";
241  attribute X_INTERFACE_INFO of dpBSCAN_tms: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN tms";
242  attribute DEBUG of dpBSCAN_tms: signal is "true";
243  attribute X_INTERFACE_INFO of dpBSCAN_tck: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN tck";
244  attribute DEBUG of dpBSCAN_tck: signal is "true";
245  attribute X_INTERFACE_INFO of dpBSCAN_runtest: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN runtest";
246  attribute DEBUG of dpBSCAN_runtest: signal is "true";
247  attribute X_INTERFACE_INFO of dpBSCAN_reset: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN reset";
248  attribute DEBUG of dpBSCAN_reset: signal is "true";
249  attribute X_INTERFACE_INFO of dpBSCAN_capture: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN capture";
250  attribute DEBUG of dpBSCAN_capture: signal is "true";
251  attribute X_INTERFACE_INFO of dpBSCAN_bscanid_en: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN bscanid_en";
252  attribute DEBUG of dpBSCAN_bscanid_en: signal is "true";
253 
254  --============================================================================
255  -- SIGNAL DECLARATIONS
256  --============================================================================
257 
258  --============================================================================
259  -- VARIABLE DECLARATIONS
260  --============================================================================
261 
262  --===========================================================================
263  --== COMPONENT DECLARATIONS
264  --===========================================================================
265 
266 --################################################################################
267 --# #
268 --# ##### #### #### # # #
269 --# # # # # # # # # #
270 --# # # # # # # ### #
271 --# ##### # # # # # #
272 --# # # # # # # # #
273 --# # # # # # # # #
274 --# ##### #### #### # #
275 --# #
276 --################################################################################
277 
278 begin
279 
280 
281 end architecture App;
282 
283 
Role_Themisto
Definition: Role.vhdl:43
Role_Themisto.soNRC_Tcp_Data_tready
in soNRC_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:98
Role_Themisto.moMEM_Mp1_ARSIZE
out moMEM_Mp1_ARSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:169
Role_Themisto.moMEM_Mp1_AWADDR
out moMEM_Mp1_AWADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:151
Role_Themisto.soNRC_Udp_Data_tdata
out soNRC_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:65
Role_Themisto.soROLE_Nrc_Udp_Meta_TREADY
in soROLE_Nrc_Udp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:75
Role_Themisto.piSHL_156_25Clk
in piSHL_156_25Clkstd_ulogic
Definition: Role.vhdl:49
Role_Themisto.moMEM_Mp1_RREADY
out moMEM_Mp1_RREADYstd_ulogic
Definition: Role.vhdl:178
Role_Themisto.soROLE_Nrc_Udp_Meta_TKEEP
out soROLE_Nrc_Udp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:76
Role_Themisto.piSHL_156_25Rst
in piSHL_156_25Rststd_ulogic
Definition: Role.vhdl:50
Role_Themisto.dpBSCAN_tdi
in dpBSCAN_tdistd_logic
Definition: Role.vhdl:200
Role_Themisto.moMEM_Mp1_RLAST
in moMEM_Mp1_RLASTstd_ulogic
Definition: Role.vhdl:176
Role_Themisto.siNRC_Udp_Data_tlast
in siNRC_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:62
Role_Themisto.siMEM_Mp0_Read_tready
out siMEM_Mp0_Read_treadystd_ulogic
Definition: Role.vhdl:131
Role_Themisto.siNRC_Role_Udp_Meta_TKEEP
in siNRC_Role_Udp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:81
Role_Themisto.siMEM_Mp0_Read_tkeep
in siMEM_Mp0_Read_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:128
Role_Themisto.dpBSCAN_reset
in dpBSCAN_resetstd_logic
Definition: Role.vhdl:207
Role_Themisto.dpBSCAN_sel
in dpBSCAN_selstd_logic
Definition: Role.vhdl:202
Role_Themisto.dpBSCAN_drck
in dpBSCAN_drckstd_logic
Definition: Role.vhdl:198
Role_Themisto.soNRC_Tcp_Data_tdata
out soNRC_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:94
Role_Themisto.soROLE_Nrc_Tcp_Meta_TREADY
in soROLE_Nrc_Tcp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:104
Role_Themisto.siNRC_Role_Tcp_Meta_TLAST
in siNRC_Role_Tcp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:111
Role_Themisto.siMEM_Mp0_WrSts_tdata
in siMEM_Mp0_WrSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:137
Role_Themisto.soMEM_Mp0_Write_tkeep
out soMEM_Mp0_Write_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:142
Role_Themisto.siNRC_Tcp_Data_tready
out siNRC_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:92
Role_Themisto.siNRC_Role_Udp_Meta_TDATA
in siNRC_Role_Udp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:78
Role_Themisto.moMEM_Mp1_AWVALID
out moMEM_Mp1_AWVALIDstd_ulogic
Definition: Role.vhdl:155
Role_Themisto.siNRC_Role_Tcp_Meta_TVALID
in siNRC_Role_Tcp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:108
Role_Themisto.siNRC_Role_Tcp_Meta_TDATA
in siNRC_Role_Tcp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:107
Role_Themisto.moMEM_Mp1_BVALID
in moMEM_Mp1_BVALIDstd_ulogic
Definition: Role.vhdl:164
Role_Themisto.moMEM_Mp1_WSTRB
out moMEM_Mp1_WSTRBstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:158
Role_Themisto.moMEM_Mp1_BREADY
out moMEM_Mp1_BREADYstd_ulogic
Definition: Role.vhdl:165
Role_Themisto.moMEM_Mp1_AWID
out moMEM_Mp1_AWIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:150
Role_Themisto.moMEM_Mp1_RVALID
in moMEM_Mp1_RVALIDstd_ulogic
Definition: Role.vhdl:177
Role_Themisto.soNRC_Udp_Data_tready
in soNRC_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:69
Role_Themisto.soMEM_Mp0_WrCmd_tready
in soMEM_Mp0_WrCmd_treadystd_ulogic
Definition: Role.vhdl:135
Role_Themisto.siNRC_Udp_Data_tvalid
in siNRC_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:61
Role_Themisto.piMMIO_Ly7_En
in piMMIO_Ly7_Enstd_ulogic
Definition: Role.vhdl:53
Role_Themisto.soMEM_Mp0_Write_tready
in soMEM_Mp0_Write_treadystd_ulogic
Definition: Role.vhdl:145
Role_Themisto.soNRC_Udp_Data_tlast
out soNRC_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:68
Role_Themisto.soROLE_Nrc_Udp_Meta_TVALID
out soROLE_Nrc_Udp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:74
Role_Themisto.soROLE_Nrc_Tcp_Meta_TVALID
out soROLE_Nrc_Tcp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:103
Role_Themisto.moMEM_Mp1_WLAST
out moMEM_Mp1_WLASTstd_ulogic
Definition: Role.vhdl:159
Role_Themisto.soNRC_Udp_Data_tvalid
out soNRC_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:67
Role_Themisto.moMEM_Mp1_WDATA
out moMEM_Mp1_WDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:157
Role_Themisto.siNRC_Tcp_Data_tdata
in siNRC_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:88
Role_Themisto.soMEM_Mp0_RdCmd_tdata
out soMEM_Mp0_RdCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:119
Role_Themisto.siMEM_Mp0_Read_tdata
in siMEM_Mp0_Read_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:127
Role_Themisto.soMEM_Mp0_Write_tdata
out soMEM_Mp0_Write_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:141
Role_Themisto.siMEM_Mp0_RdSts_tready
out siMEM_Mp0_RdSts_treadystd_ulogic
Definition: Role.vhdl:125
Role_Themisto.moMEM_Mp1_ARBURST
out moMEM_Mp1_ARBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:170
Role_Themisto.siNRC_Role_Tcp_Meta_TKEEP
in siNRC_Role_Tcp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:110
Role_Themisto.siMEM_Mp0_RdSts_tdata
in siMEM_Mp0_RdSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:123
Role_Themisto.poROL_Nrc_Tcp_Rx_ports
out poROL_Nrc_Tcp_Rx_portsstd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:100
Role_Themisto.siNRC_Tcp_Data_tvalid
in siNRC_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:90
Role_Themisto.siNRC_Role_Udp_Meta_TLAST
in siNRC_Role_Udp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:82
Role_Themisto.moMEM_Mp1_ARREADY
in moMEM_Mp1_ARREADYstd_ulogic
Definition: Role.vhdl:172
Role_Themisto.siNRC_Udp_Data_tready
out siNRC_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:63
Role_Themisto.dpBSCAN_tms
in dpBSCAN_tmsstd_logic
Definition: Role.vhdl:204
Role_Themisto.moMEM_Mp1_RRESP
in moMEM_Mp1_RRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:175
Role_Themisto.soMEM_Mp0_Write_tlast
out soMEM_Mp0_Write_tlaststd_ulogic
Definition: Role.vhdl:143
Role_Themisto.moMEM_Mp1_ARID
out moMEM_Mp1_ARIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:166
Role_Themisto.dpBSCAN_capture
in dpBSCAN_capturestd_logic
Definition: Role.vhdl:208
Role_Themisto.soMEM_Mp0_WrCmd_tvalid
out soMEM_Mp0_WrCmd_tvalidstd_ulogic
Definition: Role.vhdl:134
Role_Themisto.moMEM_Mp1_ARVALID
out moMEM_Mp1_ARVALIDstd_ulogic
Definition: Role.vhdl:171
Role_Themisto.soROLE_Nrc_Tcp_Meta_TDATA
out soROLE_Nrc_Tcp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:102
Role_Themisto.moMEM_Mp1_AWBURST
out moMEM_Mp1_AWBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:154
Role_Themisto.siNRC_Udp_Data_tkeep
in siNRC_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:60
Role_Themisto.soMEM_Mp0_RdCmd_tvalid
out soMEM_Mp0_RdCmd_tvalidstd_ulogic
Definition: Role.vhdl:120
Role_Themisto.soNRC_Tcp_Data_tkeep
out soNRC_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:95
Role_Themisto.siMEM_Mp0_Read_tvalid
in siMEM_Mp0_Read_tvalidstd_ulogic
Definition: Role.vhdl:130
Role_Themisto.dpBSCAN_bscanid_en
in dpBSCAN_bscanid_enstd_logic
Definition: Role.vhdl:209
Role_Themisto.dpBSCAN_tdo
out dpBSCAN_tdostd_logic
Definition: Role.vhdl:203
Role_Themisto.moMEM_Mp1_RID
in moMEM_Mp1_RIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:173
Role_Themisto.soROLE_Nrc_Udp_Meta_TDATA
out soROLE_Nrc_Udp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:73
Role_Themisto.piFMC_ROLE_rank
in piFMC_ROLE_rankstd_logic_vector(31 downto 0)
Definition: Role.vhdl:192
Role_Themisto.soROLE_Nrc_Tcp_Meta_TKEEP
out soROLE_Nrc_Tcp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:105
Role_Themisto.piTOP_250_00Clk
in piTOP_250_00Clkstd_ulogic
Definition: Role.vhdl:187
Role_Themisto.moMEM_Mp1_AWLEN
out moMEM_Mp1_AWLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:152
Role_Themisto.piFMC_ROLE_size
in piFMC_ROLE_sizestd_logic_vector(31 downto 0)
Definition: Role.vhdl:193
Role_Themisto.siNRC_Tcp_Data_tkeep
in siNRC_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:89
Role_Themisto.soMEM_Mp0_RdCmd_tready
in soMEM_Mp0_RdCmd_treadystd_ulogic
Definition: Role.vhdl:121
Role_Themisto.moMEM_Mp1_WREADY
in moMEM_Mp1_WREADYstd_ulogic
Definition: Role.vhdl:161
Role_Themisto.siNRC_Role_Udp_Meta_TREADY
out siNRC_Role_Udp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:80
Role_Themisto.soNRC_Tcp_Data_tlast
out soNRC_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:97
Role_Themisto.siMEM_Mp0_RdSts_tvalid
in siMEM_Mp0_RdSts_tvalidstd_ulogic
Definition: Role.vhdl:124
Role_Themisto.soROLE_Nrc_Udp_Meta_TLAST
out soROLE_Nrc_Udp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:77
Role_Themisto.moMEM_Mp1_AWSIZE
out moMEM_Mp1_AWSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:153
Role_Themisto.dpBSCAN_shift
in dpBSCAN_shiftstd_logic
Definition: Role.vhdl:199
Role_Themisto.moMEM_Mp1_RDATA
in moMEM_Mp1_RDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:174
Role_Themisto.moMEM_Mp1_BID
in moMEM_Mp1_BIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:162
Role_Themisto.soMEM_Mp0_WrCmd_tdata
out soMEM_Mp0_WrCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:133
Role_Themisto.piMMIO_Ly7_Rst
in piMMIO_Ly7_Rststd_ulogic
Definition: Role.vhdl:52
Role_Themisto.poSHL_Mmio_RdReg
out poSHL_Mmio_RdRegstd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:182
Role_Themisto.siNRC_Role_Tcp_Meta_TREADY
out siNRC_Role_Tcp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:109
Role_Themisto.siNRC_Role_Udp_Meta_TVALID
in siNRC_Role_Udp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:79
Role_Themisto.moMEM_Mp1_BRESP
in moMEM_Mp1_BRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:163
Role_Themisto.moMEM_Mp1_WVALID
out moMEM_Mp1_WVALIDstd_ulogic
Definition: Role.vhdl:160
Role_Themisto.dpBSCAN_update
in dpBSCAN_updatestd_logic
Definition: Role.vhdl:201
Role_Themisto.siNRC_Udp_Data_tdata
in siNRC_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:59
Role_Themisto.moMEM_Mp1_ARLEN
out moMEM_Mp1_ARLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:168
Role_Themisto.soROLE_Nrc_Tcp_Meta_TLAST
out soROLE_Nrc_Tcp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:106
Role_Themisto.soNRC_Udp_Data_tkeep
out soNRC_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:66
Role_Themisto.siNRC_Tcp_Data_tlast
in siNRC_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:91
Role_Themisto.siMEM_Mp0_WrSts_tready
out siMEM_Mp0_WrSts_treadystd_ulogic
Definition: Role.vhdl:139
Role_Themisto.dpBSCAN_runtest
in dpBSCAN_runteststd_logic
Definition: Role.vhdl:206
Role_Themisto.siMEM_Mp0_WrSts_tvalid
in siMEM_Mp0_WrSts_tvalidstd_ulogic
Definition: Role.vhdl:138
Role_Themisto.soMEM_Mp0_Write_tvalid
out soMEM_Mp0_Write_tvalidstd_ulogic
Definition: Role.vhdl:144
Role_Themisto.moMEM_Mp1_ARADDR
out moMEM_Mp1_ARADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:167
Role_Themisto.poVoid
out poVoidstd_ulogic
Definition: Role.vhdl:213
Role_Themisto.moMEM_Mp1_AWREADY
in moMEM_Mp1_AWREADYstd_ulogic
Definition: Role.vhdl:156
Role_Themisto.poROL_Nrc_Udp_Rx_ports
out poROL_Nrc_Udp_Rx_portsstd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:71
Role_Themisto.siMEM_Mp0_Read_tlast
in siMEM_Mp0_Read_tlaststd_ulogic
Definition: Role.vhdl:129
Role_Themisto.dpBSCAN_tck
in dpBSCAN_tckstd_logic
Definition: Role.vhdl:205
Role_Themisto.soNRC_Tcp_Data_tvalid
out soNRC_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:96