cloudFPGA (cF) API
1.0
The documentation of the source code of cloudFPGA (cF)
|
#include <stdint.h>
#include <stdio.h>
#include <hls_stream.h>
#include "ap_int.h"
#include "dynamic.hpp"
Go to the source code of this file.
Classes | |
struct | Axis< D > |
struct | DmCmd |
struct | DmSts |
Macros | |
#define | FSM_IDLE 0 |
#define | FSM_WR_PAT_CMD 1 |
#define | FSM_WR_PAT_DATA 2 |
#define | FSM_WR_PAT_STS 3 |
#define | FSM_RD_PAT_CMD 4 |
#define | FSM_RD_PAT_DATA 5 |
#define | FSM_RD_PAT_STS 6 |
#define | FSM_WR_ANTI_CMD 7 |
#define | FSM_WR_ANTI_DATA 8 |
#define | FSM_WR_ANTI_STS 9 |
#define | FSM_RD_ANTI_CMD 10 |
#define | FSM_RD_ANTI_DATA 11 |
#define | FSM_RD_ANTI_STS 12 |
#define | PHASE_IDLE 0 |
#define | PHASE_RAMP_WRITE 1 |
#define | PHASE_RAMP_READ 2 |
#define | PHASE_STRESS 3 |
#define | MEM_START_ADDR 0x000000000 |
#define | CHECK_CHUNK_SIZE 0x1000 |
#define | BYTE_PER_MEM_WORD 64 |
#define | TRANSFERS_PER_CHUNK (CHECK_CHUNK_SIZE/BYTE_PER_MEM_WORD) |
#define | CYCLES_UNTIL_TIMEOUT 0x1000 |
Functions | |
void | mem_test_flash_main (ap_uint< 1 > sys_reset, ap_uint< 2 > DIAG_CTRL_IN, ap_uint< 2 > *DIAG_STAT_OUT, ap_uint< 16 > *debug_out, hls::stream< DmCmd > &soMemRdCmdP0, hls::stream< DmSts > &siMemRdStsP0, hls::stream< Axis< 512 > > &siMemReadP0, hls::stream< DmCmd > &soMemWrCmdP0, hls::stream< DmSts > &siMemWrStsP0, hls::stream< Axis< 512 > > &soMemWriteP0) |
#define BYTE_PER_MEM_WORD 64 |
Definition at line 81 of file mem_test_flash.hpp.
#define CHECK_CHUNK_SIZE 0x1000 |
Definition at line 80 of file mem_test_flash.hpp.
#define CYCLES_UNTIL_TIMEOUT 0x1000 |
Definition at line 86 of file mem_test_flash.hpp.
#define FSM_IDLE 0 |
Copyright 2016 – 2021 IBM Corporation
Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
Definition at line 44 of file mem_test_flash.hpp.
#define FSM_RD_ANTI_CMD 10 |
Definition at line 54 of file mem_test_flash.hpp.
#define FSM_RD_ANTI_DATA 11 |
Definition at line 55 of file mem_test_flash.hpp.
#define FSM_RD_ANTI_STS 12 |
Definition at line 56 of file mem_test_flash.hpp.
#define FSM_RD_PAT_CMD 4 |
Definition at line 48 of file mem_test_flash.hpp.
#define FSM_RD_PAT_DATA 5 |
Definition at line 49 of file mem_test_flash.hpp.
#define FSM_RD_PAT_STS 6 |
Definition at line 50 of file mem_test_flash.hpp.
#define FSM_WR_ANTI_CMD 7 |
Definition at line 51 of file mem_test_flash.hpp.
#define FSM_WR_ANTI_DATA 8 |
Definition at line 52 of file mem_test_flash.hpp.
#define FSM_WR_ANTI_STS 9 |
Definition at line 53 of file mem_test_flash.hpp.
#define FSM_WR_PAT_CMD 1 |
Definition at line 45 of file mem_test_flash.hpp.
#define FSM_WR_PAT_DATA 2 |
Definition at line 46 of file mem_test_flash.hpp.
#define FSM_WR_PAT_STS 3 |
Definition at line 47 of file mem_test_flash.hpp.
#define MEM_START_ADDR 0x000000000 |
Definition at line 66 of file mem_test_flash.hpp.
#define PHASE_IDLE 0 |
Definition at line 60 of file mem_test_flash.hpp.
#define PHASE_RAMP_READ 2 |
Definition at line 62 of file mem_test_flash.hpp.
#define PHASE_RAMP_WRITE 1 |
Definition at line 61 of file mem_test_flash.hpp.
#define PHASE_STRESS 3 |
Definition at line 63 of file mem_test_flash.hpp.
#define TRANSFERS_PER_CHUNK (CHECK_CHUNK_SIZE/BYTE_PER_MEM_WORD) |
Definition at line 82 of file mem_test_flash.hpp.
void mem_test_flash_main | ( | ap_uint< 1 > | sys_reset, |
ap_uint< 2 > | DIAG_CTRL_IN, | ||
ap_uint< 2 > * | DIAG_STAT_OUT, | ||
ap_uint< 16 > * | debug_out, | ||
hls::stream< DmCmd > & | soMemRdCmdP0, | ||
hls::stream< DmSts > & | siMemRdStsP0, | ||
hls::stream< Axis< 512 > > & | siMemReadP0, | ||
hls::stream< DmCmd > & | soMemWrCmdP0, | ||
hls::stream< DmSts > & | siMemWrStsP0, | ||
hls::stream< Axis< 512 > > & | soMemWriteP0 | ||
) |