cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
Role.vhdl
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1 /*
2  * Copyright 2016 -- 2022 IBM Corporation
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 -- *****************************************************************************
18 -- *
19 -- * Title : Role template for the 'Themisto' shell of the FMKU60.
20 -- *
21 -- * File : Role.vhdl
22 -- *
23 -- * Tools : Vivado v2016.4, v2017.4, v2019.2 (64-bit)
24 -- *
25 -- * Description : In cloudFPGA, the user application is referred to as a 'role'
26 -- * and is integrated along with a 'shell' that abstracts the HW components
27 -- * of the FPGA module.
28 -- * The current role implements 2 typical UDP and TCP applications and pairs
29 -- * paires them with the shell 'Themisto'.
30 -- *
31 -- *****************************************************************************
32 
33 --******************************************************************************
34 --** CONTEXT CLAUSE ** FMKU60 ROLE(Flash)
35 --******************************************************************************
36 library IEEE;
37 use IEEE.std_logic_1164.all;
38 use IEEE.numeric_std.all;
39 
40 library UNISIM;
41 use UNISIM.vcomponents.all;
42 
43 
44 --******************************************************************************
45 --** ENTITY ** ROLE_THEMISTO
46 --******************************************************************************
47 
48 entity Role_Themisto is
49  port (
50 
51  --------------------------------------------------------
52  -- SHELL / Global Input Clock and Reset Interface
53  --------------------------------------------------------
54  piSHL_156_25Clk : in std_ulogic;
55  piSHL_156_25Rst : in std_ulogic;
56  -- LY7 Enable and Reset
57  piMMIO_Ly7_Rst : in std_ulogic;
58  piMMIO_Ly7_En : in std_ulogic;
59 
60  ------------------------------------------------------
61  -- SHELL / Role / Nts0 / Udp Interface
62  ------------------------------------------------------
63  ---- Input AXI-Write Stream Interface ----------
64  siNRC_Udp_Data_tdata : in std_ulogic_vector( 63 downto 0);
65  siNRC_Udp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
66  siNRC_Udp_Data_tvalid : in std_ulogic;
67  siNRC_Udp_Data_tlast : in std_ulogic;
68  siNRC_Udp_Data_tready : out std_ulogic;
69  ---- Output AXI-Write Stream Interface ---------
70  soNRC_Udp_Data_tdata : out std_ulogic_vector( 63 downto 0);
71  soNRC_Udp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
72  soNRC_Udp_Data_tvalid : out std_ulogic;
73  soNRC_Udp_Data_tlast : out std_ulogic;
74  soNRC_Udp_Data_tready : in std_ulogic;
75  -- Open Port vector
76  poROL_Nrc_Udp_Rx_ports : out std_ulogic_vector( 31 downto 0);
77  -- ROLE <-> NRC Meta Interface
78  soROLE_Nrc_Udp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
79  soROLE_Nrc_Udp_Meta_TVALID : out std_ulogic;
80  soROLE_Nrc_Udp_Meta_TREADY : in std_ulogic;
81  soROLE_Nrc_Udp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
82  soROLE_Nrc_Udp_Meta_TLAST : out std_ulogic;
83  siNRC_Role_Udp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
84  siNRC_Role_Udp_Meta_TVALID : in std_ulogic;
85  siNRC_Role_Udp_Meta_TREADY : out std_ulogic;
86  siNRC_Role_Udp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
87  siNRC_Role_Udp_Meta_TLAST : in std_ulogic;
88 
89  ------------------------------------------------------
90  -- SHELL / Role / Nts0 / Tcp Interface
91  ------------------------------------------------------
92  ---- Input AXI-Write Stream Interface ----------
93  siNRC_Tcp_Data_tdata : in std_ulogic_vector( 63 downto 0);
94  siNRC_Tcp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
95  siNRC_Tcp_Data_tvalid : in std_ulogic;
96  siNRC_Tcp_Data_tlast : in std_ulogic;
97  siNRC_Tcp_Data_tready : out std_ulogic;
98  ---- Output AXI-Write Stream Interface ---------
99  soNRC_Tcp_Data_tdata : out std_ulogic_vector( 63 downto 0);
100  soNRC_Tcp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
101  soNRC_Tcp_Data_tvalid : out std_ulogic;
102  soNRC_Tcp_Data_tlast : out std_ulogic;
103  soNRC_Tcp_Data_tready : in std_ulogic;
104  -- Open Port vector
105  poROL_Nrc_Tcp_Rx_ports : out std_ulogic_vector( 31 downto 0);
106  -- ROLE <-> NRC Meta Interface
107  soROLE_Nrc_Tcp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
108  soROLE_Nrc_Tcp_Meta_TVALID : out std_ulogic;
109  soROLE_Nrc_Tcp_Meta_TREADY : in std_ulogic;
110  soROLE_Nrc_Tcp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
111  soROLE_Nrc_Tcp_Meta_TLAST : out std_ulogic;
112  siNRC_Role_Tcp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
113  siNRC_Role_Tcp_Meta_TVALID : in std_ulogic;
114  siNRC_Role_Tcp_Meta_TREADY : out std_ulogic;
115  siNRC_Role_Tcp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
116  siNRC_Role_Tcp_Meta_TLAST : in std_ulogic;
117 
118  --------------------------------------------------------
119  -- SHELL / Mem / Mp0 Interface
120  --------------------------------------------------------
121  ---- Memory Port #0 / S2MM-AXIS ----------------
122  ------ Stream Read Command ---------
123  soMEM_Mp0_RdCmd_tdata : out std_ulogic_vector( 79 downto 0);
124  soMEM_Mp0_RdCmd_tvalid : out std_ulogic;
125  soMEM_Mp0_RdCmd_tready : in std_ulogic;
126  ------ Stream Read Status ----------
127  siMEM_Mp0_RdSts_tdata : in std_ulogic_vector( 7 downto 0);
128  siMEM_Mp0_RdSts_tvalid : in std_ulogic;
129  siMEM_Mp0_RdSts_tready : out std_ulogic;
130  ------ Stream Data Input Channel ---
131  siMEM_Mp0_Read_tdata : in std_ulogic_vector(511 downto 0);
132  siMEM_Mp0_Read_tkeep : in std_ulogic_vector( 63 downto 0);
133  siMEM_Mp0_Read_tlast : in std_ulogic;
134  siMEM_Mp0_Read_tvalid : in std_ulogic;
135  siMEM_Mp0_Read_tready : out std_ulogic;
136  ------ Stream Write Command --------
137  soMEM_Mp0_WrCmd_tdata : out std_ulogic_vector( 79 downto 0);
138  soMEM_Mp0_WrCmd_tvalid : out std_ulogic;
139  soMEM_Mp0_WrCmd_tready : in std_ulogic;
140  ------ Stream Write Status ---------
141  siMEM_Mp0_WrSts_tdata : in std_ulogic_vector( 7 downto 0);
142  siMEM_Mp0_WrSts_tvalid : in std_ulogic;
143  siMEM_Mp0_WrSts_tready : out std_ulogic;
144  ------ Stream Data Output Channel --
145  soMEM_Mp0_Write_tdata : out std_ulogic_vector(511 downto 0);
146  soMEM_Mp0_Write_tkeep : out std_ulogic_vector( 63 downto 0);
147  soMEM_Mp0_Write_tlast : out std_ulogic;
148  soMEM_Mp0_Write_tvalid : out std_ulogic;
149  soMEM_Mp0_Write_tready : in std_ulogic;
150 
151  --------------------------------------------------------
152  -- SHELL / Mem / Mp1 Interface
153  --------------------------------------------------------
154  moMEM_Mp1_AWID : out std_ulogic_vector(7 downto 0);
155  moMEM_Mp1_AWADDR : out std_ulogic_vector(32 downto 0);
156  moMEM_Mp1_AWLEN : out std_ulogic_vector(7 downto 0);
157  moMEM_Mp1_AWSIZE : out std_ulogic_vector(2 downto 0);
158  moMEM_Mp1_AWBURST : out std_ulogic_vector(1 downto 0);
159  moMEM_Mp1_AWVALID : out std_ulogic;
160  moMEM_Mp1_AWREADY : in std_ulogic;
161  moMEM_Mp1_WDATA : out std_ulogic_vector(511 downto 0);
162  moMEM_Mp1_WSTRB : out std_ulogic_vector(63 downto 0);
163  moMEM_Mp1_WLAST : out std_ulogic;
164  moMEM_Mp1_WVALID : out std_ulogic;
165  moMEM_Mp1_WREADY : in std_ulogic;
166  moMEM_Mp1_BID : in std_ulogic_vector(7 downto 0);
167  moMEM_Mp1_BRESP : in std_ulogic_vector(1 downto 0);
168  moMEM_Mp1_BVALID : in std_ulogic;
169  moMEM_Mp1_BREADY : out std_ulogic;
170  moMEM_Mp1_ARID : out std_ulogic_vector(7 downto 0);
171  moMEM_Mp1_ARADDR : out std_ulogic_vector(32 downto 0);
172  moMEM_Mp1_ARLEN : out std_ulogic_vector(7 downto 0);
173  moMEM_Mp1_ARSIZE : out std_ulogic_vector(2 downto 0);
174  moMEM_Mp1_ARBURST : out std_ulogic_vector(1 downto 0);
175  moMEM_Mp1_ARVALID : out std_ulogic;
176  moMEM_Mp1_ARREADY : in std_ulogic;
177  moMEM_Mp1_RID : in std_ulogic_vector(7 downto 0);
178  moMEM_Mp1_RDATA : in std_ulogic_vector(511 downto 0);
179  moMEM_Mp1_RRESP : in std_ulogic_vector(1 downto 0);
180  moMEM_Mp1_RLAST : in std_ulogic;
181  moMEM_Mp1_RVALID : in std_ulogic;
182  moMEM_Mp1_RREADY : out std_ulogic;
183 
184  ---- [APP_RDROL] -------------------
185  -- to be use as ROLE VERSION IDENTIFICATION --
186  poSHL_Mmio_RdReg : out std_ulogic_vector( 15 downto 0);
187 
188  --------------------------------------------------------
189  -- TOP : Secondary Clock (Asynchronous)
190  --------------------------------------------------------
191  piTOP_250_00Clk : in std_ulogic; -- Freerunning
192 
193  ------------------------------------------------
194  -- FMC Interface
195  ------------------------------------------------
196  piFMC_ROLE_rank : in std_logic_vector(31 downto 0);
197  piFMC_ROLE_size : in std_logic_vector(31 downto 0);
198 
199  ------------------------------------------------
200  -- DEBUG PORTS (see UG909)
201  ------------------------------------------------
202  dpBSCAN_drck : IN std_logic;
203  dpBSCAN_shift : IN std_logic;
204  dpBSCAN_tdi : IN std_logic;
205  dpBSCAN_update : IN std_logic;
206  dpBSCAN_sel : IN std_logic;
207  dpBSCAN_tdo : OUT std_logic;
208  dpBSCAN_tms : IN std_logic;
209  dpBSCAN_tck : IN std_logic;
210  dpBSCAN_runtest : IN std_logic;
211  dpBSCAN_reset : IN std_logic;
212  dpBSCAN_capture : IN std_logic;
213  dpBSCAN_bscanid_en : IN std_logic;
214 
215  poVoid : out std_ulogic
216 
217  );
218 
219 end Role_Themisto;
220 
221 
222 -- *****************************************************************************
223 -- ** ARCHITECTURE ** FLASH of ROLE_THEMISTO
224 -- *****************************************************************************
225 
226 architecture Flash of Role_Themisto is
227 
228  constant cUSE_DEPRECATED_DIRECTIVES : boolean := false;
229 
230  --============================================================================
231  -- DEBUG SIGNALS ATTRIBUTE DECLARATIONS (see UG909)
232  --============================================================================
233  attribute X_INTERFACE_INFO : string;
234  attribute DEBUG : string;
235  attribute X_INTERFACE_INFO of dpBSCAN_drck: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN drck";
236  attribute DEBUG of dpBSCAN_drck: signal is "true";
237  attribute X_INTERFACE_INFO of dpBSCAN_shift: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN shift";
238  attribute DEBUG of dpBSCAN_shift: signal is "true";
239  attribute X_INTERFACE_INFO of dpBSCAN_tdi: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN tdi";
240  attribute DEBUG of dpBSCAN_tdi: signal is "true";
241  attribute X_INTERFACE_INFO of dpBSCAN_update: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN update";
242  attribute DEBUG of dpBSCAN_update: signal is "true";
243  attribute X_INTERFACE_INFO of dpBSCAN_sel: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN sel";
244  attribute DEBUG of dpBSCAN_sel: signal is "true";
245  attribute X_INTERFACE_INFO of dpBSCAN_tdo: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN tdo";
246  attribute DEBUG of dpBSCAN_tdo: signal is "true";
247  attribute X_INTERFACE_INFO of dpBSCAN_tms: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN tms";
248  attribute DEBUG of dpBSCAN_tms: signal is "true";
249  attribute X_INTERFACE_INFO of dpBSCAN_tck: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN tck";
250  attribute DEBUG of dpBSCAN_tck: signal is "true";
251  attribute X_INTERFACE_INFO of dpBSCAN_runtest: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN runtest";
252  attribute DEBUG of dpBSCAN_runtest: signal is "true";
253  attribute X_INTERFACE_INFO of dpBSCAN_reset: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN reset";
254  attribute DEBUG of dpBSCAN_reset: signal is "true";
255  attribute X_INTERFACE_INFO of dpBSCAN_capture: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN capture";
256  attribute DEBUG of dpBSCAN_capture: signal is "true";
257  attribute X_INTERFACE_INFO of dpBSCAN_bscanid_en: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN bscanid_en";
258  attribute DEBUG of dpBSCAN_bscanid_en: signal is "true";
259 
260  --============================================================================
261  -- SIGNAL DECLARATIONS
262  --============================================================================
263 
264  -- I hate Vivado HLS
265  signal sReadTlastAsVector : std_logic_vector(0 downto 0);
266  signal sWriteTlastAsVector : std_logic_vector(0 downto 0);
267  signal sResetAsVector : std_logic_vector(0 downto 0);
268 
269  signal sMetaOutTlastAsVector_Udp : std_logic_vector(0 downto 0);
270  signal sMetaInTlastAsVector_Udp : std_logic_vector(0 downto 0);
271  signal sMetaOutTlastAsVector_Tcp : std_logic_vector(0 downto 0);
272  signal sMetaInTlastAsVector_Tcp : std_logic_vector(0 downto 0);
273 
274  signal sUdpPostCnt : std_ulogic_vector(9 downto 0);
275  signal sTcpPostCnt : std_ulogic_vector(9 downto 0);
276 
277  --signal sMemTestDebugOut : std_logic_vector(15 downto 0);
278 
279  signal sResetApps_n : std_logic;
280 
281  --============================================================================
282  -- VARIABLE DECLARATIONS
283  --============================================================================
284 
285  --===========================================================================
286  --== COMPONENT DECLARATIONS
287  --===========================================================================
288  component TriangleApplication is
289  port (
290  ------------------------------------------------------
291  -- From SHELL / Clock and Reset
292  ------------------------------------------------------
293  ap_clk : in std_logic;
294  ap_rst_n : in std_logic;
295  -- rank and size
296  piFMC_ROL_rank_V : in std_logic_vector (31 downto 0);
297  piFMC_ROL_rank_V_ap_vld : in std_logic;
298  --piSMC_ROL_rank_V_ap_vld : in std_logic;
299  piFMC_ROL_size_V : in std_logic_vector (31 downto 0);
300  piFMC_ROL_size_V_ap_vld : in std_logic;
301  --piSMC_ROL_size_V_ap_vld : in std_logic;
302  --------------------------------------------------------
303  -- From SHELL / Udp Data Interfaces
304  --------------------------------------------------------
305  siNrc_data_TDATA : in std_logic_vector( 63 downto 0);
306  siNrc_data_TKEEP : in std_logic_vector( 7 downto 0);
307  siNrc_data_TLAST : in std_logic;
308  siNrc_data_TVALID : in std_logic;
309  siNrc_data_TREADY : out std_logic;
310  --------------------------------------------------------
311  -- To SHELL / Udp Data Interfaces
312  --------------------------------------------------------
313  soNrc_data_TDATA : out std_logic_vector( 63 downto 0);
314  soNrc_data_TKEEP : out std_logic_vector( 7 downto 0);
315  soNrc_data_TLAST : out std_logic;
316  soNrc_data_TVALID : out std_logic;
317  soNrc_data_TREADY : in std_logic;
318  -- NRC Meta and Ports
319  siNrc_meta_TDATA : in std_logic_vector (63 downto 0);
320  siNrc_meta_TVALID : in std_logic;
321  siNrc_meta_TREADY : out std_logic;
322  siNrc_meta_TKEEP : in std_logic_vector (7 downto 0);
323  siNrc_meta_TLAST : in std_logic_vector (0 downto 0);
324 
325  soNrc_meta_TDATA : out std_logic_vector (63 downto 0);
326  soNrc_meta_TVALID : out std_logic;
327  soNrc_meta_TREADY : in std_logic;
328  soNrc_meta_TKEEP : out std_logic_vector (7 downto 0);
329  soNrc_meta_TLAST : out std_logic_vector (0 downto 0);
330 
331  poROL_NRC_Rx_ports_V : out std_logic_vector (31 downto 0);
332  poROL_NRC_Rx_ports_V_ap_vld : out std_logic
333  );
334  end component TriangleApplication;
335 
336  component ila_role_0 is
337  port (
338  clk : IN STD_LOGIC;
339  probe0 : in std_logic_vector( 63 downto 0);
340  probe1 : in std_logic_vector( 7 downto 0);
341  probe2 : in std_logic_vector( 0 downto 0);
342  probe3 : in std_logic_vector( 0 downto 0);
343  probe4 : in std_logic_vector( 0 downto 0);
344  probe5 : in std_logic_vector( 63 downto 0);
345  probe6 : in std_logic_vector( 7 downto 0);
346  probe7 : in std_logic_vector( 0 downto 0);
347  probe8 : in std_logic_vector( 0 downto 0);
348  probe9 : in std_logic_vector( 0 downto 0);
349  probe10 : in std_logic_vector( 63 downto 0);
350  probe11 : in std_logic_vector( 7 downto 0);
351  probe12 : in std_logic_vector( 0 downto 0);
352  probe13 : in std_logic_vector( 0 downto 0);
353  probe14 : in std_logic_vector( 0 downto 0);
354  probe15 : in std_logic_vector( 63 downto 0);
355  probe16 : in std_logic_vector( 7 downto 0);
356  probe17 : in std_logic_vector( 0 downto 0);
357  probe18 : in std_logic_vector( 0 downto 0);
358  probe19 : in std_logic_vector( 0 downto 0);
359  probe20 : in std_logic_vector( 63 downto 0);
360  probe21 : in std_logic_vector( 7 downto 0);
361  probe22 : in std_logic_vector( 0 downto 0);
362  probe23 : in std_logic_vector( 0 downto 0);
363  probe24 : in std_logic_vector( 0 downto 0);
364  probe25 : in std_logic_vector( 63 downto 0);
365  probe26 : in std_logic_vector( 7 downto 0);
366  probe27 : in std_logic_vector( 0 downto 0);
367  probe28 : in std_logic_vector( 0 downto 0);
368  probe29 : in std_logic_vector( 0 downto 0);
369  probe30 : in std_logic_vector( 63 downto 0);
370  probe31 : in std_logic_vector( 7 downto 0);
371  probe32 : in std_logic_vector( 0 downto 0);
372  probe33 : in std_logic_vector( 0 downto 0);
373  probe34 : in std_logic_vector( 0 downto 0);
374  probe35 : in std_logic_vector( 63 downto 0);
375  probe36 : in std_logic_vector( 7 downto 0);
376  probe37 : in std_logic_vector( 0 downto 0);
377  probe38 : in std_logic_vector( 0 downto 0);
378  probe39 : in std_logic_vector( 0 downto 0);
379  probe40 : in std_logic_vector( 31 downto 0);
380  probe41 : in std_logic_vector( 31 downto 0)
381  );
382  end component ila_role_0;
383 
384 
385  --===========================================================================
386  --== FUNCTION DECLARATIONS [TODO-Move to a package]
387  --===========================================================================
388  function fVectorize(s: std_logic) return std_logic_vector is
389  variable v: std_logic_vector(0 downto 0);
390  begin
391  v(0) := s;
392  return v;
393  end fVectorize;
394 
395  function fScalarize(v: in std_logic_vector) return std_ulogic is
396  begin
397  assert v'length = 1
398  report "scalarize: output port must be single bit!"
399  severity FAILURE;
400  return v(v'LEFT);
401  end;
402 
403 
404 --################################################################################
405 --# #
406 --# ##### #### #### # # #
407 --# # # # # # # # # #
408 --# # # # # # # ### #
409 --# ##### # # # # # #
410 --# # # # # # # # #
411 --# # # # # # # # #
412 --# ##### #### #### # #
413 --# #
414 --################################################################################
415 
416 begin
417 
418  -- to be use as ROLE VERSION IDENTIFICATION --
419  poSHL_Mmio_RdReg <= x"BEEF";
420 
421  sResetApps_n <= (not piMMIO_Ly7_Rst) and (piMMIO_Ly7_En);
422 
423  --################################################################################
424  --# #
425  --# # # ##### ###### ##### #
426  --# # # # # # # # # ##### ##### #
427  --# # # # # # # # # # # # # #
428  --# # # # # ###### ####### ##### ##### #
429  --# # # # # # # # # # #
430  --# ####### ##### # # # # # #
431  --# #
432  --################################################################################
433 
434  sMetaInTlastAsVector_Udp(0) <= siNRC_Role_Udp_Meta_TLAST;
435  soROLE_Nrc_Udp_Meta_TLAST <= sMetaOutTlastAsVector_Udp(0);
436 
437  UAF: TriangleApplication
438  port map (
439  ------------------------------------------------------
440  -- From SHELL / Clock and Reset
441  ------------------------------------------------------
442  ap_clk => piSHL_156_25Clk,
443  --ap_rst_n => (not piMMIO_Ly7_Rst),
444  ap_rst_n => sResetApps_n,
445 
446  piFMC_ROL_rank_V => piFMC_ROLE_rank,
447  piFMC_ROL_rank_V_ap_vld => '1',
448  piFMC_ROL_size_V => piFMC_ROLE_size,
449  piFMC_ROL_size_V_ap_vld => '1',
450  --------------------------------------------------------
451  -- From SHELL / Udp Data Interfaces
452  --------------------------------------------------------
453  siNrc_data_TDATA => siNRC_Udp_Data_tdata,
454  siNrc_data_TKEEP => siNRC_Udp_Data_tkeep,
455  siNrc_data_TLAST => siNRC_Udp_Data_tlast,
456  siNrc_data_TVALID => siNRC_Udp_Data_tvalid,
457  siNrc_data_TREADY => siNRC_Udp_Data_tready,
458  --------------------------------------------------------
459  -- To SHELL / Udp Data Interfaces
460  --------------------------------------------------------
461  soNrc_data_TDATA => soNRC_Udp_Data_tdata,
462  soNrc_data_TKEEP => soNRC_Udp_Data_tkeep,
463  soNrc_data_TLAST => soNRC_Udp_Data_tlast,
464  soNrc_data_TVALID => soNRC_Udp_Data_tvalid,
465  soNrc_data_TREADY => soNRC_Udp_Data_tready,
466 
467  siNrc_meta_TDATA => siNRC_Role_Udp_Meta_TDATA ,
468  siNrc_meta_TVALID => siNRC_Role_Udp_Meta_TVALID ,
469  siNrc_meta_TREADY => siNRC_Role_Udp_Meta_TREADY ,
470  siNrc_meta_TKEEP => siNRC_Role_Udp_Meta_TKEEP ,
471  siNrc_meta_TLAST => sMetaInTlastAsVector_Udp,
472 
473  soNrc_meta_TDATA => soROLE_Nrc_Udp_Meta_TDATA ,
474  soNrc_meta_TVALID => soROLE_Nrc_Udp_Meta_TVALID ,
475  soNrc_meta_TREADY => soROLE_Nrc_Udp_Meta_TREADY ,
476  soNrc_meta_TKEEP => soROLE_Nrc_Udp_Meta_TKEEP ,
477  soNrc_meta_TLAST => sMetaOutTlastAsVector_Udp,
478 
479  poROL_NRC_Rx_ports_V => poROL_Nrc_Udp_Rx_ports
480  );
481 
482  --################################################################################
483  --# #
484  --# ####### #### ###### ##### #
485  --# # # # # # # ##### ##### #
486  --# # # # # # # # # # # #
487  --# # # ###### ####### ##### ##### #
488  --# # # # # # # # #
489  --# # #### # # # # # #
490  --# #
491  --################################################################################
492 
493  sMetaInTlastAsVector_Tcp(0) <= siNRC_Role_Tcp_Meta_TLAST;
494  soROLE_Nrc_Tcp_Meta_TLAST <= sMetaOutTlastAsVector_Tcp(0);
495 
496  TAF: TriangleApplication
497  port map (
498 
499  ------------------------------------------------------
500  -- From SHELL / Clock and Reset
501  ------------------------------------------------------
502  ap_clk => piSHL_156_25Clk,
503  --ap_rst_n => (not piMMIO_Ly7_Rst),
504  ap_rst_n => sResetApps_n,
505 
506  piFMC_ROL_rank_V => piFMC_ROLE_rank,
507  piFMC_ROL_rank_V_ap_vld => '1',
508  piFMC_ROL_size_V => piFMC_ROLE_size,
509  piFMC_ROL_size_V_ap_vld => '1',
510  --------------------------------------------------------
511  -- From SHELL / Udp Data Interfaces
512  --------------------------------------------------------
513  siNrc_data_TDATA => siNRC_Tcp_Data_tdata,
514  siNrc_data_TKEEP => siNRC_Tcp_Data_tkeep,
515  siNrc_data_TLAST => siNRC_Tcp_Data_tlast,
516  siNrc_data_TVALID => siNRC_Tcp_Data_tvalid,
517  siNrc_data_TREADY => siNRC_Tcp_Data_tready,
518  --------------------------------------------------------
519  -- To SHELL / Udp Data Interfaces
520  --------------------------------------------------------
521  soNrc_data_TDATA => soNRC_Tcp_Data_tdata,
522  soNrc_data_TKEEP => soNRC_Tcp_Data_tkeep,
523  soNrc_data_TLAST => soNRC_Tcp_Data_tlast,
524  soNrc_data_TVALID => soNRC_Tcp_Data_tvalid,
525  soNrc_data_TREADY => soNRC_Tcp_Data_tready,
526 
527  siNrc_meta_TDATA => siNRC_Role_Tcp_Meta_TDATA ,
528  siNrc_meta_TVALID => siNRC_Role_Tcp_Meta_TVALID ,
529  siNrc_meta_TREADY => siNRC_Role_Tcp_Meta_TREADY ,
530  siNrc_meta_TKEEP => siNRC_Role_Tcp_Meta_TKEEP ,
531  siNrc_meta_TLAST => sMetaInTlastAsVector_Tcp,
532 
533  soNrc_meta_TDATA => soROLE_Nrc_Tcp_Meta_TDATA ,
534  soNrc_meta_TVALID => soROLE_Nrc_Tcp_Meta_TVALID ,
535  soNrc_meta_TREADY => soROLE_Nrc_Tcp_Meta_TREADY ,
536  soNrc_meta_TKEEP => soROLE_Nrc_Tcp_Meta_TKEEP ,
537  soNrc_meta_TLAST => sMetaOutTlastAsVector_Tcp,
538 
539  poROL_NRC_Rx_ports_V => poROL_Nrc_Tcp_Rx_ports
540  );
541 
542 
543  --################################################################################
544  -- Debug Core instantiation
545  --################################################################################
546 
547  DBG: ila_role_0
548  port map (
549  clk => piSHL_156_25Clk,
550  probe0 => siNRC_Udp_Data_tdata ,
551  probe1 => siNRC_Udp_Data_tkeep ,
552  probe2(0) => siNRC_Udp_Data_tlast ,
553  probe3(0) => siNRC_Udp_Data_tvalid ,
554  probe4(0) => siNRC_Udp_Data_tready ,
555  probe5 => soNRC_Udp_Data_tdata ,
556  probe6 => soNRC_Udp_Data_tkeep ,
557  probe7(0) => soNRC_Udp_Data_tlast ,
558  probe8(0) => soNRC_Udp_Data_tvalid ,
559  probe9(0) => soNRC_Udp_Data_tready ,
560  probe10 => siNRC_Role_Udp_Meta_TDATA ,
561  probe11 => siNRC_Role_Udp_Meta_TKEEP ,
562  probe12(0) => siNRC_Role_Udp_Meta_TREADY ,
563  probe13(0) => siNRC_Role_Udp_Meta_TVALID ,
564  probe14(0) => siNRC_Role_Udp_Meta_TLAST ,
565  probe15 => soROLE_Nrc_Udp_Meta_TDATA ,
566  probe16 => soROLE_Nrc_Udp_Meta_TKEEP ,
567  probe17(0) => soROLE_Nrc_Udp_Meta_TREADY ,
568  probe18(0) => soROLE_Nrc_Udp_Meta_TVALID ,
569  probe19(0) => soROLE_Nrc_Udp_Meta_TLAST ,
570  probe20 => siNRC_Tcp_Data_tdata ,
571  probe21 => siNRC_Tcp_Data_tkeep ,
572  probe22(0) => siNRC_Tcp_Data_tlast ,
573  probe23(0) => siNRC_Tcp_Data_tvalid ,
574  probe24(0) => siNRC_Tcp_Data_tready ,
575  probe25 => soNRC_Tcp_Data_tdata ,
576  probe26 => soNRC_Tcp_Data_tkeep ,
577  probe27(0) => soNRC_Tcp_Data_tlast ,
578  probe28(0) => soNRC_Tcp_Data_tvalid ,
579  probe29(0) => soNRC_Tcp_Data_tready ,
580  probe30 => siNRC_Role_Tcp_Meta_TDATA ,
581  probe31 => siNRC_Role_Tcp_Meta_TKEEP ,
582  probe32(0) => siNRC_Role_Tcp_Meta_TREADY ,
583  probe33(0) => siNRC_Role_Tcp_Meta_TVALID ,
584  probe34(0) => siNRC_Role_Tcp_Meta_TLAST ,
585  probe35 => soROLE_Nrc_Tcp_Meta_TDATA ,
586  probe36 => soROLE_Nrc_Tcp_Meta_TKEEP ,
587  probe37(0) => soROLE_Nrc_Tcp_Meta_TREADY ,
588  probe38(0) => soROLE_Nrc_Tcp_Meta_TVALID ,
589  probe39(0) => soROLE_Nrc_Tcp_Meta_TLAST ,
590  probe40 => poROL_Nrc_Udp_Rx_ports,
591  probe41 => poROL_Nrc_Tcp_Rx_ports
592  );
593 
594 
595  --################################################################################
596  -- 1st Memory Port dummy connections
597  --################################################################################
598  soMEM_Mp0_RdCmd_tdata <= (others => '0');
599  soMEM_Mp0_RdCmd_tvalid <= '0';
600  siMEM_Mp0_RdSts_tready <= '0';
601  siMEM_Mp0_Read_tready <= '0';
602  soMEM_Mp0_WrCmd_tdata <= (others => '0');
603  soMEM_Mp0_WrCmd_tvalid <= '0';
604  siMEM_Mp0_WrSts_tready <= '0';
605  soMEM_Mp0_Write_tdata <= (others => '0');
606  soMEM_Mp0_Write_tkeep <= (others => '0');
607  soMEM_Mp0_Write_tlast <= '0';
608  soMEM_Mp0_Write_tvalid <= '0';
609 
610  --################################################################################
611  -- 2nd Memory Port dummy connections
612  --################################################################################
613  moMEM_Mp1_AWVALID <= '0';
614  moMEM_Mp1_WVALID <= '0';
615  moMEM_Mp1_BREADY <= '0';
616  moMEM_Mp1_ARVALID <= '0';
617  moMEM_Mp1_RREADY <= '0';
618 
619 end architecture Flash;
620 
Role_Themisto
Definition: Role.vhdl:43
Role_Themisto.soNRC_Tcp_Data_tready
in soNRC_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:98
Role_Themisto.moMEM_Mp1_ARSIZE
out moMEM_Mp1_ARSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:169
Role_Themisto.moMEM_Mp1_AWADDR
out moMEM_Mp1_AWADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:151
Role_Themisto.soNRC_Udp_Data_tdata
out soNRC_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:65
Role_Themisto.soROLE_Nrc_Udp_Meta_TREADY
in soROLE_Nrc_Udp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:75
Role_Themisto.piSHL_156_25Clk
in piSHL_156_25Clkstd_ulogic
Definition: Role.vhdl:49
Role_Themisto.moMEM_Mp1_RREADY
out moMEM_Mp1_RREADYstd_ulogic
Definition: Role.vhdl:178
Role_Themisto.soROLE_Nrc_Udp_Meta_TKEEP
out soROLE_Nrc_Udp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:76
Role_Themisto.piSHL_156_25Rst
in piSHL_156_25Rststd_ulogic
Definition: Role.vhdl:50
Role_Themisto.dpBSCAN_tdi
in dpBSCAN_tdistd_logic
Definition: Role.vhdl:200
Role_Themisto.moMEM_Mp1_RLAST
in moMEM_Mp1_RLASTstd_ulogic
Definition: Role.vhdl:176
Role_Themisto.siNRC_Udp_Data_tlast
in siNRC_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:62
Role_Themisto.siMEM_Mp0_Read_tready
out siMEM_Mp0_Read_treadystd_ulogic
Definition: Role.vhdl:131
Role_Themisto.siNRC_Role_Udp_Meta_TKEEP
in siNRC_Role_Udp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:81
Role_Themisto.siMEM_Mp0_Read_tkeep
in siMEM_Mp0_Read_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:128
Role_Themisto.dpBSCAN_reset
in dpBSCAN_resetstd_logic
Definition: Role.vhdl:207
Role_Themisto.dpBSCAN_sel
in dpBSCAN_selstd_logic
Definition: Role.vhdl:202
Role_Themisto.dpBSCAN_drck
in dpBSCAN_drckstd_logic
Definition: Role.vhdl:198
Role_Themisto.soNRC_Tcp_Data_tdata
out soNRC_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:94
Role_Themisto.soROLE_Nrc_Tcp_Meta_TREADY
in soROLE_Nrc_Tcp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:104
Role_Themisto.siNRC_Role_Tcp_Meta_TLAST
in siNRC_Role_Tcp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:111
Role_Themisto.siMEM_Mp0_WrSts_tdata
in siMEM_Mp0_WrSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:137
Role_Themisto.soMEM_Mp0_Write_tkeep
out soMEM_Mp0_Write_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:142
Role_Themisto.siNRC_Tcp_Data_tready
out siNRC_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:92
Role_Themisto.siNRC_Role_Udp_Meta_TDATA
in siNRC_Role_Udp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:78
Role_Themisto.moMEM_Mp1_AWVALID
out moMEM_Mp1_AWVALIDstd_ulogic
Definition: Role.vhdl:155
Role_Themisto.siNRC_Role_Tcp_Meta_TVALID
in siNRC_Role_Tcp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:108
Role_Themisto.siNRC_Role_Tcp_Meta_TDATA
in siNRC_Role_Tcp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:107
Role_Themisto.moMEM_Mp1_BVALID
in moMEM_Mp1_BVALIDstd_ulogic
Definition: Role.vhdl:164
Role_Themisto.moMEM_Mp1_WSTRB
out moMEM_Mp1_WSTRBstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:158
Role_Themisto.moMEM_Mp1_BREADY
out moMEM_Mp1_BREADYstd_ulogic
Definition: Role.vhdl:165
Role_Themisto.moMEM_Mp1_AWID
out moMEM_Mp1_AWIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:150
Role_Themisto.moMEM_Mp1_RVALID
in moMEM_Mp1_RVALIDstd_ulogic
Definition: Role.vhdl:177
Role_Themisto.soNRC_Udp_Data_tready
in soNRC_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:69
Role_Themisto.soMEM_Mp0_WrCmd_tready
in soMEM_Mp0_WrCmd_treadystd_ulogic
Definition: Role.vhdl:135
Role_Themisto.siNRC_Udp_Data_tvalid
in siNRC_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:61
Role_Themisto.piMMIO_Ly7_En
in piMMIO_Ly7_Enstd_ulogic
Definition: Role.vhdl:53
Role_Themisto.soMEM_Mp0_Write_tready
in soMEM_Mp0_Write_treadystd_ulogic
Definition: Role.vhdl:145
Role_Themisto.soNRC_Udp_Data_tlast
out soNRC_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:68
Role_Themisto.soROLE_Nrc_Udp_Meta_TVALID
out soROLE_Nrc_Udp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:74
Role_Themisto.soROLE_Nrc_Tcp_Meta_TVALID
out soROLE_Nrc_Tcp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:103
Role_Themisto.moMEM_Mp1_WLAST
out moMEM_Mp1_WLASTstd_ulogic
Definition: Role.vhdl:159
Role_Themisto.soNRC_Udp_Data_tvalid
out soNRC_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:67
Role_Themisto.moMEM_Mp1_WDATA
out moMEM_Mp1_WDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:157
Role_Themisto.siNRC_Tcp_Data_tdata
in siNRC_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:88
Role_Themisto.soMEM_Mp0_RdCmd_tdata
out soMEM_Mp0_RdCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:119
Role_Themisto.siMEM_Mp0_Read_tdata
in siMEM_Mp0_Read_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:127
Role_Themisto.soMEM_Mp0_Write_tdata
out soMEM_Mp0_Write_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:141
Role_Themisto.siMEM_Mp0_RdSts_tready
out siMEM_Mp0_RdSts_treadystd_ulogic
Definition: Role.vhdl:125
Role_Themisto.moMEM_Mp1_ARBURST
out moMEM_Mp1_ARBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:170
Role_Themisto.siNRC_Role_Tcp_Meta_TKEEP
in siNRC_Role_Tcp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:110
Role_Themisto.siMEM_Mp0_RdSts_tdata
in siMEM_Mp0_RdSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:123
Role_Themisto.poROL_Nrc_Tcp_Rx_ports
out poROL_Nrc_Tcp_Rx_portsstd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:100
Role_Themisto.siNRC_Tcp_Data_tvalid
in siNRC_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:90
Role_Themisto.siNRC_Role_Udp_Meta_TLAST
in siNRC_Role_Udp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:82
Role_Themisto.moMEM_Mp1_ARREADY
in moMEM_Mp1_ARREADYstd_ulogic
Definition: Role.vhdl:172
Role_Themisto.siNRC_Udp_Data_tready
out siNRC_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:63
Role_Themisto.dpBSCAN_tms
in dpBSCAN_tmsstd_logic
Definition: Role.vhdl:204
Role_Themisto.moMEM_Mp1_RRESP
in moMEM_Mp1_RRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:175
Role_Themisto.soMEM_Mp0_Write_tlast
out soMEM_Mp0_Write_tlaststd_ulogic
Definition: Role.vhdl:143
Role_Themisto.moMEM_Mp1_ARID
out moMEM_Mp1_ARIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:166
Role_Themisto.dpBSCAN_capture
in dpBSCAN_capturestd_logic
Definition: Role.vhdl:208
Role_Themisto.soMEM_Mp0_WrCmd_tvalid
out soMEM_Mp0_WrCmd_tvalidstd_ulogic
Definition: Role.vhdl:134
Role_Themisto.moMEM_Mp1_ARVALID
out moMEM_Mp1_ARVALIDstd_ulogic
Definition: Role.vhdl:171
Role_Themisto.soROLE_Nrc_Tcp_Meta_TDATA
out soROLE_Nrc_Tcp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:102
Role_Themisto.moMEM_Mp1_AWBURST
out moMEM_Mp1_AWBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:154
Role_Themisto.siNRC_Udp_Data_tkeep
in siNRC_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:60
Role_Themisto.soMEM_Mp0_RdCmd_tvalid
out soMEM_Mp0_RdCmd_tvalidstd_ulogic
Definition: Role.vhdl:120
Role_Themisto.soNRC_Tcp_Data_tkeep
out soNRC_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:95
Role_Themisto.siMEM_Mp0_Read_tvalid
in siMEM_Mp0_Read_tvalidstd_ulogic
Definition: Role.vhdl:130
Role_Themisto.dpBSCAN_bscanid_en
in dpBSCAN_bscanid_enstd_logic
Definition: Role.vhdl:209
Role_Themisto.dpBSCAN_tdo
out dpBSCAN_tdostd_logic
Definition: Role.vhdl:203
Role_Themisto.moMEM_Mp1_RID
in moMEM_Mp1_RIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:173
Role_Themisto.soROLE_Nrc_Udp_Meta_TDATA
out soROLE_Nrc_Udp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:73
Role_Themisto.piFMC_ROLE_rank
in piFMC_ROLE_rankstd_logic_vector(31 downto 0)
Definition: Role.vhdl:192
Role_Themisto.soROLE_Nrc_Tcp_Meta_TKEEP
out soROLE_Nrc_Tcp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:105
Role_Themisto.piTOP_250_00Clk
in piTOP_250_00Clkstd_ulogic
Definition: Role.vhdl:187
Role_Themisto.moMEM_Mp1_AWLEN
out moMEM_Mp1_AWLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:152
Role_Themisto.piFMC_ROLE_size
in piFMC_ROLE_sizestd_logic_vector(31 downto 0)
Definition: Role.vhdl:193
Role_Themisto.siNRC_Tcp_Data_tkeep
in siNRC_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:89
Role_Themisto.soMEM_Mp0_RdCmd_tready
in soMEM_Mp0_RdCmd_treadystd_ulogic
Definition: Role.vhdl:121
Role_Themisto.moMEM_Mp1_WREADY
in moMEM_Mp1_WREADYstd_ulogic
Definition: Role.vhdl:161
Role_Themisto.siNRC_Role_Udp_Meta_TREADY
out siNRC_Role_Udp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:80
Role_Themisto.soNRC_Tcp_Data_tlast
out soNRC_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:97
Role_Themisto.siMEM_Mp0_RdSts_tvalid
in siMEM_Mp0_RdSts_tvalidstd_ulogic
Definition: Role.vhdl:124
Role_Themisto.soROLE_Nrc_Udp_Meta_TLAST
out soROLE_Nrc_Udp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:77
Role_Themisto.moMEM_Mp1_AWSIZE
out moMEM_Mp1_AWSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:153
Role_Themisto.dpBSCAN_shift
in dpBSCAN_shiftstd_logic
Definition: Role.vhdl:199
Role_Themisto.moMEM_Mp1_RDATA
in moMEM_Mp1_RDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:174
Role_Themisto.moMEM_Mp1_BID
in moMEM_Mp1_BIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:162
Role_Themisto.soMEM_Mp0_WrCmd_tdata
out soMEM_Mp0_WrCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:133
Role_Themisto.piMMIO_Ly7_Rst
in piMMIO_Ly7_Rststd_ulogic
Definition: Role.vhdl:52
Role_Themisto.poSHL_Mmio_RdReg
out poSHL_Mmio_RdRegstd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:182
Role_Themisto.siNRC_Role_Tcp_Meta_TREADY
out siNRC_Role_Tcp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:109
Role_Themisto.siNRC_Role_Udp_Meta_TVALID
in siNRC_Role_Udp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:79
Role_Themisto.moMEM_Mp1_BRESP
in moMEM_Mp1_BRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:163
Role_Themisto.moMEM_Mp1_WVALID
out moMEM_Mp1_WVALIDstd_ulogic
Definition: Role.vhdl:160
Role_Themisto.dpBSCAN_update
in dpBSCAN_updatestd_logic
Definition: Role.vhdl:201
Role_Themisto.siNRC_Udp_Data_tdata
in siNRC_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:59
Role_Themisto.moMEM_Mp1_ARLEN
out moMEM_Mp1_ARLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:168
Role_Themisto.soROLE_Nrc_Tcp_Meta_TLAST
out soROLE_Nrc_Tcp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:106
Role_Themisto.soNRC_Udp_Data_tkeep
out soNRC_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:66
Role_Themisto.siNRC_Tcp_Data_tlast
in siNRC_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:91
Role_Themisto.siMEM_Mp0_WrSts_tready
out siMEM_Mp0_WrSts_treadystd_ulogic
Definition: Role.vhdl:139
Role_Themisto.dpBSCAN_runtest
in dpBSCAN_runteststd_logic
Definition: Role.vhdl:206
Role_Themisto.siMEM_Mp0_WrSts_tvalid
in siMEM_Mp0_WrSts_tvalidstd_ulogic
Definition: Role.vhdl:138
Role_Themisto.soMEM_Mp0_Write_tvalid
out soMEM_Mp0_Write_tvalidstd_ulogic
Definition: Role.vhdl:144
Role_Themisto.moMEM_Mp1_ARADDR
out moMEM_Mp1_ARADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:167
Role_Themisto.poVoid
out poVoidstd_ulogic
Definition: Role.vhdl:213
Role_Themisto.moMEM_Mp1_AWREADY
in moMEM_Mp1_AWREADYstd_ulogic
Definition: Role.vhdl:156
Role_Themisto.poROL_Nrc_Udp_Rx_ports
out poROL_Nrc_Udp_Rx_portsstd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:71
Role_Themisto.siMEM_Mp0_Read_tlast
in siMEM_Mp0_Read_tlaststd_ulogic
Definition: Role.vhdl:129
Role_Themisto.dpBSCAN_tck
in dpBSCAN_tckstd_logic
Definition: Role.vhdl:205
Role_Themisto.soNRC_Tcp_Data_tvalid
out soNRC_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:96