cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
Role.vhdl
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1 -- *
2 -- * Copyright 2016 -- 2022 IBM Corporation
3 -- *
4 -- * Licensed under the Apache License, Version 2.0 (the "License");
5 -- * you may not use this file except in compliance with the License.
6 -- * You may obtain a copy of the License at
7 -- *
8 -- * http://www.apache.org/licenses/LICENSE-2.0
9 -- *
10 -- * Unless required by applicable law or agreed to in writing, software
11 -- * distributed under the License is distributed on an "AS IS" BASIS,
12 -- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 -- * See the License for the specific language governing permissions and
14 -- * limitations under the License.
15 -- *
16 
17 -- *
18 -- * cloudFPGA
19 -- * =============================================
20 -- * Created: Apr 2019
21 -- * Authors: FAB, WEI, NGL
22 -- *
23 -- * Description:
24 -- * ROLE template for Themisto SRA
25 -- *
26 
27 --******************************************************************************
28 --** CONTEXT CLAUSE ** FMKU60 ROLE(Flash)
29 --******************************************************************************
30 library IEEE;
31 use IEEE.std_logic_1164.all;
32 use IEEE.numeric_std.all;
33 
34 library UNISIM;
35 use UNISIM.vcomponents.all;
36 
37 -- library XIL_DEFAULTLIB;
38 -- use XIL_DEFAULTLIB.all;
39 
40 
41 --******************************************************************************
42 --** ENTITY ** FMKU60 ROLE
43 --******************************************************************************
44 
45 entity Role_Themisto is
46  port (
47 
48  --------------------------------------------------------
49  -- SHELL / Global Input Clock and Reset Interface
50  --------------------------------------------------------
51  piSHL_156_25Clk : in std_ulogic;
52  piSHL_156_25Rst : in std_ulogic;
53  -- LY7 Enable and Reset
54  piMMIO_Ly7_Rst : in std_ulogic;
55  piMMIO_Ly7_En : in std_ulogic;
56 
57  ------------------------------------------------------
58  -- SHELL / Role / Nts0 / Udp Interface
59  ------------------------------------------------------
60  ---- Input AXI-Write Stream Interface ----------
61  siNRC_Udp_Data_tdata : in std_ulogic_vector( 63 downto 0);
62  siNRC_Udp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
63  siNRC_Udp_Data_tvalid : in std_ulogic;
64  siNRC_Udp_Data_tlast : in std_ulogic;
65  siNRC_Udp_Data_tready : out std_ulogic;
66  ---- Output AXI-Write Stream Interface ---------
67  soNRC_Udp_Data_tdata : out std_ulogic_vector( 63 downto 0);
68  soNRC_Udp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
69  soNRC_Udp_Data_tvalid : out std_ulogic;
70  soNRC_Udp_Data_tlast : out std_ulogic;
71  soNRC_Udp_Data_tready : in std_ulogic;
72  -- Open Port vector
73  poROL_Nrc_Udp_Rx_ports : out std_ulogic_vector( 31 downto 0);
74  -- ROLE <-> NRC Meta Interface
75  soROLE_Nrc_Udp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
76  soROLE_Nrc_Udp_Meta_TVALID : out std_ulogic;
77  soROLE_Nrc_Udp_Meta_TREADY : in std_ulogic;
78  soROLE_Nrc_Udp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
79  soROLE_Nrc_Udp_Meta_TLAST : out std_ulogic;
80  siNRC_Role_Udp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
81  siNRC_Role_Udp_Meta_TVALID : in std_ulogic;
82  siNRC_Role_Udp_Meta_TREADY : out std_ulogic;
83  siNRC_Role_Udp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
84  siNRC_Role_Udp_Meta_TLAST : in std_ulogic;
85 
86  ------------------------------------------------------
87  -- SHELL / Role / Nts0 / Tcp Interface
88  ------------------------------------------------------
89  ---- Input AXI-Write Stream Interface ----------
90  siNRC_Tcp_Data_tdata : in std_ulogic_vector( 63 downto 0);
91  siNRC_Tcp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
92  siNRC_Tcp_Data_tvalid : in std_ulogic;
93  siNRC_Tcp_Data_tlast : in std_ulogic;
94  siNRC_Tcp_Data_tready : out std_ulogic;
95  ---- Output AXI-Write Stream Interface ---------
96  soNRC_Tcp_Data_tdata : out std_ulogic_vector( 63 downto 0);
97  soNRC_Tcp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
98  soNRC_Tcp_Data_tvalid : out std_ulogic;
99  soNRC_Tcp_Data_tlast : out std_ulogic;
100  soNRC_Tcp_Data_tready : in std_ulogic;
101  -- Open Port vector
102  poROL_Nrc_Tcp_Rx_ports : out std_ulogic_vector( 31 downto 0);
103  -- ROLE <-> NRC Meta Interface
104  soROLE_Nrc_Tcp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
105  soROLE_Nrc_Tcp_Meta_TVALID : out std_ulogic;
106  soROLE_Nrc_Tcp_Meta_TREADY : in std_ulogic;
107  soROLE_Nrc_Tcp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
108  soROLE_Nrc_Tcp_Meta_TLAST : out std_ulogic;
109  siNRC_Role_Tcp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
110  siNRC_Role_Tcp_Meta_TVALID : in std_ulogic;
111  siNRC_Role_Tcp_Meta_TREADY : out std_ulogic;
112  siNRC_Role_Tcp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
113  siNRC_Role_Tcp_Meta_TLAST : in std_ulogic;
114 
115 
116  --------------------------------------------------------
117  -- SHELL / Mem / Mp0 Interface
118  --------------------------------------------------------
119  ---- Memory Port #0 / S2MM-AXIS ----------------
120  ------ Stream Read Command ---------
121  soMEM_Mp0_RdCmd_tdata : out std_ulogic_vector( 79 downto 0);
122  soMEM_Mp0_RdCmd_tvalid : out std_ulogic;
123  soMEM_Mp0_RdCmd_tready : in std_ulogic;
124  ------ Stream Read Status ----------
125  siMEM_Mp0_RdSts_tdata : in std_ulogic_vector( 7 downto 0);
126  siMEM_Mp0_RdSts_tvalid : in std_ulogic;
127  siMEM_Mp0_RdSts_tready : out std_ulogic;
128  ------ Stream Data Input Channel ---
129  siMEM_Mp0_Read_tdata : in std_ulogic_vector(511 downto 0);
130  siMEM_Mp0_Read_tkeep : in std_ulogic_vector( 63 downto 0);
131  siMEM_Mp0_Read_tlast : in std_ulogic;
132  siMEM_Mp0_Read_tvalid : in std_ulogic;
133  siMEM_Mp0_Read_tready : out std_ulogic;
134  ------ Stream Write Command --------
135  soMEM_Mp0_WrCmd_tdata : out std_ulogic_vector( 79 downto 0);
136  soMEM_Mp0_WrCmd_tvalid : out std_ulogic;
137  soMEM_Mp0_WrCmd_tready : in std_ulogic;
138  ------ Stream Write Status ---------
139  siMEM_Mp0_WrSts_tdata : in std_ulogic_vector( 7 downto 0);
140  siMEM_Mp0_WrSts_tvalid : in std_ulogic;
141  siMEM_Mp0_WrSts_tready : out std_ulogic;
142  ------ Stream Data Output Channel --
143  soMEM_Mp0_Write_tdata : out std_ulogic_vector(511 downto 0);
144  soMEM_Mp0_Write_tkeep : out std_ulogic_vector( 63 downto 0);
145  soMEM_Mp0_Write_tlast : out std_ulogic;
146  soMEM_Mp0_Write_tvalid : out std_ulogic;
147  soMEM_Mp0_Write_tready : in std_ulogic;
148 
149  --------------------------------------------------------
150  -- SHELL / Mem / Mp1 Interface
151  --------------------------------------------------------
152  moMEM_Mp1_AWID : out std_ulogic_vector(7 downto 0);
153  moMEM_Mp1_AWADDR : out std_ulogic_vector(32 downto 0);
154  moMEM_Mp1_AWLEN : out std_ulogic_vector(7 downto 0);
155  moMEM_Mp1_AWSIZE : out std_ulogic_vector(2 downto 0);
156  moMEM_Mp1_AWBURST : out std_ulogic_vector(1 downto 0);
157  moMEM_Mp1_AWVALID : out std_ulogic;
158  moMEM_Mp1_AWREADY : in std_ulogic;
159  moMEM_Mp1_WDATA : out std_ulogic_vector(511 downto 0);
160  moMEM_Mp1_WSTRB : out std_ulogic_vector(63 downto 0);
161  moMEM_Mp1_WLAST : out std_ulogic;
162  moMEM_Mp1_WVALID : out std_ulogic;
163  moMEM_Mp1_WREADY : in std_ulogic;
164  moMEM_Mp1_BID : in std_ulogic_vector(7 downto 0);
165  moMEM_Mp1_BRESP : in std_ulogic_vector(1 downto 0);
166  moMEM_Mp1_BVALID : in std_ulogic;
167  moMEM_Mp1_BREADY : out std_ulogic;
168  moMEM_Mp1_ARID : out std_ulogic_vector(7 downto 0);
169  moMEM_Mp1_ARADDR : out std_ulogic_vector(32 downto 0);
170  moMEM_Mp1_ARLEN : out std_ulogic_vector(7 downto 0);
171  moMEM_Mp1_ARSIZE : out std_ulogic_vector(2 downto 0);
172  moMEM_Mp1_ARBURST : out std_ulogic_vector(1 downto 0);
173  moMEM_Mp1_ARVALID : out std_ulogic;
174  moMEM_Mp1_ARREADY : in std_ulogic;
175  moMEM_Mp1_RID : in std_ulogic_vector(7 downto 0);
176  moMEM_Mp1_RDATA : in std_ulogic_vector(511 downto 0);
177  moMEM_Mp1_RRESP : in std_ulogic_vector(1 downto 0);
178  moMEM_Mp1_RLAST : in std_ulogic;
179  moMEM_Mp1_RVALID : in std_ulogic;
180  moMEM_Mp1_RREADY : out std_ulogic;
181 
182  ---- [APP_RDROL] -------------------
183  -- to be use as ROLE VERSION IDENTIFICATION --
184  poSHL_Mmio_RdReg : out std_ulogic_vector( 15 downto 0);
185 
186  --------------------------------------------------------
187  -- TOP : Secondary Clock (Asynchronous)
188  --------------------------------------------------------
189  piTOP_250_00Clk : in std_ulogic; -- Freerunning
190 
191  ------------------------------------------------
192  -- FMC Interface
193  ------------------------------------------------
194  piFMC_ROLE_rank : in std_logic_vector(31 downto 0);
195  piFMC_ROLE_size : in std_logic_vector(31 downto 0);
196 
197  ------------------------------------------------
198  -- DEBUG PORTS (see UG909)
199  ------------------------------------------------
200  dpBSCAN_drck : IN std_logic;
201  dpBSCAN_shift : IN std_logic;
202  dpBSCAN_tdi : IN std_logic;
203  dpBSCAN_update : IN std_logic;
204  dpBSCAN_sel : IN std_logic;
205  dpBSCAN_tdo : OUT std_logic;
206  dpBSCAN_tms : IN std_logic;
207  dpBSCAN_tck : IN std_logic;
208  dpBSCAN_runtest : IN std_logic;
209  dpBSCAN_reset : IN std_logic;
210  dpBSCAN_capture : IN std_logic;
211  dpBSCAN_bscanid_en : IN std_logic;
212 
213 
214  poVoid : out std_ulogic
215 
216  );
217 
218 end Role_Themisto;
219 
220 
221 -- *****************************************************************************
222 -- ** ARCHITECTURE ** FLASH of ROLE
223 -- *****************************************************************************
224 
225 architecture Flash of Role_Themisto is
226 
227  constant cUSE_DEPRECATED_DIRECTIVES : boolean := false;
228 
229  --============================================================================
230  -- DEBUG SIGNALS ATTRIBUTE DECLARATIONS (see UG909)
231  --============================================================================
232  attribute X_INTERFACE_INFO : string;
233  attribute DEBUG : string;
234  attribute X_INTERFACE_INFO of dpBSCAN_drck: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN drck";
235  attribute DEBUG of dpBSCAN_drck: signal is "true";
236  attribute X_INTERFACE_INFO of dpBSCAN_shift: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN shift";
237  attribute DEBUG of dpBSCAN_shift: signal is "true";
238  attribute X_INTERFACE_INFO of dpBSCAN_tdi: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN tdi";
239  attribute DEBUG of dpBSCAN_tdi: signal is "true";
240  attribute X_INTERFACE_INFO of dpBSCAN_update: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN update";
241  attribute DEBUG of dpBSCAN_update: signal is "true";
242  attribute X_INTERFACE_INFO of dpBSCAN_sel: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN sel";
243  attribute DEBUG of dpBSCAN_sel: signal is "true";
244  attribute X_INTERFACE_INFO of dpBSCAN_tdo: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN tdo";
245  attribute DEBUG of dpBSCAN_tdo: signal is "true";
246  attribute X_INTERFACE_INFO of dpBSCAN_tms: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN tms";
247  attribute DEBUG of dpBSCAN_tms: signal is "true";
248  attribute X_INTERFACE_INFO of dpBSCAN_tck: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN tck";
249  attribute DEBUG of dpBSCAN_tck: signal is "true";
250  attribute X_INTERFACE_INFO of dpBSCAN_runtest: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN runtest";
251  attribute DEBUG of dpBSCAN_runtest: signal is "true";
252  attribute X_INTERFACE_INFO of dpBSCAN_reset: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN reset";
253  attribute DEBUG of dpBSCAN_reset: signal is "true";
254  attribute X_INTERFACE_INFO of dpBSCAN_capture: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN capture";
255  attribute DEBUG of dpBSCAN_capture: signal is "true";
256  attribute X_INTERFACE_INFO of dpBSCAN_bscanid_en: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN bscanid_en";
257  attribute DEBUG of dpBSCAN_bscanid_en: signal is "true";
258 
259  --============================================================================
260  -- SIGNAL DECLARATIONS
261  --============================================================================
262 
263 
264  -- signal EMIF_inv : std_logic_vector(7 downto 0);
265 
266  -- I hate Vivado HLS
267  signal sReadTlastAsVector : std_logic_vector(0 downto 0);
268  signal sWriteTlastAsVector : std_logic_vector(0 downto 0);
269  signal sResetAsVector : std_logic_vector(0 downto 0);
270 
271  signal sMetaOutTlastAsVector_Udp : std_logic_vector(0 downto 0);
272  signal sMetaInTlastAsVector_Udp : std_logic_vector(0 downto 0);
273  signal sMetaOutTlastAsVector_Tcp : std_logic_vector(0 downto 0);
274  signal sMetaInTlastAsVector_Tcp : std_logic_vector(0 downto 0);
275 
276  signal sUdpPostCnt : std_ulogic_vector(9 downto 0);
277  signal sTcpPostCnt : std_ulogic_vector(9 downto 0);
278 
279  --signal sMemTestDebugOut : std_logic_vector(15 downto 0);
280 
281  signal sAppReset_n : std_logic;
282 
283  --============================================================================
284  -- VARIABLE DECLARATIONS
285  --============================================================================
286 
287  --===========================================================================
288  --== COMPONENT DECLARATIONS
289  --===========================================================================
290  component UpperLowerApplication is
291  port (
292  ------------------------------------------------------
293  -- From SHELL / Clock and Reset
294  ------------------------------------------------------
295  ap_clk : in std_logic;
296  ap_rst_n : in std_logic;
297  -- rank and size
298  piFMC_ROL_rank_V : in std_logic_vector (31 downto 0);
299  piFMC_ROL_rank_V_ap_vld : in std_logic;
300  piFMC_ROL_size_V : in std_logic_vector (31 downto 0);
301  piFMC_ROL_size_V_ap_vld : in std_logic;
302  --------------------------------------------------------
303  -- From SHELL / Udp Data Interfaces
304  --------------------------------------------------------
305  siNrc_data_TDATA : in std_logic_vector( 63 downto 0);
306  siNrc_data_TKEEP : in std_logic_vector( 7 downto 0);
307  siNrc_data_TLAST : in std_logic;
308  siNrc_data_TVALID : in std_logic;
309  siNrc_data_TREADY : out std_logic;
310  --------------------------------------------------------
311  -- To SHELL / Udp Data Interfaces
312  --------------------------------------------------------
313  soNrc_data_TDATA : out std_logic_vector( 63 downto 0);
314  soNrc_data_TKEEP : out std_logic_vector( 7 downto 0);
315  soNrc_data_TLAST : out std_logic;
316  soNrc_data_TVALID : out std_logic;
317  soNrc_data_TREADY : in std_logic;
318  -- NRC Meta and Ports
319  siNrc_meta_TDATA : in std_logic_vector (63 downto 0);
320  siNrc_meta_TVALID : in std_logic;
321  siNrc_meta_TREADY : out std_logic;
322  siNrc_meta_TKEEP : in std_logic_vector (7 downto 0);
323  siNrc_meta_TLAST : in std_logic_vector (0 downto 0);
324 
325  soNrc_meta_TDATA : out std_logic_vector (63 downto 0);
326  soNrc_meta_TVALID : out std_logic;
327  soNrc_meta_TREADY : in std_logic;
328  soNrc_meta_TKEEP : out std_logic_vector (7 downto 0);
329  soNrc_meta_TLAST : out std_logic_vector (0 downto 0);
330 
331  poROL_NRC_Rx_ports_V : out std_logic_vector (31 downto 0);
332  poROL_NRC_Rx_ports_V_ap_vld : out std_logic
333  );
334  end component UpperLowerApplication;
335 
336 
337 
338  --===========================================================================
339  --== FUNCTION DECLARATIONS [TODO-Move to a package]
340  --===========================================================================
341  function fVectorize(s: std_logic) return std_logic_vector is
342  variable v: std_logic_vector(0 downto 0);
343  begin
344  v(0) := s;
345  return v;
346  end fVectorize;
347 
348  function fScalarize(v: in std_logic_vector) return std_ulogic is
349  begin
350  assert v'length = 1
351  report "scalarize: output port must be single bit!"
352  severity FAILURE;
353  return v(v'LEFT);
354  end;
355 
356 
357 --################################################################################
358 --# #
359 --# ##### #### #### # # #
360 --# # # # # # # # # #
361 --# # # # # # # ### #
362 --# ##### # # # # # #
363 --# # # # # # # # #
364 --# # # # # # # # #
365 --# ##### #### #### # #
366 --# #
367 --################################################################################
368 
369 begin
370 
371  --poSHL_Mmio_RdReg <= sMemTestDebugOut when (unsigned(piSHL_Mmio_WrReg) /= 0) else
372  -- x"BEEF";
373  -- to be use as ROLE VERSION IDENTIFICATION --
374  poSHL_Mmio_RdReg <= x"1DEA";
375 
376  sAppReset_n <= (not piMMIO_Ly7_Rst) and (piMMIO_Ly7_En);
377 
378 
379  --################################################################################
380  --# #
381  --# # # ##### ###### ##### #
382  --# # # # # # # # # ##### ##### #
383  --# # # # # # # # # # # # # #
384  --# # # # # ###### ####### ##### ##### #
385  --# # # # # # # # # # #
386  --# ####### ##### # # # # # #
387  --# #
388  --################################################################################
389 
390  -- gUdpAppFlashDepre : if cUSE_DEPRECATED_DIRECTIVES generate --TODO
391 
392  -- begin
393 
394  sMetaInTlastAsVector_Udp(0) <= siNRC_Role_Udp_Meta_TLAST;
395  soROLE_Nrc_Udp_Meta_TLAST <= sMetaOutTlastAsVector_Udp(0);
396 
397  UAF: UpperLowerApplication
398  port map (
399 
400  ------------------------------------------------------
401  -- From SHELL / Clock and Reset
402  ------------------------------------------------------
403  ap_clk => piSHL_156_25Clk,
404  --ap_rst_n => (not piMMIO_Ly7_Rst),
405  ap_rst_n => sAppReset_n,
406 
407  piFMC_ROL_rank_V => piFMC_ROLE_rank,
408  piFMC_ROL_rank_V_ap_vld => '1',
409  piFMC_ROL_size_V => piFMC_ROLE_size,
410  piFMC_ROL_size_V_ap_vld => '1',
411  --------------------------------------------------------
412  -- From SHELL / Udp Data Interfaces
413  --------------------------------------------------------
414  siNrc_data_TDATA => siNRC_Udp_Data_tdata,
415  siNrc_data_TKEEP => siNRC_Udp_Data_tkeep,
416  siNrc_data_TLAST => siNRC_Udp_Data_tlast,
417  siNrc_data_TVALID => siNRC_Udp_Data_tvalid,
418  siNrc_data_TREADY => siNRC_Udp_Data_tready,
419  --------------------------------------------------------
420  -- To SHELL / Udp Data Interfaces
421  --------------------------------------------------------
422  soNrc_data_TDATA => soNRC_Udp_Data_tdata,
423  soNrc_data_TKEEP => soNRC_Udp_Data_tkeep,
424  soNrc_data_TLAST => soNRC_Udp_Data_tlast,
425  soNrc_data_TVALID => soNRC_Udp_Data_tvalid,
426  soNrc_data_TREADY => soNRC_Udp_Data_tready,
427 
428  siNrc_meta_TDATA => siNRC_Role_Udp_Meta_TDATA ,
429  siNrc_meta_TVALID => siNRC_Role_Udp_Meta_TVALID ,
430  siNrc_meta_TREADY => siNRC_Role_Udp_Meta_TREADY ,
431  siNrc_meta_TKEEP => siNRC_Role_Udp_Meta_TKEEP ,
432  siNrc_meta_TLAST => sMetaInTlastAsVector_Udp,
433 
434  soNrc_meta_TDATA => soROLE_Nrc_Udp_Meta_TDATA ,
435  soNrc_meta_TVALID => soROLE_Nrc_Udp_Meta_TVALID ,
436  soNrc_meta_TREADY => soROLE_Nrc_Udp_Meta_TREADY ,
437  soNrc_meta_TKEEP => soROLE_Nrc_Udp_Meta_TKEEP ,
438  soNrc_meta_TLAST => sMetaOutTlastAsVector_Udp,
439 
440  poROL_NRC_Rx_ports_V => poROL_Nrc_Udp_Rx_ports
441  );
442 
443  --end generate;
444 
445 
446  --################################################################################
447  --# #
448  --# ####### #### ###### ##### #
449  --# # # # # # # ##### ##### #
450  --# # # # # # # # # # # #
451  --# # # ###### ####### ##### ##### #
452  --# # # # # # # # #
453  --# # #### # # # # # #
454  --# #
455  --################################################################################
456 
457  -- gUdpAppFlashDepre : if cUSE_DEPRECATED_DIRECTIVES generate --TODO
458 
459  -- begin
460 
461  sMetaInTlastAsVector_Tcp(0) <= siNRC_Role_Tcp_Meta_TLAST;
462  soROLE_Nrc_Tcp_Meta_TLAST <= sMetaOutTlastAsVector_Tcp(0);
463 
464  TAF: UpperLowerApplication
465  port map (
466 
467  ------------------------------------------------------
468  -- From SHELL / Clock and Reset
469  ------------------------------------------------------
470  ap_clk => piSHL_156_25Clk,
471  --ap_rst_n => (not piMMIO_Ly7_Rst),
472  ap_rst_n => sAppReset_n,
473 
474  piFMC_ROL_rank_V => piFMC_ROLE_rank,
475  piFMC_ROL_rank_V_ap_vld => '1',
476  piFMC_ROL_size_V => piFMC_ROLE_size,
477  piFMC_ROL_size_V_ap_vld => '1',
478  --------------------------------------------------------
479  -- From SHELL / Tcp Data Interfaces
480  --------------------------------------------------------
481  siNrc_data_TDATA => siNRC_Tcp_Data_tdata,
482  siNrc_data_TKEEP => siNRC_Tcp_Data_tkeep,
483  siNrc_data_TLAST => siNRC_Tcp_Data_tlast,
484  siNrc_data_TVALID => siNRC_Tcp_Data_tvalid,
485  siNrc_data_TREADY => siNRC_Tcp_Data_tready,
486  --------------------------------------------------------
487  -- To SHELL / Tcp Data Interfaces
488  --------------------------------------------------------
489  soNrc_data_TDATA => soNRC_Tcp_Data_tdata,
490  soNrc_data_TKEEP => soNRC_Tcp_Data_tkeep,
491  soNrc_data_TLAST => soNRC_Tcp_Data_tlast,
492  soNrc_data_TVALID => soNRC_Tcp_Data_tvalid,
493  soNrc_data_TREADY => soNRC_Tcp_Data_tready,
494 
495  siNrc_meta_TDATA => siNRC_Role_Tcp_Meta_TDATA ,
496  siNrc_meta_TVALID => siNRC_Role_Tcp_Meta_TVALID ,
497  siNrc_meta_TREADY => siNRC_Role_Tcp_Meta_TREADY ,
498  siNrc_meta_TKEEP => siNRC_Role_Tcp_Meta_TKEEP ,
499  siNrc_meta_TLAST => sMetaInTlastAsVector_Tcp,
500 
501  soNrc_meta_TDATA => soROLE_Nrc_Tcp_Meta_TDATA ,
502  soNrc_meta_TVALID => soROLE_Nrc_Tcp_Meta_TVALID ,
503  soNrc_meta_TREADY => soROLE_Nrc_Tcp_Meta_TREADY ,
504  soNrc_meta_TKEEP => soROLE_Nrc_Tcp_Meta_TKEEP ,
505  soNrc_meta_TLAST => sMetaOutTlastAsVector_Tcp,
506 
507  poROL_NRC_Rx_ports_V => poROL_Nrc_Tcp_Rx_ports
508  );
509 
510  --end generate;
511 
512 
513 
514  --################################################################################
515  -- 1st Memory Port dummy connections
516  --################################################################################
517  soMEM_Mp0_RdCmd_tdata <= (others => '0');
518  soMEM_Mp0_RdCmd_tvalid <= '0';
519  siMEM_Mp0_RdSts_tready <= '0';
520  siMEM_Mp0_Read_tready <= '0';
521  soMEM_Mp0_WrCmd_tdata <= (others => '0');
522  soMEM_Mp0_WrCmd_tvalid <= '0';
523  siMEM_Mp0_WrSts_tready <= '0';
524  soMEM_Mp0_Write_tdata <= (others => '0');
525  soMEM_Mp0_Write_tkeep <= (others => '0');
526  soMEM_Mp0_Write_tlast <= '0';
527  soMEM_Mp0_Write_tvalid <= '0';
528 
529 
530  --################################################################################
531  -- 2nd Memory Port dummy connections
532  --################################################################################
533 
534  moMEM_Mp1_AWVALID <= '0';
535  moMEM_Mp1_WVALID <= '0';
536  moMEM_Mp1_BREADY <= '0';
537  moMEM_Mp1_ARVALID <= '0';
538  moMEM_Mp1_RREADY <= '0';
539 
540 end architecture Flash;
541 
Role_Themisto
Definition: Role.vhdl:43
Role_Themisto.soNRC_Tcp_Data_tready
in soNRC_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:98
Role_Themisto.moMEM_Mp1_ARSIZE
out moMEM_Mp1_ARSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:169
Role_Themisto.moMEM_Mp1_AWADDR
out moMEM_Mp1_AWADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:151
Role_Themisto.soNRC_Udp_Data_tdata
out soNRC_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:65
Role_Themisto.soROLE_Nrc_Udp_Meta_TREADY
in soROLE_Nrc_Udp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:75
Role_Themisto.piSHL_156_25Clk
in piSHL_156_25Clkstd_ulogic
Definition: Role.vhdl:49
Role_Themisto.moMEM_Mp1_RREADY
out moMEM_Mp1_RREADYstd_ulogic
Definition: Role.vhdl:178
Role_Themisto.soROLE_Nrc_Udp_Meta_TKEEP
out soROLE_Nrc_Udp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:76
Role_Themisto.piSHL_156_25Rst
in piSHL_156_25Rststd_ulogic
Definition: Role.vhdl:50
Role_Themisto.dpBSCAN_tdi
in dpBSCAN_tdistd_logic
Definition: Role.vhdl:200
Role_Themisto.moMEM_Mp1_RLAST
in moMEM_Mp1_RLASTstd_ulogic
Definition: Role.vhdl:176
Role_Themisto.siNRC_Udp_Data_tlast
in siNRC_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:62
Role_Themisto.siMEM_Mp0_Read_tready
out siMEM_Mp0_Read_treadystd_ulogic
Definition: Role.vhdl:131
Role_Themisto.siNRC_Role_Udp_Meta_TKEEP
in siNRC_Role_Udp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:81
Role_Themisto.siMEM_Mp0_Read_tkeep
in siMEM_Mp0_Read_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:128
Role_Themisto.dpBSCAN_reset
in dpBSCAN_resetstd_logic
Definition: Role.vhdl:207
Role_Themisto.dpBSCAN_sel
in dpBSCAN_selstd_logic
Definition: Role.vhdl:202
Role_Themisto.dpBSCAN_drck
in dpBSCAN_drckstd_logic
Definition: Role.vhdl:198
Role_Themisto.soNRC_Tcp_Data_tdata
out soNRC_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:94
Role_Themisto.soROLE_Nrc_Tcp_Meta_TREADY
in soROLE_Nrc_Tcp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:104
Role_Themisto.siNRC_Role_Tcp_Meta_TLAST
in siNRC_Role_Tcp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:111
Role_Themisto.siMEM_Mp0_WrSts_tdata
in siMEM_Mp0_WrSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:137
Role_Themisto.soMEM_Mp0_Write_tkeep
out soMEM_Mp0_Write_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:142
Role_Themisto.siNRC_Tcp_Data_tready
out siNRC_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:92
Role_Themisto.siNRC_Role_Udp_Meta_TDATA
in siNRC_Role_Udp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:78
Role_Themisto.moMEM_Mp1_AWVALID
out moMEM_Mp1_AWVALIDstd_ulogic
Definition: Role.vhdl:155
Role_Themisto.siNRC_Role_Tcp_Meta_TVALID
in siNRC_Role_Tcp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:108
Role_Themisto.siNRC_Role_Tcp_Meta_TDATA
in siNRC_Role_Tcp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:107
Role_Themisto.moMEM_Mp1_BVALID
in moMEM_Mp1_BVALIDstd_ulogic
Definition: Role.vhdl:164
Role_Themisto.moMEM_Mp1_WSTRB
out moMEM_Mp1_WSTRBstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:158
Role_Themisto.moMEM_Mp1_BREADY
out moMEM_Mp1_BREADYstd_ulogic
Definition: Role.vhdl:165
Role_Themisto.moMEM_Mp1_AWID
out moMEM_Mp1_AWIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:150
Role_Themisto.moMEM_Mp1_RVALID
in moMEM_Mp1_RVALIDstd_ulogic
Definition: Role.vhdl:177
Role_Themisto.soNRC_Udp_Data_tready
in soNRC_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:69
Role_Themisto.soMEM_Mp0_WrCmd_tready
in soMEM_Mp0_WrCmd_treadystd_ulogic
Definition: Role.vhdl:135
Role_Themisto.siNRC_Udp_Data_tvalid
in siNRC_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:61
Role_Themisto.piMMIO_Ly7_En
in piMMIO_Ly7_Enstd_ulogic
Definition: Role.vhdl:53
Role_Themisto.soMEM_Mp0_Write_tready
in soMEM_Mp0_Write_treadystd_ulogic
Definition: Role.vhdl:145
Role_Themisto.soNRC_Udp_Data_tlast
out soNRC_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:68
Role_Themisto.soROLE_Nrc_Udp_Meta_TVALID
out soROLE_Nrc_Udp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:74
Role_Themisto.soROLE_Nrc_Tcp_Meta_TVALID
out soROLE_Nrc_Tcp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:103
Role_Themisto.moMEM_Mp1_WLAST
out moMEM_Mp1_WLASTstd_ulogic
Definition: Role.vhdl:159
Role_Themisto.soNRC_Udp_Data_tvalid
out soNRC_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:67
Role_Themisto.moMEM_Mp1_WDATA
out moMEM_Mp1_WDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:157
Role_Themisto.siNRC_Tcp_Data_tdata
in siNRC_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:88
Role_Themisto.soMEM_Mp0_RdCmd_tdata
out soMEM_Mp0_RdCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:119
Role_Themisto.siMEM_Mp0_Read_tdata
in siMEM_Mp0_Read_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:127
Role_Themisto.soMEM_Mp0_Write_tdata
out soMEM_Mp0_Write_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:141
Role_Themisto.siMEM_Mp0_RdSts_tready
out siMEM_Mp0_RdSts_treadystd_ulogic
Definition: Role.vhdl:125
Role_Themisto.moMEM_Mp1_ARBURST
out moMEM_Mp1_ARBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:170
Role_Themisto.siNRC_Role_Tcp_Meta_TKEEP
in siNRC_Role_Tcp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:110
Role_Themisto.siMEM_Mp0_RdSts_tdata
in siMEM_Mp0_RdSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:123
Role_Themisto.poROL_Nrc_Tcp_Rx_ports
out poROL_Nrc_Tcp_Rx_portsstd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:100
Role_Themisto.siNRC_Tcp_Data_tvalid
in siNRC_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:90
Role_Themisto.siNRC_Role_Udp_Meta_TLAST
in siNRC_Role_Udp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:82
Role_Themisto.moMEM_Mp1_ARREADY
in moMEM_Mp1_ARREADYstd_ulogic
Definition: Role.vhdl:172
Role_Themisto.siNRC_Udp_Data_tready
out siNRC_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:63
Role_Themisto.dpBSCAN_tms
in dpBSCAN_tmsstd_logic
Definition: Role.vhdl:204
Role_Themisto.moMEM_Mp1_RRESP
in moMEM_Mp1_RRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:175
Role_Themisto.soMEM_Mp0_Write_tlast
out soMEM_Mp0_Write_tlaststd_ulogic
Definition: Role.vhdl:143
Role_Themisto.moMEM_Mp1_ARID
out moMEM_Mp1_ARIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:166
Role_Themisto.dpBSCAN_capture
in dpBSCAN_capturestd_logic
Definition: Role.vhdl:208
Role_Themisto.soMEM_Mp0_WrCmd_tvalid
out soMEM_Mp0_WrCmd_tvalidstd_ulogic
Definition: Role.vhdl:134
Role_Themisto.moMEM_Mp1_ARVALID
out moMEM_Mp1_ARVALIDstd_ulogic
Definition: Role.vhdl:171
Role_Themisto.soROLE_Nrc_Tcp_Meta_TDATA
out soROLE_Nrc_Tcp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:102
Role_Themisto.moMEM_Mp1_AWBURST
out moMEM_Mp1_AWBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:154
Role_Themisto.siNRC_Udp_Data_tkeep
in siNRC_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:60
Role_Themisto.soMEM_Mp0_RdCmd_tvalid
out soMEM_Mp0_RdCmd_tvalidstd_ulogic
Definition: Role.vhdl:120
Role_Themisto.soNRC_Tcp_Data_tkeep
out soNRC_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:95
Role_Themisto.siMEM_Mp0_Read_tvalid
in siMEM_Mp0_Read_tvalidstd_ulogic
Definition: Role.vhdl:130
Role_Themisto.dpBSCAN_bscanid_en
in dpBSCAN_bscanid_enstd_logic
Definition: Role.vhdl:209
Role_Themisto.dpBSCAN_tdo
out dpBSCAN_tdostd_logic
Definition: Role.vhdl:203
Role_Themisto.moMEM_Mp1_RID
in moMEM_Mp1_RIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:173
Role_Themisto.soROLE_Nrc_Udp_Meta_TDATA
out soROLE_Nrc_Udp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:73
Role_Themisto.piFMC_ROLE_rank
in piFMC_ROLE_rankstd_logic_vector(31 downto 0)
Definition: Role.vhdl:192
Role_Themisto.soROLE_Nrc_Tcp_Meta_TKEEP
out soROLE_Nrc_Tcp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:105
Role_Themisto.piTOP_250_00Clk
in piTOP_250_00Clkstd_ulogic
Definition: Role.vhdl:187
Role_Themisto.moMEM_Mp1_AWLEN
out moMEM_Mp1_AWLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:152
Role_Themisto.piFMC_ROLE_size
in piFMC_ROLE_sizestd_logic_vector(31 downto 0)
Definition: Role.vhdl:193
Role_Themisto.siNRC_Tcp_Data_tkeep
in siNRC_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:89
Role_Themisto.soMEM_Mp0_RdCmd_tready
in soMEM_Mp0_RdCmd_treadystd_ulogic
Definition: Role.vhdl:121
Role_Themisto.moMEM_Mp1_WREADY
in moMEM_Mp1_WREADYstd_ulogic
Definition: Role.vhdl:161
Role_Themisto.siNRC_Role_Udp_Meta_TREADY
out siNRC_Role_Udp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:80
Role_Themisto.soNRC_Tcp_Data_tlast
out soNRC_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:97
Role_Themisto.siMEM_Mp0_RdSts_tvalid
in siMEM_Mp0_RdSts_tvalidstd_ulogic
Definition: Role.vhdl:124
Role_Themisto.soROLE_Nrc_Udp_Meta_TLAST
out soROLE_Nrc_Udp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:77
Role_Themisto.moMEM_Mp1_AWSIZE
out moMEM_Mp1_AWSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:153
Role_Themisto.dpBSCAN_shift
in dpBSCAN_shiftstd_logic
Definition: Role.vhdl:199
Role_Themisto.moMEM_Mp1_RDATA
in moMEM_Mp1_RDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:174
Role_Themisto.moMEM_Mp1_BID
in moMEM_Mp1_BIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:162
Role_Themisto.soMEM_Mp0_WrCmd_tdata
out soMEM_Mp0_WrCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:133
Role_Themisto.piMMIO_Ly7_Rst
in piMMIO_Ly7_Rststd_ulogic
Definition: Role.vhdl:52
Role_Themisto.poSHL_Mmio_RdReg
out poSHL_Mmio_RdRegstd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:182
Role_Themisto.siNRC_Role_Tcp_Meta_TREADY
out siNRC_Role_Tcp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:109
Role_Themisto.siNRC_Role_Udp_Meta_TVALID
in siNRC_Role_Udp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:79
Role_Themisto.moMEM_Mp1_BRESP
in moMEM_Mp1_BRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:163
Role_Themisto.moMEM_Mp1_WVALID
out moMEM_Mp1_WVALIDstd_ulogic
Definition: Role.vhdl:160
Role_Themisto.dpBSCAN_update
in dpBSCAN_updatestd_logic
Definition: Role.vhdl:201
Role_Themisto.siNRC_Udp_Data_tdata
in siNRC_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:59
Role_Themisto.moMEM_Mp1_ARLEN
out moMEM_Mp1_ARLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:168
Role_Themisto.soROLE_Nrc_Tcp_Meta_TLAST
out soROLE_Nrc_Tcp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:106
Role_Themisto.soNRC_Udp_Data_tkeep
out soNRC_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:66
Role_Themisto.siNRC_Tcp_Data_tlast
in siNRC_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:91
Role_Themisto.siMEM_Mp0_WrSts_tready
out siMEM_Mp0_WrSts_treadystd_ulogic
Definition: Role.vhdl:139
Role_Themisto.dpBSCAN_runtest
in dpBSCAN_runteststd_logic
Definition: Role.vhdl:206
Role_Themisto.siMEM_Mp0_WrSts_tvalid
in siMEM_Mp0_WrSts_tvalidstd_ulogic
Definition: Role.vhdl:138
Role_Themisto.soMEM_Mp0_Write_tvalid
out soMEM_Mp0_Write_tvalidstd_ulogic
Definition: Role.vhdl:144
Role_Themisto.moMEM_Mp1_ARADDR
out moMEM_Mp1_ARADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:167
Role_Themisto.poVoid
out poVoidstd_ulogic
Definition: Role.vhdl:213
Role_Themisto.moMEM_Mp1_AWREADY
in moMEM_Mp1_AWREADYstd_ulogic
Definition: Role.vhdl:156
Role_Themisto.poROL_Nrc_Udp_Rx_ports
out poROL_Nrc_Udp_Rx_portsstd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:71
Role_Themisto.siMEM_Mp0_Read_tlast
in siMEM_Mp0_Read_tlaststd_ulogic
Definition: Role.vhdl:129
Role_Themisto.dpBSCAN_tck
in dpBSCAN_tckstd_logic
Definition: Role.vhdl:205
Role_Themisto.soNRC_Tcp_Data_tvalid
out soNRC_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:96