cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
Role.vhdl
Go to the documentation of this file.
1 -- *
2 -- * cloudFPGA
3 -- * Copyright IBM Research, All Rights Reserved
4 -- * =============================================
5 -- * Created: Apr 2019
6 -- * Authors: FAB, WEI, NGL
7 -- *
8 -- * Description:
9 -- * ROLE template for Themisto SRA
10 -- *
11 
12 --******************************************************************************
13 --** CONTEXT CLAUSE ** FMKU60 ROLE(Flash)
14 --******************************************************************************
15 library IEEE;
16 use IEEE.std_logic_1164.all;
17 use IEEE.numeric_std.all;
18 
19 library UNISIM;
20 use UNISIM.vcomponents.all;
21 
22 -- library XIL_DEFAULTLIB;
23 -- use XIL_DEFAULTLIB.all;
24 
25 
26 --******************************************************************************
27 --** ENTITY ** FMKU60 ROLE
28 --******************************************************************************
29 
30 entity Role_Themisto is
31  port (
32 
33  --------------------------------------------------------
34  -- SHELL / Global Input Clock and Reset Interface
35  --------------------------------------------------------
36  piSHL_156_25Clk : in std_ulogic;
37  piSHL_156_25Rst : in std_ulogic;
38  -- LY7 Enable and Reset
39  piMMIO_Ly7_Rst : in std_ulogic;
40  piMMIO_Ly7_En : in std_ulogic;
41 
42  ------------------------------------------------------
43  -- SHELL / Role / Nts0 / Udp Interface
44  ------------------------------------------------------
45  ---- Input AXI-Write Stream Interface ----------
46  siNRC_Udp_Data_tdata : in std_ulogic_vector( 63 downto 0);
47  siNRC_Udp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
48  siNRC_Udp_Data_tvalid : in std_ulogic;
49  siNRC_Udp_Data_tlast : in std_ulogic;
50  siNRC_Udp_Data_tready : out std_ulogic;
51  ---- Output AXI-Write Stream Interface ---------
52  soNRC_Udp_Data_tdata : out std_ulogic_vector( 63 downto 0);
53  soNRC_Udp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
54  soNRC_Udp_Data_tvalid : out std_ulogic;
55  soNRC_Udp_Data_tlast : out std_ulogic;
56  soNRC_Udp_Data_tready : in std_ulogic;
57  -- Open Port vector
58  poROL_Nrc_Udp_Rx_ports : out std_ulogic_vector( 31 downto 0);
59  -- ROLE <-> NRC Meta Interface
60  soROLE_Nrc_Udp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
61  soROLE_Nrc_Udp_Meta_TVALID : out std_ulogic;
62  soROLE_Nrc_Udp_Meta_TREADY : in std_ulogic;
63  soROLE_Nrc_Udp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
64  soROLE_Nrc_Udp_Meta_TLAST : out std_ulogic;
65  siNRC_Role_Udp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
66  siNRC_Role_Udp_Meta_TVALID : in std_ulogic;
67  siNRC_Role_Udp_Meta_TREADY : out std_ulogic;
68  siNRC_Role_Udp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
69  siNRC_Role_Udp_Meta_TLAST : in std_ulogic;
70 
71  ------------------------------------------------------
72  -- SHELL / Role / Nts0 / Tcp Interface
73  ------------------------------------------------------
74  ---- Input AXI-Write Stream Interface ----------
75  siNRC_Tcp_Data_tdata : in std_ulogic_vector( 63 downto 0);
76  siNRC_Tcp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
77  siNRC_Tcp_Data_tvalid : in std_ulogic;
78  siNRC_Tcp_Data_tlast : in std_ulogic;
79  siNRC_Tcp_Data_tready : out std_ulogic;
80  ---- Output AXI-Write Stream Interface ---------
81  soNRC_Tcp_Data_tdata : out std_ulogic_vector( 63 downto 0);
82  soNRC_Tcp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
83  soNRC_Tcp_Data_tvalid : out std_ulogic;
84  soNRC_Tcp_Data_tlast : out std_ulogic;
85  soNRC_Tcp_Data_tready : in std_ulogic;
86  -- Open Port vector
87  poROL_Nrc_Tcp_Rx_ports : out std_ulogic_vector( 31 downto 0);
88  -- ROLE <-> NRC Meta Interface
89  soROLE_Nrc_Tcp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
90  soROLE_Nrc_Tcp_Meta_TVALID : out std_ulogic;
91  soROLE_Nrc_Tcp_Meta_TREADY : in std_ulogic;
92  soROLE_Nrc_Tcp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
93  soROLE_Nrc_Tcp_Meta_TLAST : out std_ulogic;
94  siNRC_Role_Tcp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
95  siNRC_Role_Tcp_Meta_TVALID : in std_ulogic;
96  siNRC_Role_Tcp_Meta_TREADY : out std_ulogic;
97  siNRC_Role_Tcp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
98  siNRC_Role_Tcp_Meta_TLAST : in std_ulogic;
99 
100 
101  --------------------------------------------------------
102  -- SHELL / Mem / Mp0 Interface
103  --------------------------------------------------------
104  ---- Memory Port #0 / S2MM-AXIS ----------------
105  ------ Stream Read Command ---------
106  soMEM_Mp0_RdCmd_tdata : out std_ulogic_vector( 79 downto 0);
107  soMEM_Mp0_RdCmd_tvalid : out std_ulogic;
108  soMEM_Mp0_RdCmd_tready : in std_ulogic;
109  ------ Stream Read Status ----------
110  siMEM_Mp0_RdSts_tdata : in std_ulogic_vector( 7 downto 0);
111  siMEM_Mp0_RdSts_tvalid : in std_ulogic;
112  siMEM_Mp0_RdSts_tready : out std_ulogic;
113  ------ Stream Data Input Channel ---
114  siMEM_Mp0_Read_tdata : in std_ulogic_vector(511 downto 0);
115  siMEM_Mp0_Read_tkeep : in std_ulogic_vector( 63 downto 0);
116  siMEM_Mp0_Read_tlast : in std_ulogic;
117  siMEM_Mp0_Read_tvalid : in std_ulogic;
118  siMEM_Mp0_Read_tready : out std_ulogic;
119  ------ Stream Write Command --------
120  soMEM_Mp0_WrCmd_tdata : out std_ulogic_vector( 79 downto 0);
121  soMEM_Mp0_WrCmd_tvalid : out std_ulogic;
122  soMEM_Mp0_WrCmd_tready : in std_ulogic;
123  ------ Stream Write Status ---------
124  siMEM_Mp0_WrSts_tdata : in std_ulogic_vector( 7 downto 0);
125  siMEM_Mp0_WrSts_tvalid : in std_ulogic;
126  siMEM_Mp0_WrSts_tready : out std_ulogic;
127  ------ Stream Data Output Channel --
128  soMEM_Mp0_Write_tdata : out std_ulogic_vector(511 downto 0);
129  soMEM_Mp0_Write_tkeep : out std_ulogic_vector( 63 downto 0);
130  soMEM_Mp0_Write_tlast : out std_ulogic;
131  soMEM_Mp0_Write_tvalid : out std_ulogic;
132  soMEM_Mp0_Write_tready : in std_ulogic;
133 
134  --------------------------------------------------------
135  -- SHELL / Mem / Mp1 Interface
136  --------------------------------------------------------
137  moMEM_Mp1_AWID : out std_ulogic_vector(3 downto 0);
138  moMEM_Mp1_AWADDR : out std_ulogic_vector(32 downto 0);
139  moMEM_Mp1_AWLEN : out std_ulogic_vector(7 downto 0);
140  moMEM_Mp1_AWSIZE : out std_ulogic_vector(2 downto 0);
141  moMEM_Mp1_AWBURST : out std_ulogic_vector(1 downto 0);
142  moMEM_Mp1_AWVALID : out std_ulogic;
143  moMEM_Mp1_AWREADY : in std_ulogic;
144  moMEM_Mp1_WDATA : out std_ulogic_vector(511 downto 0);
145  moMEM_Mp1_WSTRB : out std_ulogic_vector(63 downto 0);
146  moMEM_Mp1_WLAST : out std_ulogic;
147  moMEM_Mp1_WVALID : out std_ulogic;
148  moMEM_Mp1_WREADY : in std_ulogic;
149  moMEM_Mp1_BID : in std_ulogic_vector(3 downto 0);
150  moMEM_Mp1_BRESP : in std_ulogic_vector(1 downto 0);
151  moMEM_Mp1_BVALID : in std_ulogic;
152  moMEM_Mp1_BREADY : out std_ulogic;
153  moMEM_Mp1_ARID : out std_ulogic_vector(3 downto 0);
154  moMEM_Mp1_ARADDR : out std_ulogic_vector(32 downto 0);
155  moMEM_Mp1_ARLEN : out std_ulogic_vector(7 downto 0);
156  moMEM_Mp1_ARSIZE : out std_ulogic_vector(2 downto 0);
157  moMEM_Mp1_ARBURST : out std_ulogic_vector(1 downto 0);
158  moMEM_Mp1_ARVALID : out std_ulogic;
159  moMEM_Mp1_ARREADY : in std_ulogic;
160  moMEM_Mp1_RID : in std_ulogic_vector(3 downto 0);
161  moMEM_Mp1_RDATA : in std_ulogic_vector(511 downto 0);
162  moMEM_Mp1_RRESP : in std_ulogic_vector(1 downto 0);
163  moMEM_Mp1_RLAST : in std_ulogic;
164  moMEM_Mp1_RVALID : in std_ulogic;
165  moMEM_Mp1_RREADY : out std_ulogic;
166 
167  ---- [APP_RDROL] -------------------
168  -- to be use as ROLE VERSION IDENTIFICATION --
169  poSHL_Mmio_RdReg : out std_ulogic_vector( 15 downto 0);
170 
171  --------------------------------------------------------
172  -- TOP : Secondary Clock (Asynchronous)
173  --------------------------------------------------------
174  piTOP_250_00Clk : in std_ulogic; -- Freerunning
175 
176  ------------------------------------------------
177  -- SMC Interface
178  ------------------------------------------------
179  piFMC_ROLE_rank : in std_logic_vector(31 downto 0);
180  piFMC_ROLE_size : in std_logic_vector(31 downto 0);
181 
182  poVoid : out std_ulogic
183 
184  );
185 
186 end Role_Themisto;
187 
188 
189 -- *****************************************************************************
190 -- ** ARCHITECTURE ** FLASH of ROLE
191 -- *****************************************************************************
192 
193 architecture Flash of Role_Themisto is
194 
195  constant cUSE_DEPRECATED_DIRECTIVES : boolean := false;
196 
197  --============================================================================
198  -- SIGNAL DECLARATIONS
199  --============================================================================
200 
201 
202  -- signal EMIF_inv : std_logic_vector(7 downto 0);
203 
204  -- I hate Vivado HLS
205  signal sReadTlastAsVector : std_logic_vector(0 downto 0);
206  signal sWriteTlastAsVector : std_logic_vector(0 downto 0);
207  signal sResetAsVector : std_logic_vector(0 downto 0);
208 
209  signal sMetaOutTlastAsVector_Udp : std_logic_vector(0 downto 0);
210  signal sMetaInTlastAsVector_Udp : std_logic_vector(0 downto 0);
211  signal sMetaOutTlastAsVector_Tcp : std_logic_vector(0 downto 0);
212  signal sMetaInTlastAsVector_Tcp : std_logic_vector(0 downto 0);
213 
214  signal sUdpPostCnt : std_ulogic_vector(9 downto 0);
215  signal sTcpPostCnt : std_ulogic_vector(9 downto 0);
216 
217  --signal sMemTestDebugOut : std_logic_vector(15 downto 0);
218 
219  --============================================================================
220  -- VARIABLE DECLARATIONS
221  --============================================================================
222 
223  --===========================================================================
224  --== COMPONENT DECLARATIONS
225  --===========================================================================
226  component MCEuropeanEngineApplication is
227  port (
228  ------------------------------------------------------
229  -- From SHELL / Clock and Reset
230  ------------------------------------------------------
231  ap_clk : in std_logic;
232  ap_rst_n : in std_logic;
233  ap_start : in std_logic;
234 
235  -- rank and size
236  piFMC_ROL_rank_V : in std_logic_vector (31 downto 0);
237  --piSMC_ROL_rank_V_ap_vld : in std_logic;
238  piFMC_ROL_size_V : in std_logic_vector (31 downto 0);
239  --piSMC_ROL_size_V_ap_vld : in std_logic;
240  --------------------------------------------------------
241  -- From SHELL / Udp-Tcp Data Interfaces
242  --------------------------------------------------------
243  siSHL_This_Data_tdata : in std_logic_vector( 63 downto 0);
244  siSHL_This_Data_tkeep : in std_logic_vector( 7 downto 0);
245  siSHL_This_Data_tlast : in std_logic;
246  siSHL_This_Data_tvalid : in std_logic;
247  siSHL_This_Data_tready : out std_logic;
248  --------------------------------------------------------
249  -- To SHELL / Udp-Tcp Data Interfaces
250  --------------------------------------------------------
251  soTHIS_Shl_Data_tdata : out std_logic_vector( 63 downto 0);
252  soTHIS_Shl_Data_tkeep : out std_logic_vector( 7 downto 0);
253  soTHIS_Shl_Data_tlast : out std_logic;
254  soTHIS_Shl_Data_tvalid : out std_logic;
255  soTHIS_Shl_Data_tready : in std_logic;
256  -- NRC Meta and Ports
257  siNrc_meta_TDATA : in std_logic_vector (63 downto 0);
258  siNrc_meta_TVALID : in std_logic;
259  siNrc_meta_TREADY : out std_logic;
260  siNrc_meta_TKEEP : in std_logic_vector (7 downto 0);
261  siNrc_meta_TLAST : in std_logic_vector (0 downto 0);
262 
263  soNrc_meta_TDATA : out std_logic_vector (63 downto 0);
264  soNrc_meta_TVALID : out std_logic;
265  soNrc_meta_TREADY : in std_logic;
266  soNrc_meta_TKEEP : out std_logic_vector (7 downto 0);
267  soNrc_meta_TLAST : out std_logic_vector (0 downto 0);
268 
269  poROL_NRC_Rx_ports_V : out std_logic_vector (31 downto 0);
270  poROL_NRC_Rx_ports_V_ap_vld : out std_logic
271  );
272  end component MCEuropeanEngineApplication;
273 
274 
275 
276  --===========================================================================
277  --== FUNCTION DECLARATIONS [TODO-Move to a package]
278  --===========================================================================
279  function fVectorize(s: std_logic) return std_logic_vector is
280  variable v: std_logic_vector(0 downto 0);
281  begin
282  v(0) := s;
283  return v;
284  end fVectorize;
285 
286  function fScalarize(v: in std_logic_vector) return std_ulogic is
287  begin
288  assert v'length = 1
289  report "scalarize: output port must be single bit!"
290  severity FAILURE;
291  return v(v'LEFT);
292  end;
293 
294 
295 --################################################################################
296 --# #
297 --# ##### #### #### # # #
298 --# # # # # # # # # #
299 --# # # # # # # ### #
300 --# ##### # # # # # #
301 --# # # # # # # # #
302 --# # # # # # # # #
303 --# ##### #### #### # #
304 --# #
305 --################################################################################
306 
307 begin
308 
309  --poSHL_Mmio_RdReg <= sMemTestDebugOut when (unsigned(piSHL_Mmio_WrReg) /= 0) else
310  -- x"BEEF";
311  -- to be use as ROLE VERSION IDENTIFICATION --
312  poSHL_Mmio_RdReg <= x"BEEF";
313 
314 
315  --################################################################################
316  --# #
317  --# # # ##### ###### ##### #
318  --# # # # # # # # # ##### ##### #
319  --# # # # # # # # # # # # # #
320  --# # # # # ###### ####### ##### ##### #
321  --# # # # # # # # # # #
322  --# ####### ##### # # # # # #
323  --# #
324  --################################################################################
325 
326  -- gUdpAppFlashDepre : if cUSE_DEPRECATED_DIRECTIVES generate --TODO
327 
328  -- begin
329 
330  sMetaInTlastAsVector_Udp(0) <= siNRC_Role_Udp_Meta_TLAST;
331  soROLE_Nrc_Udp_Meta_TLAST <= sMetaOutTlastAsVector_Udp(0);
332 
333  UAF: MCEuropeanEngineApplication
334  port map (
335 
336  ------------------------------------------------------
337  -- From SHELL / Clock and Reset
338  ------------------------------------------------------
339  ap_clk => piSHL_156_25Clk,
340  ap_rst_n => (not piMMIO_Ly7_Rst),
341  ap_start => piMMIO_Ly7_En,
342 
343  piFMC_ROL_rank_V => piFMC_ROLE_rank,
344  --piFMC_ROL_rank_V_ap_vld => '1',
345  piFMC_ROL_size_V => piFMC_ROLE_size,
346  --piFMC_ROL_size_V_ap_vld => '1',
347  --------------------------------------------------------
348  -- From SHELL / Udp Data Interfaces
349  --------------------------------------------------------
350  siSHL_This_Data_tdata => siNRC_Udp_Data_tdata,
351  siSHL_This_Data_tkeep => siNRC_Udp_Data_tkeep,
352  siSHL_This_Data_tlast => siNRC_Udp_Data_tlast,
353  siSHL_This_Data_tvalid => siNRC_Udp_Data_tvalid,
354  siSHL_This_Data_tready => siNRC_Udp_Data_tready,
355  --------------------------------------------------------
356  -- To SHELL / Udp Data Interfaces
357  --------------------------------------------------------
358  soTHIS_Shl_Data_tdata => soNRC_Udp_Data_tdata,
359  soTHIS_Shl_Data_tkeep => soNRC_Udp_Data_tkeep,
360  soTHIS_Shl_Data_tlast => soNRC_Udp_Data_tlast,
361  soTHIS_Shl_Data_tvalid => soNRC_Udp_Data_tvalid,
362  soTHIS_Shl_Data_tready => soNRC_Udp_Data_tready,
363 
364  siNrc_meta_TDATA => siNRC_Role_Udp_Meta_TDATA ,
365  siNrc_meta_TVALID => siNRC_Role_Udp_Meta_TVALID ,
366  siNrc_meta_TREADY => siNRC_Role_Udp_Meta_TREADY ,
367  siNrc_meta_TKEEP => siNRC_Role_Udp_Meta_TKEEP ,
368  siNrc_meta_TLAST => sMetaInTlastAsVector_Udp,
369 
370  soNrc_meta_TDATA => soROLE_Nrc_Udp_Meta_TDATA ,
371  soNrc_meta_TVALID => soROLE_Nrc_Udp_Meta_TVALID ,
372  soNrc_meta_TREADY => soROLE_Nrc_Udp_Meta_TREADY ,
373  soNrc_meta_TKEEP => soROLE_Nrc_Udp_Meta_TKEEP ,
374  soNrc_meta_TLAST => sMetaOutTlastAsVector_Udp,
375 
376  poROL_NRC_Rx_ports_V => poROL_Nrc_Udp_Rx_ports
377  --poROL_NRC_Udp_Rx_ports_V_ap_vld => '1'
378  );
379 
380  --end generate;
381 
382 
383  --################################################################################
384  --# #
385  --# ####### #### ###### ##### #
386  --# # # # # # # ##### ##### #
387  --# # # # # # # # # # # #
388  --# # # ###### ####### ##### ##### #
389  --# # # # # # # # #
390  --# # #### # # # # # #
391  --# #
392  --################################################################################
393 
394  -- gUdpAppFlashDepre : if cUSE_DEPRECATED_DIRECTIVES generate --TODO
395 
396  -- begin
397 
398  sMetaInTlastAsVector_Tcp(0) <= siNRC_Role_Tcp_Meta_TLAST;
399  soROLE_Nrc_Tcp_Meta_TLAST <= sMetaOutTlastAsVector_Tcp(0);
400 
401 -- auto excluding TAF TAF: MCEuropeanEngineApplication
402 -- auto excluding TAF port map (
403 -- auto excluding TAF
404 -- auto excluding TAF ------------------------------------------------------
405 -- auto excluding TAF -- From SHELL / Clock and Reset
406 -- auto excluding TAF ------------------------------------------------------
407 -- auto excluding TAF ap_clk => piSHL_156_25Clk,
408 -- auto excluding TAF ap_rst_n => (not piMMIO_Ly7_Rst),
409 -- auto excluding TAF ap_start => piMMIO_Ly7_En,
410 -- auto excluding TAF
411 -- auto excluding TAF piFMC_ROL_rank_V => piFMC_ROLE_rank,
412 -- auto excluding TAF --piFMC_ROL_rank_V_ap_vld => '1',
413 -- auto excluding TAF piFMC_ROL_size_V => piFMC_ROLE_size,
414 -- auto excluding TAF --piFMC_ROL_size_V_ap_vld => '1',
415 -- auto excluding TAF --------------------------------------------------------
416 -- auto excluding TAF -- From SHELL / Tcp Data Interfaces
417 -- auto excluding TAF --------------------------------------------------------
418 -- auto excluding TAF siSHL_This_Data_tdata => siNRC_Tcp_Data_tdata,
419 -- auto excluding TAF siSHL_This_Data_tkeep => siNRC_Tcp_Data_tkeep,
420 -- auto excluding TAF siSHL_This_Data_tlast => siNRC_Tcp_Data_tlast,
421 -- auto excluding TAF siSHL_This_Data_tvalid => siNRC_Tcp_Data_tvalid,
422 -- auto excluding TAF siSHL_This_Data_tready => siNRC_Tcp_Data_tready,
423 -- auto excluding TAF --------------------------------------------------------
424 -- auto excluding TAF -- To SHELL / Tcp Data Interfaces
425 -- auto excluding TAF --------------------------------------------------------
426 -- auto excluding TAF soTHIS_Shl_Data_tdata => soNRC_Tcp_Data_tdata,
427 -- auto excluding TAF soTHIS_Shl_Data_tkeep => soNRC_Tcp_Data_tkeep,
428 -- auto excluding TAF soTHIS_Shl_Data_tlast => soNRC_Tcp_Data_tlast,
429 -- auto excluding TAF soTHIS_Shl_Data_tvalid => soNRC_Tcp_Data_tvalid,
430 -- auto excluding TAF soTHIS_Shl_Data_tready => soNRC_Tcp_Data_tready,
431 -- auto excluding TAF
432 -- auto excluding TAF siNrc_meta_TDATA => siNRC_Role_Tcp_Meta_TDATA ,
433 -- auto excluding TAF siNrc_meta_TVALID => siNRC_Role_Tcp_Meta_TVALID ,
434 -- auto excluding TAF siNrc_meta_TREADY => siNRC_Role_Tcp_Meta_TREADY ,
435 -- auto excluding TAF siNrc_meta_TKEEP => siNRC_Role_Tcp_Meta_TKEEP ,
436 -- auto excluding TAF siNrc_meta_TLAST => sMetaInTlastAsVector_Tcp,
437 -- auto excluding TAF
438 -- auto excluding TAF soNrc_meta_TDATA => soROLE_Nrc_Tcp_Meta_TDATA ,
439 -- auto excluding TAF soNrc_meta_TVALID => soROLE_Nrc_Tcp_Meta_TVALID ,
440 -- auto excluding TAF soNrc_meta_TREADY => soROLE_Nrc_Tcp_Meta_TREADY ,
441 -- auto excluding TAF soNrc_meta_TKEEP => soROLE_Nrc_Tcp_Meta_TKEEP ,
442 -- auto excluding TAF soNrc_meta_TLAST => sMetaOutTlastAsVector_Tcp,
443 -- auto excluding TAF
444 -- auto excluding TAF poROL_NRC_Rx_ports_V => poROL_Nrc_Tcp_Rx_ports
445 -- auto excluding TAF --poROL_NRC_Tcp_Rx_ports_V_ap_vld => '1'
446 -- auto excluding TAF );
447 
448 
449 
450  --################################################################################
451  -- TCP Port dummy connections
452  --################################################################################
453 
454  siNRC_Tcp_Data_tready <= '0';
455  soNRC_Tcp_Data_tdata <= (others => '0');
456  soNRC_Tcp_Data_tkeep <= (others => '0');
457  soNRC_Tcp_Data_tvalid <= '0';
458  soNRC_Tcp_Data_tlast <= '0';
459  poROL_Nrc_Tcp_Rx_ports <= (others => '0');
460  soROLE_Nrc_Tcp_Meta_TDATA <= (others => '0');
461  soROLE_Nrc_Tcp_Meta_TVALID <= '0';
462  soROLE_Nrc_Tcp_Meta_TKEEP <= (others => '0');
463  soROLE_Nrc_Tcp_Meta_TLAST <= '0';
464  siNRC_Role_Tcp_Meta_TREADY <= '0';
465 
466 
467 
468 
469  --end generate;
470 
471  --DEBUGING:
472  --poROL_Nrc_Tcp_Rx_ports <= (others => '0');
473 
474  --################################################################################
475  -- 1st Memory Port dummy connections
476  --################################################################################
477  soMEM_Mp0_RdCmd_tdata <= (others => '0');
478  soMEM_Mp0_RdCmd_tvalid <= '0';
479  siMEM_Mp0_RdSts_tready <= '0';
480  siMEM_Mp0_Read_tready <= '0';
481  soMEM_Mp0_WrCmd_tdata <= (others => '0');
482  soMEM_Mp0_WrCmd_tvalid <= '0';
483  siMEM_Mp0_WrSts_tready <= '0';
484  soMEM_Mp0_Write_tdata <= (others => '0');
485  soMEM_Mp0_Write_tkeep <= (others => '0');
486  soMEM_Mp0_Write_tlast <= '0';
487  soMEM_Mp0_Write_tvalid <= '0';
488 
489 
490  --################################################################################
491  -- 2nd Memory Port dummy connections
492  --################################################################################
493 
494  moMEM_Mp1_AWVALID <= '0';
495  moMEM_Mp1_WVALID <= '0';
496  moMEM_Mp1_BREADY <= '0';
497  moMEM_Mp1_ARVALID <= '0';
498  moMEM_Mp1_RREADY <= '0';
499 
500 end architecture Flash;
501 
Role_Themisto
Definition: Role.vhdl:43
Role_Themisto.soNRC_Tcp_Data_tready
in soNRC_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:98
Role_Themisto.moMEM_Mp1_ARSIZE
out moMEM_Mp1_ARSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:169
Role_Themisto.moMEM_Mp1_AWADDR
out moMEM_Mp1_AWADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:151
Role_Themisto.soNRC_Udp_Data_tdata
out soNRC_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:65
Role_Themisto.soROLE_Nrc_Udp_Meta_TREADY
in soROLE_Nrc_Udp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:75
Role_Themisto.piSHL_156_25Clk
in piSHL_156_25Clkstd_ulogic
Definition: Role.vhdl:49
Role_Themisto.moMEM_Mp1_RREADY
out moMEM_Mp1_RREADYstd_ulogic
Definition: Role.vhdl:178
Role_Themisto.soROLE_Nrc_Udp_Meta_TKEEP
out soROLE_Nrc_Udp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:76
Role_Themisto.piSHL_156_25Rst
in piSHL_156_25Rststd_ulogic
Definition: Role.vhdl:50
Role_Themisto.moMEM_Mp1_RLAST
in moMEM_Mp1_RLASTstd_ulogic
Definition: Role.vhdl:176
Role_Themisto.siNRC_Udp_Data_tlast
in siNRC_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:62
Role_Themisto.siMEM_Mp0_Read_tready
out siMEM_Mp0_Read_treadystd_ulogic
Definition: Role.vhdl:131
Role_Themisto.siNRC_Role_Udp_Meta_TKEEP
in siNRC_Role_Udp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:81
Role_Themisto.siMEM_Mp0_Read_tkeep
in siMEM_Mp0_Read_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:128
Role_Themisto.soNRC_Tcp_Data_tdata
out soNRC_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:94
Role_Themisto.soROLE_Nrc_Tcp_Meta_TREADY
in soROLE_Nrc_Tcp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:104
Role_Themisto.siNRC_Role_Tcp_Meta_TLAST
in siNRC_Role_Tcp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:111
Role_Themisto.siMEM_Mp0_WrSts_tdata
in siMEM_Mp0_WrSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:137
Role_Themisto.soMEM_Mp0_Write_tkeep
out soMEM_Mp0_Write_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:142
Role_Themisto.siNRC_Tcp_Data_tready
out siNRC_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:92
Role_Themisto.siNRC_Role_Udp_Meta_TDATA
in siNRC_Role_Udp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:78
Role_Themisto.moMEM_Mp1_AWVALID
out moMEM_Mp1_AWVALIDstd_ulogic
Definition: Role.vhdl:155
Role_Themisto.siNRC_Role_Tcp_Meta_TVALID
in siNRC_Role_Tcp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:108
Role_Themisto.siNRC_Role_Tcp_Meta_TDATA
in siNRC_Role_Tcp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:107
Role_Themisto.moMEM_Mp1_BVALID
in moMEM_Mp1_BVALIDstd_ulogic
Definition: Role.vhdl:164
Role_Themisto.moMEM_Mp1_WSTRB
out moMEM_Mp1_WSTRBstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:158
Role_Themisto.moMEM_Mp1_BREADY
out moMEM_Mp1_BREADYstd_ulogic
Definition: Role.vhdl:165
Role_Themisto.moMEM_Mp1_AWID
out moMEM_Mp1_AWIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:150
Role_Themisto.moMEM_Mp1_RVALID
in moMEM_Mp1_RVALIDstd_ulogic
Definition: Role.vhdl:177
Role_Themisto.soNRC_Udp_Data_tready
in soNRC_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:69
Role_Themisto.soMEM_Mp0_WrCmd_tready
in soMEM_Mp0_WrCmd_treadystd_ulogic
Definition: Role.vhdl:135
Role_Themisto.siNRC_Udp_Data_tvalid
in siNRC_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:61
Role_Themisto.piMMIO_Ly7_En
in piMMIO_Ly7_Enstd_ulogic
Definition: Role.vhdl:53
Role_Themisto.soMEM_Mp0_Write_tready
in soMEM_Mp0_Write_treadystd_ulogic
Definition: Role.vhdl:145
Role_Themisto.soNRC_Udp_Data_tlast
out soNRC_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:68
Role_Themisto.soROLE_Nrc_Udp_Meta_TVALID
out soROLE_Nrc_Udp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:74
Role_Themisto.soROLE_Nrc_Tcp_Meta_TVALID
out soROLE_Nrc_Tcp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:103
Role_Themisto.moMEM_Mp1_WLAST
out moMEM_Mp1_WLASTstd_ulogic
Definition: Role.vhdl:159
Role_Themisto.soNRC_Udp_Data_tvalid
out soNRC_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:67
Role_Themisto.moMEM_Mp1_WDATA
out moMEM_Mp1_WDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:157
Role_Themisto.siNRC_Tcp_Data_tdata
in siNRC_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:88
Role_Themisto.soMEM_Mp0_RdCmd_tdata
out soMEM_Mp0_RdCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:119
Role_Themisto.siMEM_Mp0_Read_tdata
in siMEM_Mp0_Read_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:127
Role_Themisto.soMEM_Mp0_Write_tdata
out soMEM_Mp0_Write_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:141
Role_Themisto.siMEM_Mp0_RdSts_tready
out siMEM_Mp0_RdSts_treadystd_ulogic
Definition: Role.vhdl:125
Role_Themisto.moMEM_Mp1_ARBURST
out moMEM_Mp1_ARBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:170
Role_Themisto.siNRC_Role_Tcp_Meta_TKEEP
in siNRC_Role_Tcp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:110
Role_Themisto.siMEM_Mp0_RdSts_tdata
in siMEM_Mp0_RdSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:123
Role_Themisto.poROL_Nrc_Tcp_Rx_ports
out poROL_Nrc_Tcp_Rx_portsstd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:100
Role_Themisto.siNRC_Tcp_Data_tvalid
in siNRC_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:90
Role_Themisto.siNRC_Role_Udp_Meta_TLAST
in siNRC_Role_Udp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:82
Role_Themisto.moMEM_Mp1_ARREADY
in moMEM_Mp1_ARREADYstd_ulogic
Definition: Role.vhdl:172
Role_Themisto.siNRC_Udp_Data_tready
out siNRC_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:63
Role_Themisto.moMEM_Mp1_RRESP
in moMEM_Mp1_RRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:175
Role_Themisto.soMEM_Mp0_Write_tlast
out soMEM_Mp0_Write_tlaststd_ulogic
Definition: Role.vhdl:143
Role_Themisto.moMEM_Mp1_ARID
out moMEM_Mp1_ARIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:166
Role_Themisto.soMEM_Mp0_WrCmd_tvalid
out soMEM_Mp0_WrCmd_tvalidstd_ulogic
Definition: Role.vhdl:134
Role_Themisto.moMEM_Mp1_ARVALID
out moMEM_Mp1_ARVALIDstd_ulogic
Definition: Role.vhdl:171
Role_Themisto.soROLE_Nrc_Tcp_Meta_TDATA
out soROLE_Nrc_Tcp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:102
Role_Themisto.moMEM_Mp1_AWBURST
out moMEM_Mp1_AWBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:154
Role_Themisto.siNRC_Udp_Data_tkeep
in siNRC_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:60
Role_Themisto.soMEM_Mp0_RdCmd_tvalid
out soMEM_Mp0_RdCmd_tvalidstd_ulogic
Definition: Role.vhdl:120
Role_Themisto.soNRC_Tcp_Data_tkeep
out soNRC_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:95
Role_Themisto.siMEM_Mp0_Read_tvalid
in siMEM_Mp0_Read_tvalidstd_ulogic
Definition: Role.vhdl:130
Role_Themisto.moMEM_Mp1_RID
in moMEM_Mp1_RIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:173
Role_Themisto.soROLE_Nrc_Udp_Meta_TDATA
out soROLE_Nrc_Udp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:73
Role_Themisto.piFMC_ROLE_rank
in piFMC_ROLE_rankstd_logic_vector(31 downto 0)
Definition: Role.vhdl:192
Role_Themisto.soROLE_Nrc_Tcp_Meta_TKEEP
out soROLE_Nrc_Tcp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:105
Role_Themisto.piTOP_250_00Clk
in piTOP_250_00Clkstd_ulogic
Definition: Role.vhdl:187
Role_Themisto.moMEM_Mp1_AWLEN
out moMEM_Mp1_AWLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:152
Role_Themisto.piFMC_ROLE_size
in piFMC_ROLE_sizestd_logic_vector(31 downto 0)
Definition: Role.vhdl:193
Role_Themisto.siNRC_Tcp_Data_tkeep
in siNRC_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:89
Role_Themisto.soMEM_Mp0_RdCmd_tready
in soMEM_Mp0_RdCmd_treadystd_ulogic
Definition: Role.vhdl:121
Role_Themisto.moMEM_Mp1_WREADY
in moMEM_Mp1_WREADYstd_ulogic
Definition: Role.vhdl:161
Role_Themisto.siNRC_Role_Udp_Meta_TREADY
out siNRC_Role_Udp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:80
Role_Themisto.soNRC_Tcp_Data_tlast
out soNRC_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:97
Role_Themisto.siMEM_Mp0_RdSts_tvalid
in siMEM_Mp0_RdSts_tvalidstd_ulogic
Definition: Role.vhdl:124
Role_Themisto.soROLE_Nrc_Udp_Meta_TLAST
out soROLE_Nrc_Udp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:77
Role_Themisto.moMEM_Mp1_AWSIZE
out moMEM_Mp1_AWSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:153
Role_Themisto.moMEM_Mp1_RDATA
in moMEM_Mp1_RDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:174
Role_Themisto.moMEM_Mp1_BID
in moMEM_Mp1_BIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:162
Role_Themisto.soMEM_Mp0_WrCmd_tdata
out soMEM_Mp0_WrCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:133
Role_Themisto.piMMIO_Ly7_Rst
in piMMIO_Ly7_Rststd_ulogic
Definition: Role.vhdl:52
Role_Themisto.poSHL_Mmio_RdReg
out poSHL_Mmio_RdRegstd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:182
Role_Themisto.siNRC_Role_Tcp_Meta_TREADY
out siNRC_Role_Tcp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:109
Role_Themisto.siNRC_Role_Udp_Meta_TVALID
in siNRC_Role_Udp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:79
Role_Themisto.moMEM_Mp1_BRESP
in moMEM_Mp1_BRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:163
Role_Themisto.moMEM_Mp1_WVALID
out moMEM_Mp1_WVALIDstd_ulogic
Definition: Role.vhdl:160
Role_Themisto.siNRC_Udp_Data_tdata
in siNRC_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:59
Role_Themisto.moMEM_Mp1_ARLEN
out moMEM_Mp1_ARLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:168
Role_Themisto.soROLE_Nrc_Tcp_Meta_TLAST
out soROLE_Nrc_Tcp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:106
Role_Themisto.soNRC_Udp_Data_tkeep
out soNRC_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:66
Role_Themisto.siNRC_Tcp_Data_tlast
in siNRC_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:91
Role_Themisto.siMEM_Mp0_WrSts_tready
out siMEM_Mp0_WrSts_treadystd_ulogic
Definition: Role.vhdl:139
Role_Themisto.siMEM_Mp0_WrSts_tvalid
in siMEM_Mp0_WrSts_tvalidstd_ulogic
Definition: Role.vhdl:138
Role_Themisto.soMEM_Mp0_Write_tvalid
out soMEM_Mp0_Write_tvalidstd_ulogic
Definition: Role.vhdl:144
Role_Themisto.moMEM_Mp1_ARADDR
out moMEM_Mp1_ARADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:167
Role_Themisto.poVoid
out poVoidstd_ulogic
Definition: Role.vhdl:213
Role_Themisto.moMEM_Mp1_AWREADY
in moMEM_Mp1_AWREADYstd_ulogic
Definition: Role.vhdl:156
Role_Themisto.poROL_Nrc_Udp_Rx_ports
out poROL_Nrc_Udp_Rx_portsstd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:71
Role_Themisto.siMEM_Mp0_Read_tlast
in siMEM_Mp0_Read_tlaststd_ulogic
Definition: Role.vhdl:129
Role_Themisto.soNRC_Tcp_Data_tvalid
out soNRC_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:96