cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
Generics | Libraries | Ports | Use Clauses
DualPortAsymmetricRam Entity Reference

Libraries

IEEE 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 

Generics

gDataWidth_A  integer := 8
gSize_A  integer := 1024
gAddrWidth_A  integer := 10
gDataWidth_B  integer := 64
gSize_B  integer := 128
gAddrWidth_B  integer := 7

Ports

piClkA   in   std_logic
piEnA   in   std_logic
piWenA   in   std_logic
piAddrA   in   std_logic_vector ( gAddrWidth_A - 1 downto 0 )
piDataA   in   std_logic_vector ( gDataWidth_A - 1 downto 0 )
poDataA   out   std_logic_vector ( gDataWidth_A - 1 downto 0 )
piClkB   in   std_logic
piEnB   in   std_logic
piWenB   in   std_logic
piAddrB   in   std_logic_vector ( gAddrWidth_B - 1 downto 0 )
piDataB   in   std_logic_vector ( gDataWidth_B - 1 downto 0 )
poDataB   out   std_logic_vector ( gDataWidth_B - 1 downto 0 )

Detailed Description

Definition at line 51 of file dpAsymRam.vhd.

Member Data Documentation

◆ gAddrWidth_A

gAddrWidth_A integer := 10
Generic

Definition at line 55 of file dpAsymRam.vhd.

◆ gAddrWidth_B

gAddrWidth_B integer := 7
Generic

Definition at line 59 of file dpAsymRam.vhd.

◆ gDataWidth_A

gDataWidth_A integer := 8
Generic

Definition at line 53 of file dpAsymRam.vhd.

◆ gDataWidth_B

gDataWidth_B integer := 64
Generic

Definition at line 56 of file dpAsymRam.vhd.

◆ gSize_A

gSize_A integer := 1024
Generic

Definition at line 54 of file dpAsymRam.vhd.

◆ gSize_B

gSize_B integer := 128
Generic

Definition at line 57 of file dpAsymRam.vhd.

◆ IEEE

IEEE
Library

Definition at line 42 of file dpAsymRam.vhd.

◆ piAddrA

piAddrA in std_logic_vector ( gAddrWidth_A - 1 downto 0 )
Port

Definition at line 65 of file dpAsymRam.vhd.

◆ piAddrB

piAddrB in std_logic_vector ( gAddrWidth_B - 1 downto 0 )
Port

Definition at line 72 of file dpAsymRam.vhd.

◆ piClkA

piClkA in std_logic
Port

Definition at line 62 of file dpAsymRam.vhd.

◆ piClkB

piClkB in std_logic
Port

Definition at line 69 of file dpAsymRam.vhd.

◆ piDataA

piDataA in std_logic_vector ( gDataWidth_A - 1 downto 0 )
Port

Definition at line 66 of file dpAsymRam.vhd.

◆ piDataB

piDataB in std_logic_vector ( gDataWidth_B - 1 downto 0 )
Port

Definition at line 73 of file dpAsymRam.vhd.

◆ piEnA

piEnA in std_logic
Port

Definition at line 63 of file dpAsymRam.vhd.

◆ piEnB

piEnB in std_logic
Port

Definition at line 70 of file dpAsymRam.vhd.

◆ piWenA

piWenA in std_logic
Port

Definition at line 64 of file dpAsymRam.vhd.

◆ piWenB

piWenB in std_logic
Port

Definition at line 71 of file dpAsymRam.vhd.

◆ poDataA

poDataA out std_logic_vector ( gDataWidth_A - 1 downto 0 )
Port

Definition at line 67 of file dpAsymRam.vhd.

◆ poDataB

poDataB out std_logic_vector ( gDataWidth_B - 1 downto 0 )
Port

Definition at line 75 of file dpAsymRam.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 43 of file dpAsymRam.vhd.

◆ std_logic_arith

std_logic_arith
use clause

Definition at line 45 of file dpAsymRam.vhd.

◆ std_logic_unsigned

std_logic_unsigned
use clause

Definition at line 44 of file dpAsymRam.vhd.

The documentation for this class was generated from the following file: