MEM

Memory Sub-System (MEM). This component implements the dynamic memory controllers for the FPGA module FMKU2595 equipped with a XCKU060. This memory sub-system implements two DDR4 memory channels (MC0 and MC1 ), each with a capacity of 8GB. By convention, the memory channel #0 (MC0) is dedicated to the network transport and session (NTS) stack, and the memory channel #1 (MC1) is reserved for the user application. The documentation of MEM is available at https://pages.github.ibm.com/cloudFPGA/Doc/pages/cfdk.html#memory-sub-system-mem. More...

Collaboration diagram for MEM:

Files
file	mem.hpp
	: Memory Sub-System (MEM) for the cloudFPGA shell.

Classes
struct	DmCmd
struct	DmSts

Macros
#define	KU60_MEM_BANK0_SIZE   8*1024*1024
#define	KU60_MEM_BANK1_SIZE   8*1024*1024

Detailed Description

Memory Sub-System (MEM). This component implements the dynamic memory controllers for the FPGA module FMKU2595 equipped with a XCKU060. This memory sub-system implements two DDR4 memory channels (MC0 and MC1 ), each with a capacity of 8GB. By convention, the memory channel #0 (MC0) is dedicated to the network transport and session (NTS) stack, and the memory channel #1 (MC1) is reserved for the user application. The documentation of MEM is available at https://pages.github.ibm.com/cloudFPGA/Doc/pages/cfdk.html#memory-sub-system-mem.

Macro Definition Documentation

KU60_MEM_BANK0_SIZE

#define KU60_MEM_BANK0_SIZE   8*1024*1024

GLOBAL DEFINITIONS USED BY MEM

Definition at line 69 of file mem.hpp.

KU60_MEM_BANK1_SIZE

#define KU60_MEM_BANK1_SIZE   8*1024*1024

Definition at line 70 of file mem.hpp.