RLB

Ready Logic Barrier (RLB) for the Network Transport Stack (NTS). More...

Collaboration diagram for RLB:

Modules
	RLB_TEST
	Testbench for the Ready Logic Barrier (RLB) for the Network Transport Stack (NTS).

Files
file	test_uoe.cpp
	: Testbench for the UDP Offload Engine (UOE).
file	test_rlb.hpp
	: Testbench for the UDP Offload Engine (UOE).

Macros
#define	THIS_NAME   "RLB"
#define	TRACE_OFF   0x0000
#define	TRACE_TODO   1 << 1
#define	TRACE_ALL   0xFFFF
#define	DEBUG_LEVEL   (TRACE_OFF)

Functions
void	rlb (StsBit *poMMIO_Ready, stream< StsBool > &siUOE_Ready, stream< StsBool > &siTOE_Ready)
	Main process of the Ready Logic Barrier (RLB). More...

Variables
bool	gTraceEvent

Detailed Description

Ready Logic Barrier (RLB) for the Network Transport Stack (NTS).

Macro Definition Documentation

DEBUG_LEVEL

#define DEBUG_LEVEL   (TRACE_OFF)

Definition at line 49 of file rlb.cpp.

THIS_NAME

#define THIS_NAME   "RLB"

Definition at line 43 of file rlb.cpp.

TRACE_ALL

#define TRACE_ALL   0xFFFF

Definition at line 47 of file rlb.cpp.

TRACE_OFF

#define TRACE_OFF   0x0000

Definition at line 45 of file rlb.cpp.

TRACE_TODO

#define TRACE_TODO   1 << 1

Definition at line 46 of file rlb.cpp.

Function Documentation

rlb()

void rlb	(	StsBit *	poMMIO_Ready,
		stream< StsBool > &	siUOE_Ready,
		stream< StsBool > &	siTOE_Ready
	)

Main process of the Ready Logic Barrier (RLB).

– MMIO Interface

Parameters

[out]	poMMIO_Ready	Ready signal to [SHELL/MMIO]. – UOE / Ready Data Stream
[in]	siUOE_Ready	Ready data stream from UdpOffloadEngine (UOE). – TOE / Ready Data Stream
[in]	siTOE_Ready	Ready data stream from TcpOffloadEngine (TOE).

ENTITY - READY LOGIC BARRIER (RLB)

Definition at line 62 of file rlb.cpp.

{
  #if HLS_VERSION == 2017
    //-- DIRECTIVES FOR THE INTERFACES ----------------------------------------
    #pragma HLS INTERFACE ap_ctrl_none port=return
 
 
 
 
 
    #pragma HLS INTERFACE ap_none register   port=poMMIO_Ready   name=poMMIO_Ready
    #pragma HLS RESOURCE core=AXI4Stream variable=siUOE_Ready    metadata="-bus_bundle siUOE_Ready"
    #pragma HLS RESOURCE core=AXI4Stream variable=siTOE_Ready    metadata="-bus_bundle siTOE_Ready"
 
    //-- DIRECTIVES FOR THIS PROCESS -------------------------------------------
    #pragma HLS pipeline II=1
#else
    //-- DIRECTIVES FOR THE INTERFACES -----------------------------------------
    #pragma HLS INTERFACE ap_ctrl_none port=return
 
    #pragma HLS INTERFACE ap_none register      port=poMMIO_Ready   name=poMMIO_Ready
    #pragma HLS INTERFACE axis    register both port=siUOE_Ready    name=siUOE_Ready
    #pragma HLS INTERFACE axis    register both port=siTOE_Ready    name=siTOE_Ready
 
    //-- DIRECTIVES FOR THIS PROCESS -------------------------------------------
    #pragma HLS PIPELINE II=1 enable_flush
    #pragma HLS INLINE off
#endif
 
    const char *myName  = concat2(THIS_NAME, "RLB");
 
    //-- STATIC CONTROL VARIABLES (with RESET) --------------------------------
    static enum FsmStates { BARRIER=0, SYNC } rlb_fsmState;
    #pragma HLS RESET                variable=rlb_fsmState
    static StsBool                            rlb_uoeReady;
    #pragma HSL RESET                variable=rlb_uoeReady
    static StsBool                            rlb_toeReady;
    #pragma HSL RESET                variable=rlb_toeReady
 
    switch(rlb_fsmState) {
    case BARRIER:
        *poMMIO_Ready = 0;
        if(!siUOE_Ready.empty()) {
            siUOE_Ready.read(rlb_uoeReady);
        }
        if(!siTOE_Ready.empty()) {
            siTOE_Ready.read(rlb_toeReady);
        }
        if (rlb_uoeReady and rlb_toeReady) {
            rlb_fsmState = SYNC;
        }
        break;
    case SYNC:
        *poMMIO_Ready = 1;
        break;
    }
}

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Variable Documentation

gTraceEvent

bool gTraceEvent

extern

HELPERS FOR THE DEBUGGING TRACES .e.g: DEBUG_LEVEL = (TRACE_MPd | TRACE_IBUF)

HELPERS FOR THE DEBUGGING TRACES .e.g: DEBUG_LEVEL = (MDL_TRACE | IPS_TRACE)

Definition at line 151 of file tb_nal.cpp.