cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)

Ready Logic Barrier (RLB) for the Network Transport Stack (NTS). More...

Collaboration diagram for RLB:

Modules

 RLB_TEST
 Testbench for the Ready Logic Barrier (RLB) for the Network Transport Stack (NTS).
 

Files

file  test_uoe.cpp
 : Testbench for the UDP Offload Engine (UOE).
 
file  test_rlb.hpp
 : Testbench for the UDP Offload Engine (UOE).
 

Macros

#define THIS_NAME   "RLB"
 
#define TRACE_OFF   0x0000
 
#define TRACE_TODO   1 << 1
 
#define TRACE_ALL   0xFFFF
 
#define DEBUG_LEVEL   (TRACE_OFF)
 

Functions

void rlb (StsBit *poMMIO_Ready, stream< StsBool > &siUOE_Ready, stream< StsBool > &siTOE_Ready)
 Main process of the Ready Logic Barrier (RLB). More...
 

Variables

bool gTraceEvent
 

Detailed Description

Ready Logic Barrier (RLB) for the Network Transport Stack (NTS).

Macro Definition Documentation

◆ DEBUG_LEVEL

#define DEBUG_LEVEL   (TRACE_OFF)

Definition at line 49 of file rlb.cpp.

◆ THIS_NAME

#define THIS_NAME   "RLB"

Definition at line 43 of file rlb.cpp.

◆ TRACE_ALL

#define TRACE_ALL   0xFFFF

Definition at line 47 of file rlb.cpp.

◆ TRACE_OFF

#define TRACE_OFF   0x0000

Definition at line 45 of file rlb.cpp.

◆ TRACE_TODO

#define TRACE_TODO   1 << 1

Definition at line 46 of file rlb.cpp.

Function Documentation

◆ rlb()

void rlb ( StsBit poMMIO_Ready,
stream< StsBool > &  siUOE_Ready,
stream< StsBool > &  siTOE_Ready 
)

Main process of the Ready Logic Barrier (RLB).

– MMIO Interface

Parameters
[out]poMMIO_ReadyReady signal to [SHELL/MMIO]. – UOE / Ready Data Stream
[in]siUOE_ReadyReady data stream from UdpOffloadEngine (UOE). – TOE / Ready Data Stream
[in]siTOE_ReadyReady data stream from TcpOffloadEngine (TOE).

ENTITY - READY LOGIC BARRIER (RLB)

Definition at line 62 of file rlb.cpp.

78 {
79  #if HLS_VERSION == 2017
80  //-- DIRECTIVES FOR THE INTERFACES ----------------------------------------
81  #pragma HLS INTERFACE ap_ctrl_none port=return
82 
83 
84 
85 
86 
87  #pragma HLS INTERFACE ap_none register port=poMMIO_Ready name=poMMIO_Ready
88  #pragma HLS RESOURCE core=AXI4Stream variable=siUOE_Ready metadata="-bus_bundle siUOE_Ready"
89  #pragma HLS RESOURCE core=AXI4Stream variable=siTOE_Ready metadata="-bus_bundle siTOE_Ready"
90 
91  //-- DIRECTIVES FOR THIS PROCESS -------------------------------------------
92  #pragma HLS pipeline II=1
93 #else
94  //-- DIRECTIVES FOR THE INTERFACES -----------------------------------------
95  #pragma HLS INTERFACE ap_ctrl_none port=return
96 
97  #pragma HLS INTERFACE ap_none register port=poMMIO_Ready name=poMMIO_Ready
98  #pragma HLS INTERFACE axis register both port=siUOE_Ready name=siUOE_Ready
99  #pragma HLS INTERFACE axis register both port=siTOE_Ready name=siTOE_Ready
100 
101  //-- DIRECTIVES FOR THIS PROCESS -------------------------------------------
102  #pragma HLS PIPELINE II=1 enable_flush
103  #pragma HLS INLINE off
104 #endif
105 
106  const char *myName = concat2(THIS_NAME, "RLB");
107 
108  //-- STATIC CONTROL VARIABLES (with RESET) --------------------------------
109  static enum FsmStates { BARRIER=0, SYNC } rlb_fsmState;
110  #pragma HLS RESET variable=rlb_fsmState
111  static StsBool rlb_uoeReady;
112  #pragma HSL RESET variable=rlb_uoeReady
113  static StsBool rlb_toeReady;
114  #pragma HSL RESET variable=rlb_toeReady
115 
116  switch(rlb_fsmState) {
117  case BARRIER:
118  *poMMIO_Ready = 0;
119  if(!siUOE_Ready.empty()) {
120  siUOE_Ready.read(rlb_uoeReady);
121  }
122  if(!siTOE_Ready.empty()) {
123  siTOE_Ready.read(rlb_toeReady);
124  }
125  if (rlb_uoeReady and rlb_toeReady) {
126  rlb_fsmState = SYNC;
127  }
128  break;
129  case SYNC:
130  *poMMIO_Ready = 1;
131  break;
132  }
133 }
bool StsBool
Definition: nal.hpp:246
#define THIS_NAME
Definition: rlb.cpp:43
#define concat2(firstCharConst, secondCharConst)
Definition: nts_utils.hpp:159
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Variable Documentation

◆ gTraceEvent

bool gTraceEvent
extern

HELPERS FOR THE DEBUGGING TRACES .e.g: DEBUG_LEVEL = (TRACE_MPd | TRACE_IBUF)

HELPERS FOR THE DEBUGGING TRACES .e.g: DEBUG_LEVEL = (MDL_TRACE | IPS_TRACE)

Definition at line 151 of file tb_nal.cpp.