cloudFPGA (cF) API
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rlb.hpp
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/*
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* Copyright 2016 -- 2021 IBM Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _RLB_H
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#define _RLB_H
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#include "../../../NTS/nts.hpp"
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#include "../../../NTS/nts_utils.hpp"
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#include "../../../NTS/SimNtsUtils.hpp"
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void
rlb
(
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//------------------------------------------------------
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//-- MMIO Interface
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//------------------------------------------------------
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StsBit
*poMMIO_Ready,
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//------------------------------------------------------
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//-- UOE / Data Stream Interface
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//------------------------------------------------------
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stream<StsBool> &siUOE_Ready,
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//------------------------------------------------------
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//-- TOE / Data Stream Interface
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//------------------------------------------------------
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stream<StsBool> &siTOE_Ready
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);
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#endif
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rlb
void rlb(StsBit *poMMIO_Ready, stream< StsBool > &siUOE_Ready, stream< StsBool > &siTOE_Ready)
Main process of the Ready Logic Barrier (RLB).
Definition:
rlb.cpp:62
StsBit
ap_uint< 1 > StsBit
Definition:
nts_types.hpp:116
repos_for_Dox
cFDK
SRA
LIB
SHELL
LIB
hls
NTS
rlb
src
rlb.hpp
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