tb_fmc.cpp File Reference

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#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include "../src/fmc.hpp"
#include "../../../../../hls/cfdk.hpp"
#include "../../../../../hls/network.hpp"
#include "../../../../../hls/axi_utils.hpp"
#include "../../NAL/src/nal.hpp"
#include <stdint.h>
#include <hls_stream.h>
#include <sys/time.h>

Include dependency graph for tb_fmc.cpp:

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Macros
#define	DEBUG
#define	HWICAP_SEQ_SIZE   ((16*IN_BUFFER_SIZE + 512)/4)
#define	HWICAP_SEQ_START_ADDRESS   1024

Functions
stream< Axis< 8 > >	FMC_Debug_Pyrolink ("FMC_Debug_Pyrolink")
stream< Axis< 8 > >	Debug_FMC_Pyrolink ("Debug_FMC_Pyrolink")
stream< TcpWord >	sFMC_NAL_Tcp_data ("sFMC_Nal_Tcp_data")
stream< AppMeta >	sFMC_NAL_Tcp_sessId ("sFMC_Nal_Tcp_sessId")
stream< TcpWord >	sNAL_FMC_Tcp_data ("sNAL_FMC_Tcp_data")
stream< AppMeta >	sNAL_FMC_Tcp_sessId ("sNAL_FMC_Tcp_sessId")
ap_uint< 32 >	reverse_byte_order (ap_uint< 32 > input)
void	stepDut ()
	Run a single iteration of the DUT model. More...
bool	checkResult (ap_uint< 32 > MMIO, ap_uint< 32 > expected)
void	printBuffer (volatile uint8_t *buffer_int, char *msg, int max_pages)
void	printBuffer32 (ap_uint< 32 > buffer_int[(32 *16)], char *msg, int max_pages)
bool	checkSeqHwicap (uint32_t *true_buffer, ap_uint< 32 > *out_buffer, uint32_t start_address, uint32_t end_address, bool not_to_swap)
void	initBuffer (ap_uint< 4 > cnt, ap_uint< 32 > xmem[(32 *16)], bool lastPage, bool withPattern)
ap_uint< 64 >	initStream (ap_uint< 4 > cnt, stream< NetworkWord > &tcp_data, int nr_words, bool with_pattern, bool inverse_upper, bool insert_tlast)
void	copyBufferToXmem (char *buffer_int, ap_uint< 32 > xmem[(32 *16)])
void	copyBufferToStream (char *buffer_int, stream< NetworkWord > &tcp_data, int content_len)
void	drainStream (stream< NetworkWord > &tcp_data)
int	main ()

Variables
ap_uint< 32 >	MMIO_in = 0x0
ap_uint< 32 >	MMIO
ap_uint< 32 >	MMIO_in_BE
ap_uint< 32 >	MMIO_out_BE
ap_uint< 1 >	layer_4_enabled = 0b1
ap_uint< 1 >	layer_6_enabled = 0b0
ap_uint< 1 >	layer_7_enabled = 0b0
ap_uint< 1 >	nts_ready = 0b1
ap_uint< 16 >	role_mmio = 0x1DEA
ap_uint< 16 >	uoe_drop_cnt = 0x0
ap_uint< 8 >	toe_notif_drop_cnt = 0
ap_uint< 8 >	toe_meta_drop_cnt = 0
ap_uint< 8 >	toe_data_drop_cnt = 0
ap_uint< 8 >	toe_crc_drop_cnt = 0
ap_uint< 8 >	toe_sess_drop_cnt = 0
ap_uint< 8 >	toe_ooo_drop_cnt = 0
ap_uint< 32 >	sim_fpga_time_seconds = 0
ap_uint< 32 >	sim_fpga_time_minutes = 0
ap_uint< 32 >	sim_fpga_time_hours = 0
ap_uint< 1 >	decoupActive = 0b0
ap_uint< 1 >	decoupStatus = 0b0
ap_uint< 1 >	softReset = 0b0
ap_uint< 32 >	nodeRank_out
ap_uint< 32 >	clusterSize_out
ap_uint< 32 >	HWICAP [512]
uint8_t	HWICAP_seq_IN [((16 *4096+512)/4) *4]
ap_uint< 32 >	HWICAP_seq_OUT [((16 *4096+512)/4)]
ap_uint< 32 >	xmem [(32 *16)]
ap_uint< 32 >	nalCtrl [(0x3ff/4)]
ap_uint< 1 >	disable_ctrl_link = 0b0
ap_uint< 1 >	disable_pyro_link = 0b0
int	simCnt

Detailed Description

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Copyright 2016 – 2021 IBM Corporation

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

System: : cloudFPGA Component : Shell, FPGA Management Core (FMC) Language : Vivado HLS

Definition in file tb_fmc.cpp.