test_sobel.cpp File Reference

: Testbench for Sobel. More...

#include "../include/sobel.hpp"
#include "../../common/src/common.cpp"

Include dependency graph for test_sobel.cpp:

Go to the source code of this file.

Macros
#define	THIS_NAME   "TB"
#define	TRACE_OFF   0x0000
#define	TRACE_URIF   1 << 1
#define	TRACE_UAF   1 << 2
#define	TRACE_MMIO   1 << 3
#define	TRACE_ALL   0xFFFF
#define	DEBUG_LEVEL   (TRACE_ALL)
#define	OK   true
#define	KO   false
#define	VALID   true
#define	UNVALID   false
#define	DEBUG_TRACE   true
#define	TB_TRIALS   2
#define	ENABLE_DDR_EMULATE_DELAY_IN_TB
#define	ENABLED   (ap_uint<1>)1
#define	DISABLED   (ap_uint<1>)0
#define	MEMORY_LINES_512   TOTMEMDW_512 /* 64 KiB */

Functions
stream< UdpWord >	sSHL_Uaf_Data ("sSHL_Uaf_Data")
stream< UdpWord >	sUAF_Shl_Data ("sUAF_Shl_Data")
stream< UdpWord >	image_stream_from_sobel ("image_stream_from_sobel")
stream< NetworkMetaStream >	siUdp_meta ("siUdp_meta")
stream< NetworkMetaStream >	soUdp_meta ("soUdp_meta")
stream< DmCmd >	sROL_Shl_Mem_RdCmdP0 ("sROL_Shl_Mem_RdCmdP0")
stream< DmSts >	sSHL_Rol_Mem_RdStsP0 ("sSHL_Rol_Mem_RdStsP0")
stream< Axis< 512 > >	sSHL_Rol_Mem_ReadP0 ("sSHL_Rol_Mem_ReadP0")
stream< DmCmd >	sROL_Shl_Mem_WrCmdP0 ("sROL_Shl_Mem_WrCmdP0")
stream< DmSts >	sSHL_Rol_Mem_WrStsP0 ("sSHL_Rol_Mem_WrStsP0")
stream< Axis< 512 > >	sROL_Shl_Mem_WriteP0 ("sROL_Shl_Mem_WriteP0")
void	stepDut ()
	Run a single iteration of the DUT model. More...
int	main (int argc, char **argv)
	Main testbench of Hrris. More...

Variables
ap_uint< 1 >	piSHL_This_MmioPostPktEn
ap_uint< 1 >	piSHL_This_MmioCaptPktEn
ap_uint< 32 >	s_udp_rx_ports = 0x0
ap_uint< 32 >	node_rank
ap_uint< 32 >	cluster_size
membus_t	lcl_mem0 [(1+(IMGSIZE - 1)/(512/8))]
membus_t	lcl_mem1 [(1+(IMGSIZE - 1)/(512/8))]
int	simCnt

Detailed Description

: Testbench for Sobel.

Copyright 2016 – 2022 IBM Corporation

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

System: : cloudFPGA Component : Role Language : Vivado HLS

Created: Nov 2021 Authors: FAB, WEI, NGL, DID, DCO

Copyright 2009-2015 - Xilinx Inc. - All rights reserved. Copyright 2015-2020 - IBM Research - All Rights Reserved.

Definition in file test_sobel.cpp.