cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
test_toe.hpp
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43 
56 #ifndef _TEST_TOE_H_
57 #define _TEST_TOE_H_
58 
59 #include <ap_shift_reg.h>
60 #include <cstdio>
61 #include <iostream>
62 #include <fstream>
63 #include <map>
64 #include <set>
65 #include <string>
66 #include <unistd.h>
67 
68 #include "../../../NTS/nts_config.hpp"
69 #include "../../../NTS/nts_utils.hpp"
70 #include "../../../NTS/SimNtsUtils.hpp"
71 #include "../../../NTS/SimAppData.hpp"
72 #include "../../../NTS/SimIp4Packet.hpp"
73 #include "../../../NTS/toe/src/toe.hpp"
74 #include "../../../NTS/toe/src/toe_utils.hpp"
75 #include "../../../NTS/toe/test/dummy_memory/dummy_memory.hpp"
76 
77 
78 //---------------------------------------------------------
79 //-- TESTBENCH GLOBAL DEFINES
80 // 'STARTUP_DELAY' is used to delay the start of the [TB] functions.
81 //---------------------------------------------------------
82 #define TB_STARTUP_DELAY (TOE_SIZEOF_LISTEN_PORT_TABLE)
83 #define TB_GRACE_TIME 2500 // Adds some cycles to drain the DUT before exiting
84 
85 //#define TB_MAX_SIM_CYCLES 2500000
86 //#define TB_MIN_SIM_CYCLES 1000
87 #define TB_STARTUP_TIME 25
88 
89 //---------------------------------------------------------
90 //-- DEFAULT LOCAL FPGA AND FOREIGN HOST SOCKETS
91 //-- By default, the following sockets will be used by the
92 //-- testbench, unless the user specifies new ones via the
93 //-- test vector files.
94 //---------------------------------------------------------
95 #define DEFAULT_FPGA_IP4_ADDR 0x0A0CC801 // TOE's local IP Address = 10.12.200.01
96 #define DEFAULT_FPGA_LSN_PORT 0x0057 // TOE listens on port = 87 (static ports must be 0..32767)
97 #define DEFAULT_FPGA_SND_PORT TOE_FIRST_EPHEMERAL_PORT_NUM // TOE's ephemeral port # = 32768
98 
99 #define DEFAULT_HOST_IP4_ADDR 0x0A0CC832 // TB's foreign IP Address = 10.12.200.50
100 #define DEFAULT_HOST_LSN_PORT 0x0058 // TB listens on port = 88
101 #define DEFAULT_HOST_SND_PORT 0x8058 // TB's ephemeral port # = 32856
102 
103 //---------------------------------------------------------
104 //-- TESTBENCH MODES OF OPERATION
105 //---------------------------------------------------------
106 enum TestingMode { RX_MODE='0', TX_MODE='1', BIDIR_MODE='2', ECHO_MODE='3' };
107 
108 //---------------------------------------------------------
109 //-- C/RTL LATENCIES AND INITIAL INTERVALS
110 //-- Use numbers >= to those of the 'CoSimulation Report'
111 //---------------------------------------------------------
112 #define APP_RSP_LATENCY 10 // [FIXME - "ipRx_TwentyPkt.dat" will fail if latency goes down to 5.
113 
114 #define MEM_RD_CMD_LATENCY 10
115 #define MEM_RD_DAT_LATENCY 10
116 #define MEM_RD_STS_LATENCY 10
117 
118 #define MEM_WR_CMD_LATENCY 10
119 #define MEM_WR_DAT_LATENCY 10
120 #define MEM_WR_STS_LATENCY 10
121 
122 #define CAM_LOOKUP_LATENCY 1
123 #define CAM_UPDATE_LATENCY 10
124 
125 #define RTT_LINK 25
126 
127 #define FPGA_CLIENT_CONNECT_TIMEOUT 250 // In clock cycles
128 
129 //---------------------------------------------------------
130 //-- TESTBENCH GLOBAL VARIABLES
131 //-- These variables might be updated/overwritten by the
132 //-- content of a test-vector file.
133 //---------------------------------------------------------
134 bool gTraceEvent = false;
135 bool gFatalError = false;
136 unsigned int gSimCycCnt = 0;
138 //unsigned int gMaxSimCycles = TB_MIN_SIM_CYCLES + TB_GRACE_TIME;
139 
140 Ip4Addr gFpgaIp4Addr = DEFAULT_FPGA_IP4_ADDR; // IPv4 address (in NETWORK BYTE ORDER)
143 Ip4Addr gHostIp4Addr = DEFAULT_HOST_IP4_ADDR; // IPv4 address (in NETWORK BYTE ORDER)
145 bool gSortTaifGold = false; // Do not sort soTAIF.gold file
146 
147 bool gTest_RcvdIp4Packet = true; // Check the received IPv4 packet
148 bool gTest_RcvdIp4TotLen = true; // Check the received IPv4-Total-Length field
149 bool gTest_RcvdIp4HdrCsum = true; // Check the received IPv4-Header-Checksum field
150 bool gTest_RcvdUdpLen = true; // Check the received UDP-Length field
151 bool gTest_RcvdLy4Csum = true; // Check the received TCP|UDP Layer-4-Checksum field
152 bool gTest_SentIp4TotLen = true; // Check the sent IPv4-Total-Length field
153 bool gTest_SentIp4HdrCsum = true; // Check the sent IPv4-Header-Checksum field
154 bool gTest_SentUdpLen = true; // Check the sent UDP-Length field
155 bool gTest_SentLy4Csum = true; // Check the sent TCP|UDP Layer-4-Checksum field
156 
157 #endif
158 
bool gTest_RcvdIp4Packet
Definition: test_toe.hpp:147
TestingMode
#define DEFAULT_FPGA_LSN_PORT
Definition: test_toe.hpp:96
#define TB_STARTUP_DELAY
Definition: test_toe.hpp:82
#define DEFAULT_HOST_LSN_PORT
Definition: test_toe.hpp:100
Ip4Addr gHostIp4Addr
Definition: test_toe.hpp:143
#define TB_GRACE_TIME
Definition: test_toe.hpp:83
TcpPort gFpgaLsnPort
Definition: test_toe.hpp:141
bool gTest_RcvdLy4Csum
Definition: test_toe.hpp:151
TcpPort gFpgaSndPort
Definition: test_toe.hpp:142
bool gTest_SentIp4TotLen
Definition: test_toe.hpp:152
bool gTest_SentIp4HdrCsum
Definition: test_toe.hpp:153
unsigned int gMaxSimCycles
Definition: test_toe.hpp:137
unsigned int gSimCycCnt
Definition: test_toe.hpp:136
bool gTraceEvent
Definition: test_toe.hpp:134
Ip4Addr gFpgaIp4Addr
Definition: test_toe.hpp:140
bool gTest_SentLy4Csum
Definition: test_toe.hpp:155
bool gFatalError
Definition: test_toe.hpp:135
#define DEFAULT_HOST_IP4_ADDR
Definition: test_toe.hpp:99
bool gTest_RcvdIp4HdrCsum
Definition: test_toe.hpp:149
bool gTest_RcvdIp4TotLen
Definition: test_toe.hpp:148
bool gSortTaifGold
Definition: test_toe.hpp:145
#define DEFAULT_FPGA_IP4_ADDR
Definition: test_toe.hpp:95
bool gTest_RcvdUdpLen
Definition: test_toe.hpp:150
TcpPort gHostLsnPort
Definition: test_toe.hpp:144
bool gTest_SentUdpLen
Definition: test_toe.hpp:154
@ TX_MODE
Definition: test_toe.hpp:106
@ BIDIR_MODE
Definition: test_toe.hpp:106
@ ECHO_MODE
Definition: test_toe.hpp:106
@ RX_MODE
Definition: test_toe.hpp:106
#define TOE_FIRST_EPHEMERAL_PORT_NUM
Definition: toe.hpp:101
ap_uint< 32 > Ip4Addr
Definition: AxisIp4.hpp:169
ap_uint< 16 > TcpPort
Definition: AxisTcp.hpp:105