cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
Role.vhdl
Go to the documentation of this file.
1 -- /*******************************************************************************
2 -- * Copyright 2016 -- 2021 IBM Corporation
3 -- *
4 -- * Licensed under the Apache License, Version 2.0 (the "License");
5 -- * you may not use this file except in compliance with the License.
6 -- * You may obtain a copy of the License at
7 -- *
8 -- * http://www.apache.org/licenses/LICENSE-2.0
9 -- *
10 -- * Unless required by applicable law or agreed to in writing, software
11 -- * distributed under the License is distributed on an "AS IS" BASIS,
12 -- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 -- * See the License for the specific language governing permissions and
14 -- * limitations under the License.
15 -- *******************************************************************************/
16 
17 -- *****************************************************************************
18 -- *
19 -- * cloudFPGA
20 -- *
21 -- *----------------------------------------------------------------------------
22 -- *
23 -- * Title : Role for the bring-up of the FMKU2595 when equipped with a XCKU060.
24 -- *
25 -- * File : Role.vhdl
26 -- *
27 -- * Created : Feb 2018
28 -- * Authors : Francois Abel <fab@zurich.ibm.com>
29 -- * Beat Weiss <wei@zurich.ibm.com>
30 -- * Burkhard Ringlein <ngl@zurich.ibm.com>
31 -- *
32 -- * Devices : xcku060-ffva1156-2-i
33 -- * Tools : Vivado v2016.4, 2017.4 (64-bit)
34 -- * Depends : None
35 -- *
36 -- * Description : In cloudFPGA, the user application is referred to as a 'ROLE'
37 -- * and is integrated along with a 'SHELL' that abstracts the HW components
38 -- * of the FPGA module.
39 -- * The current module contains the boot Flash application of the FPGA card
40 -- * that is specified here as a 'ROLE'. Such a role is referred to as a
41 -- * "superuser" role because it cannot be instantiated by a non-priviledged
42 -- * cloudFPGA user.
43 -- *
44 -- * As the name of the entity indicates, this ROLE implements the following
45 -- * interfaces with the SHELL:
46 -- * - one UDP port interface (based on the AXI4-Stream interface),
47 -- * - one TCP port interface (based on the AXI4-Stream interface),
48 -- * - two Memory Port interfaces (based on the MM2S and S2MM AXI4-Stream
49 -- * interfaces described in PG022-AXI-DataMover).
50 -- *
51 -- * Parameters: None.
52 -- *
53 -- *
54 -- *****************************************************************************
55 
56 --******************************************************************************
57 --** CONTEXT CLAUSE ** FMKU60 ROLE(Flash)
58 --******************************************************************************
59 library IEEE;
60 use IEEE.std_logic_1164.all;
61 use IEEE.numeric_std.all;
62 
63 library UNISIM;
64 use UNISIM.vcomponents.all;
65 
66 -- library XIL_DEFAULTLIB;
67 -- use XIL_DEFAULTLIB.all;
68 
69 
70 --******************************************************************************
71 --** ENTITY ** FMKU60 ROLE
72 --******************************************************************************
73 
74 entity Role_Kale is
75  port (
76 
77  --------------------------------------------------------
78  -- SHELL / Clock, Reset and Enable Interface
79  --------------------------------------------------------
80  piSHL_156_25Clk : in std_ulogic;
81  piSHL_156_25Rst : in std_ulogic;
82 
83  --------------------------------------------------------
84  -- SHELL / Nts / Udp Interface
85  --------------------------------------------------------
86  -- Input UDP Data (AXI4S) ----------
87  siSHL_Nts_Udp_Data_tdata : in std_ulogic_vector( 63 downto 0);
88  siSHL_Nts_Udp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
89  siSHL_Nts_Udp_Data_tlast : in std_ulogic;
90  siSHL_Nts_Udp_Data_tvalid : in std_ulogic;
91  siSHL_Nts_Udp_Data_tready : out std_ulogic;
92  -- Output UDP Data (AXI4S) ---------
93  soSHL_Nts_Udp_Data_tdata : out std_ulogic_vector( 63 downto 0);
94  soSHL_Nts_Udp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
95  soSHL_Nts_Udp_Data_tlast : out std_ulogic;
96  soSHL_Nts_Udp_Data_tvalid : out std_ulogic;
97  soSHL_Nts_Udp_Data_tready : in std_ulogic;
98 
99  ------------------------------------------------------
100  -- SHELL / Nts / Tcp / TxP Data Flow Interfaces
101  ------------------------------------------------------
102  -- FPGA Transmit Path (ROLE-->SHELL) ---------
103  ---- Stream TCP Data ---------------
104  soSHL_Nts_Tcp_Data_tdata : out std_ulogic_vector( 63 downto 0);
105  soSHL_Nts_Tcp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
106  soSHL_Nts_Tcp_Data_tlast : out std_ulogic;
107  soSHL_Nts_Tcp_Data_tvalid : out std_ulogic;
108  soSHL_Nts_Tcp_Data_tready : in std_ulogic;
109  ---- Stream TCP Metadata -----------
110  soSHL_Nts_Tcp_Meta_tdata : out std_ulogic_vector( 15 downto 0);
111  soSHL_Nts_Tcp_Meta_tvalid : out std_ulogic;
112  soSHL_Nts_Tcp_Meta_tready : in std_ulogic;
113  ---- Stream TCP Data Status --------
114  siSHL_Nts_Tcp_DSts_tdata : in std_ulogic_vector( 23 downto 0);
115  siSHL_Nts_Tcp_DSts_tvalid : in std_ulogic;
116  siSHL_Nts_Tcp_DSts_tready : out std_ulogic;
117 
118  --------------------------------------------------------
119  -- SHELL / Nts / Tcp / RxP Data Flow Interfaces
120  --------------------------------------------------------
121  -- FPGA Receive Path (SHELL-->ROLE) ----------
122  ---- Stream TCP Data ---------------
123  siSHL_Nts_Tcp_Data_tdata : in std_ulogic_vector( 63 downto 0);
124  siSHL_Nts_Tcp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
125  siSHL_Nts_Tcp_Data_tlast : in std_ulogic;
126  siSHL_Nts_Tcp_Data_tvalid : in std_ulogic;
127  siSHL_Nts_Tcp_Data_tready : out std_ulogic;
128  ---- Stream TCP Meta ---------------
129  siSHL_Nts_Tcp_Meta_tdata : in std_ulogic_vector( 15 downto 0);
130  siSHL_Nts_Tcp_Meta_tkeep : in std_ulogic_vector( 1 downto 0);
131  siSHL_Nts_Tcp_Meta_tlast : in std_ulogic;
132  siSHL_Nts_Tcp_Meta_tvalid : in std_ulogic;
133  siSHL_Nts_Tcp_Meta_tready : out std_ulogic;
134  ---- Stream TCP Data Notification --
135  siSHL_Nts_Tcp_Notif_tdata : in std_ulogic_vector(7+96 downto 0);
136  siSHL_Nts_Tcp_Notif_tvalid : in std_ulogic;
137  siSHL_Nts_Tcp_Notif_tready : out std_ulogic;
138  ---- Stream TCP Data Request -------
139  soSHL_Nts_Tcp_DReq_tdata : out std_ulogic_vector( 31 downto 0);
140  soSHL_Nts_Tcp_DReq_tvalid : out std_ulogic;
141  soSHL_Nts_Tcp_DReq_tready : in std_ulogic;
142 
143  ------------------------------------------------------
144  -- SHELL / Nts / Tcp / TxP Ctlr Flow Interfaces
145  ------------------------------------------------------
146  -- FPGA Transmit Path (ROLE-->SHELL) ---------
147  ---- Stream TCP Open Session Request
148  soSHL_Nts_Tcp_OpnReq_tdata : out std_ulogic_vector( 47 downto 0);
149  soSHL_Nts_Tcp_OpnReq_tvalid : out std_ulogic;
150  soSHL_Nts_Tcp_OpnReq_tready : in std_ulogic;
151  ---- Stream TCP Open Session Reply -
152  siSHL_Nts_Tcp_OpnRep_tdata : in std_ulogic_vector( 23 downto 0);
153  siSHL_Nts_Tcp_OpnRep_tvalid : in std_ulogic;
154  siSHL_Nts_Tcp_OpnRep_tready : out std_ulogic;
155  ---- Stream TCP Close Request ------
156  soSHL_Nts_Tcp_ClsReq_tdata : out std_ulogic_vector( 15 downto 0);
157  soSHL_Nts_Tcp_ClsReq_tvalid : out std_ulogic;
158  soSHL_Nts_Tcp_ClsReq_tready : in std_ulogic;
159 
160  ------------------------------------------------------
161  -- SHELL / Nts / Tcp / RxP Ctlr Flow Interfaces
162  ------------------------------------------------------
163  -- FPGA Receive Path (SHELL-->ROLE) ----------
164  ---- Stream TCP Listen Request -----
165  soSHL_Nts_Tcp_LsnReq_tdata : out std_ulogic_vector( 15 downto 0);
166  soSHL_Nts_Tcp_LsnReq_tvalid : out std_ulogic;
167  soSHL_Nts_Tcp_LsnReq_tready : in std_ulogic;
168  ---- Stream TCP Listen Acknnoledge -
169  siSHL_Nts_Tcp_LsnAck_tdata : in std_ulogic_vector( 7 downto 0);
170  siSHL_Nts_Tcp_LsnAck_tvalid : in std_ulogic;
171  siSHL_Nts_Tcp_LsnAck_tready : out std_ulogic;
172 
173  --------------------------------------------------------
174  -- SHELL / Mem / Mp0 Interface
175  --------------------------------------------------------
176  ---- Memory Port #0 / S2MM-AXIS ----------------
177  ------ Stream Read Command ---------
178  soSHL_Mem_Mp0_RdCmd_tdata : out std_ulogic_vector( 79 downto 0);
179  soSHL_Mem_Mp0_RdCmd_tvalid : out std_ulogic;
180  soSHL_Mem_Mp0_RdCmd_tready : in std_ulogic;
181  ------ Stream Read Status ----------
182  siSHL_Mem_Mp0_RdSts_tdata : in std_ulogic_vector( 7 downto 0);
183  siSHL_Mem_Mp0_RdSts_tvalid : in std_ulogic;
184  siSHL_Mem_Mp0_RdSts_tready : out std_ulogic;
185  ------ Stream Read Data ------------
186  siSHL_Mem_Mp0_Read_tdata : in std_ulogic_vector(511 downto 0);
187  siSHL_Mem_Mp0_Read_tkeep : in std_ulogic_vector( 63 downto 0);
188  siSHL_Mem_Mp0_Read_tlast : in std_ulogic;
189  siSHL_Mem_Mp0_Read_tvalid : in std_ulogic;
190  siSHL_Mem_Mp0_Read_tready : out std_ulogic;
191  ------ Stream Write Command --------
192  soSHL_Mem_Mp0_WrCmd_tdata : out std_ulogic_vector( 79 downto 0);
193  soSHL_Mem_Mp0_WrCmd_tvalid : out std_ulogic;
194  soSHL_Mem_Mp0_WrCmd_tready : in std_ulogic;
195  ------ Stream Write Status ---------
196  siSHL_Mem_Mp0_WrSts_tdata : in std_ulogic_vector( 7 downto 0);
197  siSHL_Mem_Mp0_WrSts_tvalid : in std_ulogic;
198  siSHL_Mem_Mp0_WrSts_tready : out std_ulogic;
199  ------ Stream Write Data -----------
200  soSHL_Mem_Mp0_Write_tdata : out std_ulogic_vector(511 downto 0);
201  soSHL_Mem_Mp0_Write_tkeep : out std_ulogic_vector( 63 downto 0);
202  soSHL_Mem_Mp0_Write_tlast : out std_ulogic;
203  soSHL_Mem_Mp0_Write_tvalid : out std_ulogic;
204  soSHL_Mem_Mp0_Write_tready : in std_ulogic;
205 
206  --------------------------------------------------------
207  -- SHELL / Mem / Mp1 Interface
208  --------------------------------------------------------
209  ---- Memory Port #1 / S2MM-AXIS ------------------
210  ------ Stream Read Command ---------
211  soSHL_Mem_Mp1_RdCmd_tdata : out std_ulogic_vector( 79 downto 0);
212  soSHL_Mem_Mp1_RdCmd_tvalid : out std_ulogic;
213  soSHL_Mem_Mp1_RdCmd_tready : in std_ulogic;
214  ------ Stream Read Status ----------
215  siSHL_Mem_Mp1_RdSts_tdata : in std_ulogic_vector( 7 downto 0);
216  siSHL_Mem_Mp1_RdSts_tvalid : in std_ulogic;
217  siSHL_Mem_Mp1_RdSts_tready : out std_ulogic;
218  ------ Stream Data Input Channel ---
219  siSHL_Mem_Mp1_Read_tdata : in std_ulogic_vector(511 downto 0);
220  siSHL_Mem_Mp1_Read_tkeep : in std_ulogic_vector( 63 downto 0);
221  siSHL_Mem_Mp1_Read_tlast : in std_ulogic;
222  siSHL_Mem_Mp1_Read_tvalid : in std_ulogic;
223  siSHL_Mem_Mp1_Read_tready : out std_ulogic;
224  ------ Stream Write Command --------
225  soSHL_Mem_Mp1_WrCmd_tdata : out std_ulogic_vector( 79 downto 0);
226  soSHL_Mem_Mp1_WrCmd_tvalid : out std_ulogic;
227  soSHL_Mem_Mp1_WrCmd_tready : in std_ulogic;
228  ------ Stream Write Status ---------
229  siSHL_Mem_Mp1_WrSts_tvalid : in std_ulogic;
230  siSHL_Mem_Mp1_WrSts_tdata : in std_ulogic_vector( 7 downto 0);
231  siSHL_Mem_Mp1_WrSts_tready : out std_ulogic;
232  ------ Stream Data Output Channel --
233  soSHL_Mem_Mp1_Write_tdata : out std_ulogic_vector(511 downto 0);
234  soSHL_Mem_Mp1_Write_tkeep : out std_ulogic_vector( 63 downto 0);
235  soSHL_Mem_Mp1_Write_tlast : out std_ulogic;
236  soSHL_Mem_Mp1_Write_tvalid : out std_ulogic;
237  soSHL_Mem_Mp1_Write_tready : in std_ulogic;
238 
239  --------------------------------------------------------
240  -- SHELL / Mmio / AppFlash Interface
241  --------------------------------------------------------
242  ---- [PHY_RESET] -------------------
243  piSHL_Mmio_Ly7Rst : in std_ulogic;
244  ---- [PHY_ENABLE] ------------------
245  piSHL_Mmio_Ly7En : in std_ulogic;
246  ---- [DIAG_CTRL_1] -----------------
247  piSHL_Mmio_Mc1_MemTestCtrl : in std_ulogic_vector( 1 downto 0);
248  ---- [DIAG_STAT_1] -----------------
249  poSHL_Mmio_Mc1_MemTestStat : out std_ulogic_vector( 1 downto 0);
250  ---- [DIAG_CTRL_2] -----------------
251  piSHL_Mmio_UdpEchoCtrl : in std_ulogic_vector( 1 downto 0);
252  piSHL_Mmio_UdpPostDgmEn : in std_ulogic;
253  piSHL_Mmio_UdpCaptDgmEn : in std_ulogic;
254  piSHL_Mmio_TcpEchoCtrl : in std_ulogic_vector( 1 downto 0);
255  piSHL_Mmio_TcpPostSegEn : in std_ulogic;
256  piSHL_Mmio_TcpCaptSegEn : in std_ulogic;
257  ---- [APP_RDROL] -------------------
258  poSHL_Mmio_RdReg : out std_ulogic_vector( 15 downto 0);
259  --- [APP_WRROL] --------------------
260  piSHL_Mmio_WrReg : in std_ulogic_vector( 15 downto 0);
261 
262  --------------------------------------------------------
263  -- TOP : Secondary Clock (Asynchronous)
264  --------------------------------------------------------
265  piTOP_250_00Clk : in std_ulogic; -- Freerunning
266 
267  poVoid : out std_ulogic
268 
269  );
270 
271 end Role_Kale;
272 
273 
Role_Kale
Definition: Role.vhdl:74
Role_Kale.soSHL_Mem_Mp0_RdCmd_tvalid
out soSHL_Mem_Mp0_RdCmd_tvalidstd_ulogic
Definition: Role.vhdl:179
Role_Kale.siSHL_Nts_Tcp_Data_tkeep
in siSHL_Nts_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:124
Role_Kale.siSHL_Nts_Tcp_Notif_tvalid
in siSHL_Nts_Tcp_Notif_tvalidstd_ulogic
Definition: Role.vhdl:136
Role_Kale.siSHL_Mem_Mp0_Read_tlast
in siSHL_Mem_Mp0_Read_tlaststd_ulogic
Definition: Role.vhdl:188
Role_Kale.soSHL_Nts_Tcp_Data_tvalid
out soSHL_Nts_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:107
Role_Kale.siSHL_Nts_Tcp_OpnRep_tdata
in siSHL_Nts_Tcp_OpnRep_tdatastd_ulogic_vector(23 downto 0)
Definition: Role.vhdl:152
Role_Kale.soSHL_Mem_Mp1_Write_tready
in soSHL_Mem_Mp1_Write_treadystd_ulogic
Definition: Role.vhdl:237
Role_Kale.siSHL_Mem_Mp0_WrSts_tvalid
in siSHL_Mem_Mp0_WrSts_tvalidstd_ulogic
Definition: Role.vhdl:197
Role_Kale.poSHL_Mmio_RdReg
out poSHL_Mmio_RdRegstd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:258
Role_Kale.piSHL_156_25Rst
in piSHL_156_25Rststd_ulogic
Definition: Role.vhdl:81
Role_Kale.siSHL_Nts_Tcp_DSts_tready
out siSHL_Nts_Tcp_DSts_treadystd_ulogic
Definition: Role.vhdl:116
Role_Kale.siSHL_Nts_Udp_Data_tlast
in siSHL_Nts_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:89
Role_Kale.siSHL_Mem_Mp0_Read_tkeep
in siSHL_Mem_Mp0_Read_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:187
Role_Kale.soSHL_Mem_Mp1_WrCmd_tvalid
out soSHL_Mem_Mp1_WrCmd_tvalidstd_ulogic
Definition: Role.vhdl:226
Role_Kale.piSHL_Mmio_UdpPostDgmEn
in piSHL_Mmio_UdpPostDgmEnstd_ulogic
Definition: Role.vhdl:252
Role_Kale.soSHL_Nts_Tcp_DReq_tvalid
out soSHL_Nts_Tcp_DReq_tvalidstd_ulogic
Definition: Role.vhdl:140
Role_Kale.soSHL_Nts_Tcp_OpnReq_tready
in soSHL_Nts_Tcp_OpnReq_treadystd_ulogic
Definition: Role.vhdl:150
Role_Kale.soSHL_Mem_Mp1_Write_tlast
out soSHL_Mem_Mp1_Write_tlaststd_ulogic
Definition: Role.vhdl:235
Role_Kale.siSHL_Mem_Mp0_RdSts_tvalid
in siSHL_Mem_Mp0_RdSts_tvalidstd_ulogic
Definition: Role.vhdl:183
Role_Kale.piSHL_Mmio_TcpCaptSegEn
in piSHL_Mmio_TcpCaptSegEnstd_ulogic
Definition: Role.vhdl:256
Role_Kale.soSHL_Mem_Mp0_WrCmd_tvalid
out soSHL_Mem_Mp0_WrCmd_tvalidstd_ulogic
Definition: Role.vhdl:193
Role_Kale.piSHL_Mmio_Ly7En
in piSHL_Mmio_Ly7Enstd_ulogic
Definition: Role.vhdl:245
Role_Kale.soSHL_Nts_Tcp_Meta_tready
in soSHL_Nts_Tcp_Meta_treadystd_ulogic
Definition: Role.vhdl:112
Role_Kale.soSHL_Nts_Tcp_Data_tlast
out soSHL_Nts_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:106
Role_Kale.siSHL_Mem_Mp0_Read_tready
out siSHL_Mem_Mp0_Read_treadystd_ulogic
Definition: Role.vhdl:190
Role_Kale.soSHL_Nts_Tcp_ClsReq_tdata
out soSHL_Nts_Tcp_ClsReq_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:156
Role_Kale.siSHL_Nts_Udp_Data_tready
out siSHL_Nts_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:91
Role_Kale.siSHL_Mem_Mp0_WrSts_tdata
in siSHL_Mem_Mp0_WrSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:196
Role_Kale.soSHL_Nts_Tcp_DReq_tready
in soSHL_Nts_Tcp_DReq_treadystd_ulogic
Definition: Role.vhdl:141
Role_Kale.siSHL_Nts_Tcp_LsnAck_tvalid
in siSHL_Nts_Tcp_LsnAck_tvalidstd_ulogic
Definition: Role.vhdl:170
Role_Kale.piSHL_156_25Clk
in piSHL_156_25Clkstd_ulogic
Definition: Role.vhdl:80
Role_Kale.soSHL_Nts_Tcp_LsnReq_tvalid
out soSHL_Nts_Tcp_LsnReq_tvalidstd_ulogic
Definition: Role.vhdl:166
Role_Kale.siSHL_Nts_Tcp_Meta_tready
out siSHL_Nts_Tcp_Meta_treadystd_ulogic
Definition: Role.vhdl:133
Role_Kale.soSHL_Mem_Mp1_Write_tdata
out soSHL_Mem_Mp1_Write_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:233
Role_Kale.soSHL_Nts_Udp_Data_tvalid
out soSHL_Nts_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:96
Role_Kale.siSHL_Nts_Tcp_Data_tready
out siSHL_Nts_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:127
Role_Kale.siSHL_Nts_Udp_Data_tdata
in siSHL_Nts_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:87
Role_Kale.poSHL_Mmio_Mc1_MemTestStat
out poSHL_Mmio_Mc1_MemTestStatstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:249
Role_Kale.soSHL_Nts_Tcp_Data_tready
in soSHL_Nts_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:108
Role_Kale.piSHL_Mmio_UdpCaptDgmEn
in piSHL_Mmio_UdpCaptDgmEnstd_ulogic
Definition: Role.vhdl:253
Role_Kale.soSHL_Mem_Mp0_Write_tready
in soSHL_Mem_Mp0_Write_treadystd_ulogic
Definition: Role.vhdl:204
Role_Kale.siSHL_Nts_Tcp_Notif_tready
out siSHL_Nts_Tcp_Notif_treadystd_ulogic
Definition: Role.vhdl:137
Role_Kale.siSHL_Nts_Tcp_OpnRep_tvalid
in siSHL_Nts_Tcp_OpnRep_tvalidstd_ulogic
Definition: Role.vhdl:153
Role_Kale.soSHL_Mem_Mp0_WrCmd_tdata
out soSHL_Mem_Mp0_WrCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:192
Role_Kale.siSHL_Nts_Tcp_OpnRep_tready
out siSHL_Nts_Tcp_OpnRep_treadystd_ulogic
Definition: Role.vhdl:154
Role_Kale.siSHL_Nts_Tcp_Data_tlast
in siSHL_Nts_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:125
Role_Kale.soSHL_Nts_Udp_Data_tready
in soSHL_Nts_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:97
Role_Kale.soSHL_Mem_Mp0_Write_tdata
out soSHL_Mem_Mp0_Write_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:200
Role_Kale.siSHL_Mem_Mp1_WrSts_tready
out siSHL_Mem_Mp1_WrSts_treadystd_ulogic
Definition: Role.vhdl:231
Role_Kale.siSHL_Mem_Mp1_RdSts_tvalid
in siSHL_Mem_Mp1_RdSts_tvalidstd_ulogic
Definition: Role.vhdl:216
Role_Kale.siSHL_Mem_Mp0_RdSts_tdata
in siSHL_Mem_Mp0_RdSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:182
Role_Kale.soSHL_Mem_Mp1_WrCmd_tready
in soSHL_Mem_Mp1_WrCmd_treadystd_ulogic
Definition: Role.vhdl:227
Role_Kale.soSHL_Nts_Tcp_LsnReq_tdata
out soSHL_Nts_Tcp_LsnReq_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:165
Role_Kale.soSHL_Mem_Mp0_RdCmd_tready
in soSHL_Mem_Mp0_RdCmd_treadystd_ulogic
Definition: Role.vhdl:180
Role_Kale.siSHL_Mem_Mp1_Read_tkeep
in siSHL_Mem_Mp1_Read_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:220
Role_Kale.siSHL_Nts_Tcp_Meta_tlast
in siSHL_Nts_Tcp_Meta_tlaststd_ulogic
Definition: Role.vhdl:131
Role_Kale.soSHL_Nts_Tcp_Meta_tvalid
out soSHL_Nts_Tcp_Meta_tvalidstd_ulogic
Definition: Role.vhdl:111
Role_Kale.piSHL_Mmio_Mc1_MemTestCtrl
in piSHL_Mmio_Mc1_MemTestCtrlstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:247
Role_Kale.soSHL_Nts_Udp_Data_tlast
out soSHL_Nts_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:95
Role_Kale.soSHL_Nts_Tcp_OpnReq_tvalid
out soSHL_Nts_Tcp_OpnReq_tvalidstd_ulogic
Definition: Role.vhdl:149
Role_Kale.soSHL_Nts_Tcp_OpnReq_tdata
out soSHL_Nts_Tcp_OpnReq_tdatastd_ulogic_vector(47 downto 0)
Definition: Role.vhdl:148
Role_Kale.soSHL_Nts_Tcp_Meta_tdata
out soSHL_Nts_Tcp_Meta_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:110
Role_Kale.soSHL_Nts_Tcp_ClsReq_tvalid
out soSHL_Nts_Tcp_ClsReq_tvalidstd_ulogic
Definition: Role.vhdl:157
Role_Kale.soSHL_Mem_Mp1_Write_tkeep
out soSHL_Mem_Mp1_Write_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:234
Role_Kale.soSHL_Mem_Mp0_Write_tvalid
out soSHL_Mem_Mp0_Write_tvalidstd_ulogic
Definition: Role.vhdl:203
Role_Kale.siSHL_Nts_Tcp_Meta_tkeep
in siSHL_Nts_Tcp_Meta_tkeepstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:130
Role_Kale.siSHL_Nts_Udp_Data_tkeep
in siSHL_Nts_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:88
Role_Kale.soSHL_Nts_Tcp_LsnReq_tready
in soSHL_Nts_Tcp_LsnReq_treadystd_ulogic
Definition: Role.vhdl:167
Role_Kale.poVoid
out poVoidstd_ulogic
Definition: Role.vhdl:269
Role_Kale.siSHL_Mem_Mp1_WrSts_tvalid
in siSHL_Mem_Mp1_WrSts_tvalidstd_ulogic
Definition: Role.vhdl:229
Role_Kale.siSHL_Mem_Mp1_Read_tready
out siSHL_Mem_Mp1_Read_treadystd_ulogic
Definition: Role.vhdl:223
Role_Kale.piSHL_Mmio_TcpPostSegEn
in piSHL_Mmio_TcpPostSegEnstd_ulogic
Definition: Role.vhdl:255
Role_Kale.soSHL_Mem_Mp1_RdCmd_tvalid
out soSHL_Mem_Mp1_RdCmd_tvalidstd_ulogic
Definition: Role.vhdl:212
Role_Kale.soSHL_Mem_Mp0_WrCmd_tready
in soSHL_Mem_Mp0_WrCmd_treadystd_ulogic
Definition: Role.vhdl:194
Role_Kale.soSHL_Mem_Mp0_Write_tlast
out soSHL_Mem_Mp0_Write_tlaststd_ulogic
Definition: Role.vhdl:202
Role_Kale.siSHL_Nts_Tcp_Notif_tdata
in siSHL_Nts_Tcp_Notif_tdatastd_ulogic_vector(7+96 downto 0)
Definition: Role.vhdl:135
Role_Kale.soSHL_Nts_Tcp_Data_tdata
out soSHL_Nts_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:104
Role_Kale.siSHL_Nts_Tcp_LsnAck_tdata
in siSHL_Nts_Tcp_LsnAck_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:169
Role_Kale.soSHL_Nts_Tcp_Data_tkeep
out soSHL_Nts_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:105
Role_Kale.soSHL_Nts_Udp_Data_tdata
out soSHL_Nts_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:93
Role_Kale.siSHL_Nts_Tcp_Meta_tdata
in siSHL_Nts_Tcp_Meta_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:129
Role_Kale.piSHL_Mmio_UdpEchoCtrl
in piSHL_Mmio_UdpEchoCtrlstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:251
Role_Kale.soSHL_Mem_Mp0_RdCmd_tdata
out soSHL_Mem_Mp0_RdCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:178
Role_Kale.siSHL_Nts_Tcp_Data_tdata
in siSHL_Nts_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:123
Role_Kale.siSHL_Mem_Mp1_Read_tvalid
in siSHL_Mem_Mp1_Read_tvalidstd_ulogic
Definition: Role.vhdl:222
Role_Kale.siSHL_Mem_Mp1_RdSts_tdata
in siSHL_Mem_Mp1_RdSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:215
Role_Kale.piSHL_Mmio_TcpEchoCtrl
in piSHL_Mmio_TcpEchoCtrlstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:254
Role_Kale.siSHL_Nts_Tcp_DSts_tvalid
in siSHL_Nts_Tcp_DSts_tvalidstd_ulogic
Definition: Role.vhdl:115
Role_Kale.soSHL_Nts_Tcp_DReq_tdata
out soSHL_Nts_Tcp_DReq_tdatastd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:139
Role_Kale.siSHL_Nts_Tcp_DSts_tdata
in siSHL_Nts_Tcp_DSts_tdatastd_ulogic_vector(23 downto 0)
Definition: Role.vhdl:114
Role_Kale.soSHL_Nts_Udp_Data_tkeep
out soSHL_Nts_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:94
Role_Kale.siSHL_Nts_Tcp_LsnAck_tready
out siSHL_Nts_Tcp_LsnAck_treadystd_ulogic
Definition: Role.vhdl:171
Role_Kale.siSHL_Mem_Mp0_Read_tvalid
in siSHL_Mem_Mp0_Read_tvalidstd_ulogic
Definition: Role.vhdl:189
Role_Kale.soSHL_Mem_Mp0_Write_tkeep
out soSHL_Mem_Mp0_Write_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:201
Role_Kale.soSHL_Mem_Mp1_RdCmd_tready
in soSHL_Mem_Mp1_RdCmd_treadystd_ulogic
Definition: Role.vhdl:213
Role_Kale.siSHL_Nts_Udp_Data_tvalid
in siSHL_Nts_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:90
Role_Kale.siSHL_Mem_Mp1_RdSts_tready
out siSHL_Mem_Mp1_RdSts_treadystd_ulogic
Definition: Role.vhdl:217
Role_Kale.siSHL_Mem_Mp1_WrSts_tdata
in siSHL_Mem_Mp1_WrSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:230
Role_Kale.piTOP_250_00Clk
in piTOP_250_00Clkstd_ulogic
Definition: Role.vhdl:265
Role_Kale.siSHL_Mem_Mp1_Read_tdata
in siSHL_Mem_Mp1_Read_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:219
Role_Kale.siSHL_Nts_Tcp_Meta_tvalid
in siSHL_Nts_Tcp_Meta_tvalidstd_ulogic
Definition: Role.vhdl:132
Role_Kale.piSHL_Mmio_WrReg
in piSHL_Mmio_WrRegstd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:260
Role_Kale.siSHL_Mem_Mp1_Read_tlast
in siSHL_Mem_Mp1_Read_tlaststd_ulogic
Definition: Role.vhdl:221
Role_Kale.soSHL_Nts_Tcp_ClsReq_tready
in soSHL_Nts_Tcp_ClsReq_treadystd_ulogic
Definition: Role.vhdl:158
Role_Kale.soSHL_Mem_Mp1_WrCmd_tdata
out soSHL_Mem_Mp1_WrCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:225
Role_Kale.siSHL_Mem_Mp0_WrSts_tready
out siSHL_Mem_Mp0_WrSts_treadystd_ulogic
Definition: Role.vhdl:198
Role_Kale.siSHL_Mem_Mp0_RdSts_tready
out siSHL_Mem_Mp0_RdSts_treadystd_ulogic
Definition: Role.vhdl:184
Role_Kale.siSHL_Mem_Mp0_Read_tdata
in siSHL_Mem_Mp0_Read_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:186
Role_Kale.piSHL_Mmio_Ly7Rst
in piSHL_Mmio_Ly7Rststd_ulogic
Definition: Role.vhdl:243
Role_Kale.soSHL_Mem_Mp1_Write_tvalid
out soSHL_Mem_Mp1_Write_tvalidstd_ulogic
Definition: Role.vhdl:236
Role_Kale.soSHL_Mem_Mp1_RdCmd_tdata
out soSHL_Mem_Mp1_RdCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:211
Role_Kale.siSHL_Nts_Tcp_Data_tvalid
in siSHL_Nts_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:126