cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
Role_Kale Entity Reference

Libraries

IEEE 
UNISIM 
XIL_DEFAULTLIB 

Use Clauses

std_logic_1164 
numeric_std 
vcomponents 
all 

Generics

gVivadoVersion  integer := 2019

Ports

piSHL_156_25Clk   in   std_ulogic
piSHL_156_25Rst   in   std_ulogic
siSHL_Nts_Udp_Data_tdata   in   std_ulogic_vector ( 63 downto 0 )
siSHL_Nts_Udp_Data_tkeep   in   std_ulogic_vector ( 7 downto 0 )
siSHL_Nts_Udp_Data_tlast   in   std_ulogic
siSHL_Nts_Udp_Data_tvalid   in   std_ulogic
siSHL_Nts_Udp_Data_tready   out   std_ulogic
soSHL_Nts_Udp_Data_tdata   out   std_ulogic_vector ( 63 downto 0 )
soSHL_Nts_Udp_Data_tkeep   out   std_ulogic_vector ( 7 downto 0 )
soSHL_Nts_Udp_Data_tlast   out   std_ulogic
soSHL_Nts_Udp_Data_tvalid   out   std_ulogic
soSHL_Nts_Udp_Data_tready   in   std_ulogic
soSHL_Nts_Tcp_Data_tdata   out   std_ulogic_vector ( 63 downto 0 )
soSHL_Nts_Tcp_Data_tkeep   out   std_ulogic_vector ( 7 downto 0 )
soSHL_Nts_Tcp_Data_tlast   out   std_ulogic
soSHL_Nts_Tcp_Data_tvalid   out   std_ulogic
soSHL_Nts_Tcp_Data_tready   in   std_ulogic
soSHL_Nts_Tcp_Meta_tdata   out   std_ulogic_vector ( 15 downto 0 )
soSHL_Nts_Tcp_Meta_tvalid   out   std_ulogic
soSHL_Nts_Tcp_Meta_tready   in   std_ulogic
siSHL_Nts_Tcp_DSts_tdata   in   std_ulogic_vector ( 23 downto 0 )
siSHL_Nts_Tcp_DSts_tvalid   in   std_ulogic
siSHL_Nts_Tcp_DSts_tready   out   std_ulogic
siSHL_Nts_Tcp_Data_tdata   in   std_ulogic_vector ( 63 downto 0 )
siSHL_Nts_Tcp_Data_tkeep   in   std_ulogic_vector ( 7 downto 0 )
siSHL_Nts_Tcp_Data_tlast   in   std_ulogic
siSHL_Nts_Tcp_Data_tvalid   in   std_ulogic
siSHL_Nts_Tcp_Data_tready   out   std_ulogic
siSHL_Nts_Tcp_Meta_tdata   in   std_ulogic_vector ( 15 downto 0 )
siSHL_Nts_Tcp_Meta_tkeep   in   std_ulogic_vector ( 1 downto 0 )
siSHL_Nts_Tcp_Meta_tlast   in   std_ulogic
siSHL_Nts_Tcp_Meta_tvalid   in   std_ulogic
siSHL_Nts_Tcp_Meta_tready   out   std_ulogic
siSHL_Nts_Tcp_Notif_tdata   in   std_ulogic_vector ( 7 + 96 downto 0 )
siSHL_Nts_Tcp_Notif_tvalid   in   std_ulogic
siSHL_Nts_Tcp_Notif_tready   out   std_ulogic
soSHL_Nts_Tcp_DReq_tdata   out   std_ulogic_vector ( 31 downto 0 )
soSHL_Nts_Tcp_DReq_tvalid   out   std_ulogic
soSHL_Nts_Tcp_DReq_tready   in   std_ulogic
soSHL_Nts_Tcp_OpnReq_tdata   out   std_ulogic_vector ( 47 downto 0 )
soSHL_Nts_Tcp_OpnReq_tvalid   out   std_ulogic
soSHL_Nts_Tcp_OpnReq_tready   in   std_ulogic
siSHL_Nts_Tcp_OpnRep_tdata   in   std_ulogic_vector ( 23 downto 0 )
siSHL_Nts_Tcp_OpnRep_tvalid   in   std_ulogic
siSHL_Nts_Tcp_OpnRep_tready   out   std_ulogic
soSHL_Nts_Tcp_ClsReq_tdata   out   std_ulogic_vector ( 15 downto 0 )
soSHL_Nts_Tcp_ClsReq_tvalid   out   std_ulogic
soSHL_Nts_Tcp_ClsReq_tready   in   std_ulogic
soSHL_Nts_Tcp_LsnReq_tdata   out   std_ulogic_vector ( 15 downto 0 )
soSHL_Nts_Tcp_LsnReq_tvalid   out   std_ulogic
soSHL_Nts_Tcp_LsnReq_tready   in   std_ulogic
siSHL_Nts_Tcp_LsnAck_tdata   in   std_ulogic_vector ( 7 downto 0 )
siSHL_Nts_Tcp_LsnAck_tvalid   in   std_ulogic
siSHL_Nts_Tcp_LsnAck_tready   out   std_ulogic
soSHL_Mem_Mp0_RdCmd_tdata   out   std_ulogic_vector ( 79 downto 0 )
soSHL_Mem_Mp0_RdCmd_tvalid   out   std_ulogic
soSHL_Mem_Mp0_RdCmd_tready   in   std_ulogic
siSHL_Mem_Mp0_RdSts_tdata   in   std_ulogic_vector ( 7 downto 0 )
siSHL_Mem_Mp0_RdSts_tvalid   in   std_ulogic
siSHL_Mem_Mp0_RdSts_tready   out   std_ulogic
siSHL_Mem_Mp0_Read_tdata   in   std_ulogic_vector ( 511 downto 0 )
siSHL_Mem_Mp0_Read_tkeep   in   std_ulogic_vector ( 63 downto 0 )
siSHL_Mem_Mp0_Read_tlast   in   std_ulogic
siSHL_Mem_Mp0_Read_tvalid   in   std_ulogic
siSHL_Mem_Mp0_Read_tready   out   std_ulogic
soSHL_Mem_Mp0_WrCmd_tdata   out   std_ulogic_vector ( 79 downto 0 )
soSHL_Mem_Mp0_WrCmd_tvalid   out   std_ulogic
soSHL_Mem_Mp0_WrCmd_tready   in   std_ulogic
siSHL_Mem_Mp0_WrSts_tdata   in   std_ulogic_vector ( 7 downto 0 )
siSHL_Mem_Mp0_WrSts_tvalid   in   std_ulogic
siSHL_Mem_Mp0_WrSts_tready   out   std_ulogic
soSHL_Mem_Mp0_Write_tdata   out   std_ulogic_vector ( 511 downto 0 )
soSHL_Mem_Mp0_Write_tkeep   out   std_ulogic_vector ( 63 downto 0 )
soSHL_Mem_Mp0_Write_tlast   out   std_ulogic
soSHL_Mem_Mp0_Write_tvalid   out   std_ulogic
soSHL_Mem_Mp0_Write_tready   in   std_ulogic
soSHL_Mem_Mp1_RdCmd_tdata   out   std_ulogic_vector ( 79 downto 0 )
soSHL_Mem_Mp1_RdCmd_tvalid   out   std_ulogic
soSHL_Mem_Mp1_RdCmd_tready   in   std_ulogic
siSHL_Mem_Mp1_RdSts_tdata   in   std_ulogic_vector ( 7 downto 0 )
siSHL_Mem_Mp1_RdSts_tvalid   in   std_ulogic
siSHL_Mem_Mp1_RdSts_tready   out   std_ulogic
siSHL_Mem_Mp1_Read_tdata   in   std_ulogic_vector ( 511 downto 0 )
siSHL_Mem_Mp1_Read_tkeep   in   std_ulogic_vector ( 63 downto 0 )
siSHL_Mem_Mp1_Read_tlast   in   std_ulogic
siSHL_Mem_Mp1_Read_tvalid   in   std_ulogic
siSHL_Mem_Mp1_Read_tready   out   std_ulogic
soSHL_Mem_Mp1_WrCmd_tdata   out   std_ulogic_vector ( 79 downto 0 )
soSHL_Mem_Mp1_WrCmd_tvalid   out   std_ulogic
soSHL_Mem_Mp1_WrCmd_tready   in   std_ulogic
siSHL_Mem_Mp1_WrSts_tvalid   in   std_ulogic
siSHL_Mem_Mp1_WrSts_tdata   in   std_ulogic_vector ( 7 downto 0 )
siSHL_Mem_Mp1_WrSts_tready   out   std_ulogic
soSHL_Mem_Mp1_Write_tdata   out   std_ulogic_vector ( 511 downto 0 )
soSHL_Mem_Mp1_Write_tkeep   out   std_ulogic_vector ( 63 downto 0 )
soSHL_Mem_Mp1_Write_tlast   out   std_ulogic
soSHL_Mem_Mp1_Write_tvalid   out   std_ulogic
soSHL_Mem_Mp1_Write_tready   in   std_ulogic
piSHL_Mmio_Ly7Rst   in   std_ulogic
piSHL_Mmio_Ly7En   in   std_ulogic
piSHL_Mmio_Mc1_MemTestCtrl   in   std_ulogic_vector ( 1 downto 0 )
poSHL_Mmio_Mc1_MemTestStat   out   std_ulogic_vector ( 1 downto 0 )
piSHL_Mmio_UdpEchoCtrl   in   std_ulogic_vector ( 1 downto 0 )
piSHL_Mmio_UdpPostDgmEn   in   std_ulogic
piSHL_Mmio_UdpCaptDgmEn   in   std_ulogic
piSHL_Mmio_TcpEchoCtrl   in   std_ulogic_vector ( 1 downto 0 )
piSHL_Mmio_TcpPostSegEn   in   std_ulogic
piSHL_Mmio_TcpCaptSegEn   in   std_ulogic
poSHL_Mmio_RdReg   out   std_ulogic_vector ( 15 downto 0 )
piSHL_Mmio_WrReg   in   std_ulogic_vector ( 15 downto 0 )
piTOP_250_00Clk   in   std_ulogic
poVoid   out   std_ulogic
siSHL_Nts_Udp_Meta_tdata   in   std_ulogic_vector ( 95 downto 0 )
siSHL_Nts_Udp_Meta_tvalid   in   std_ulogic
siSHL_Nts_Udp_Meta_tready   out   std_ulogic
siSHL_Nts_Udp_DLen_tdata   in   std_ulogic_vector ( 15 downto 0 )
siSHL_Nts_Udp_DLen_tvalid   in   std_ulogic
siSHL_Nts_Udp_DLen_tready   out   std_ulogic
soSHL_Nts_Udp_Meta_tdata   out   std_ulogic_vector ( 95 downto 0 )
soSHL_Nts_Udp_Meta_tvalid   out   std_ulogic
soSHL_Nts_Udp_Meta_tready   in   std_ulogic
soSHL_Nts_Udp_DLen_tdata   out   std_ulogic_vector ( 15 downto 0 )
soSHL_Nts_Udp_DLen_tvalid   out   std_ulogic
soSHL_Nts_Udp_DLen_tready   in   std_ulogic
soSHL_Nts_Udp_LsnReq_tdata   out   std_ulogic_vector ( 15 downto 0 )
soSHL_Nts_Udp_LsnReq_tvalid   out   std_ulogic
soSHL_Nts_Udp_LsnReq_tready   in   std_ulogic
siSHL_Nts_Udp_LsnRep_tdata   in   std_ulogic_vector ( 7 downto 0 )
siSHL_Nts_Udp_LsnRep_tvalid   in   std_ulogic
siSHL_Nts_Udp_LsnRep_tready   out   std_ulogic
soSHL_Nts_Udp_ClsReq_tdata   out   std_ulogic_vector ( 15 downto 0 )
soSHL_Nts_Udp_ClsReq_tvalid   out   std_ulogic
soSHL_Nts_Udp_ClsReq_tready   in   std_ulogic
siSHL_Nts_Udp_ClsRep_tdata   in   std_ulogic_vector ( 7 downto 0 )
siSHL_Nts_Udp_ClsRep_tvalid   in   std_ulogic
siSHL_Nts_Udp_ClsRep_tready   out   std_ulogic
soSHL_Nts_Tcp_SndReq_tdata   out   std_ulogic_vector ( 31 downto 0 )
soSHL_Nts_Tcp_SndReq_tvalid   out   std_ulogic
soSHL_Nts_Tcp_SndReq_tready   in   std_ulogic
siSHL_Nts_Tcp_SndRep_tdata   in   std_ulogic_vector ( 55 downto 0 )
siSHL_Nts_Tcp_SndRep_tvalid   in   std_ulogic
siSHL_Nts_Tcp_SndRep_tready   out   std_ulogic
siSHL_Nts_Tcp_LsnRep_tdata   in   std_ulogic_vector ( 7 downto 0 )
siSHL_Nts_Tcp_LsnRep_tvalid   in   std_ulogic
siSHL_Nts_Tcp_LsnRep_tready   out   std_ulogic
moSHL_Mem_Mp1_AWID   out   std_ulogic_vector ( 7 downto 0 )
moSHL_Mem_Mp1_AWADDR   out   std_ulogic_vector ( 32 downto 0 )
moSHL_Mem_Mp1_AWLEN   out   std_ulogic_vector ( 7 downto 0 )
moSHL_Mem_Mp1_AWSIZE   out   std_ulogic_vector ( 2 downto 0 )
moSHL_Mem_Mp1_AWBURST   out   std_ulogic_vector ( 1 downto 0 )
moSHL_Mem_Mp1_AWVALID   out   std_ulogic
moSHL_Mem_Mp1_AWREADY   in   std_ulogic
moSHL_Mem_Mp1_WDATA   out   std_ulogic_vector ( 511 downto 0 )
moSHL_Mem_Mp1_WSTRB   out   std_ulogic_vector ( 63 downto 0 )
moSHL_Mem_Mp1_WLAST   out   std_ulogic
moSHL_Mem_Mp1_WVALID   out   std_ulogic
moSHL_Mem_Mp1_WREADY   in   std_ulogic
moSHL_Mem_Mp1_BID   in   std_ulogic_vector ( 7 downto 0 )
moSHL_Mem_Mp1_BRESP   in   std_ulogic_vector ( 1 downto 0 )
moSHL_Mem_Mp1_BVALID   in   std_ulogic
moSHL_Mem_Mp1_BREADY   out   std_ulogic
moSHL_Mem_Mp1_ARID   out   std_ulogic_vector ( 7 downto 0 )
moSHL_Mem_Mp1_ARADDR   out   std_ulogic_vector ( 32 downto 0 )
moSHL_Mem_Mp1_ARLEN   out   std_ulogic_vector ( 7 downto 0 )
moSHL_Mem_Mp1_ARSIZE   out   std_ulogic_vector ( 2 downto 0 )
moSHL_Mem_Mp1_ARBURST   out   std_ulogic_vector ( 1 downto 0 )
moSHL_Mem_Mp1_ARVALID   out   std_ulogic
moSHL_Mem_Mp1_ARREADY   in   std_ulogic
moSHL_Mem_Mp1_RID   in   std_ulogic_vector ( 7 downto 0 )
moSHL_Mem_Mp1_RDATA   in   std_ulogic_vector ( 511 downto 0 )
moSHL_Mem_Mp1_RRESP   in   std_ulogic_vector ( 1 downto 0 )
moSHL_Mem_Mp1_RLAST   in   std_ulogic
moSHL_Mem_Mp1_RVALID   in   std_ulogic
moSHL_Mem_Mp1_RREADY   out   std_ulogic

Detailed Description

Definition at line 74 of file Role.vhdl.

Member Data Documentation

◆ all

all
use clause

Definition at line 45 of file Role.vhdl.

◆ gVivadoVersion

gVivadoVersion integer := 2019
Generic

Definition at line 54 of file Role.vhdl.

◆ IEEE

IEEE
Library

Definition at line 59 of file Role.vhdl.

◆ moSHL_Mem_Mp1_ARADDR

moSHL_Mem_Mp1_ARADDR out std_ulogic_vector ( 32 downto 0 )
Port

Definition at line 234 of file Role.vhdl.

◆ moSHL_Mem_Mp1_ARBURST

moSHL_Mem_Mp1_ARBURST out std_ulogic_vector ( 1 downto 0 )
Port

Definition at line 237 of file Role.vhdl.

◆ moSHL_Mem_Mp1_ARID

moSHL_Mem_Mp1_ARID out std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 233 of file Role.vhdl.

◆ moSHL_Mem_Mp1_ARLEN

moSHL_Mem_Mp1_ARLEN out std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 235 of file Role.vhdl.

◆ moSHL_Mem_Mp1_ARREADY

moSHL_Mem_Mp1_ARREADY in std_ulogic
Port

Definition at line 239 of file Role.vhdl.

◆ moSHL_Mem_Mp1_ARSIZE

moSHL_Mem_Mp1_ARSIZE out std_ulogic_vector ( 2 downto 0 )
Port

Definition at line 236 of file Role.vhdl.

◆ moSHL_Mem_Mp1_ARVALID

moSHL_Mem_Mp1_ARVALID out std_ulogic
Port

Definition at line 238 of file Role.vhdl.

◆ moSHL_Mem_Mp1_AWADDR

moSHL_Mem_Mp1_AWADDR out std_ulogic_vector ( 32 downto 0 )
Port

Definition at line 215 of file Role.vhdl.

◆ moSHL_Mem_Mp1_AWBURST

moSHL_Mem_Mp1_AWBURST out std_ulogic_vector ( 1 downto 0 )
Port

Definition at line 218 of file Role.vhdl.

◆ moSHL_Mem_Mp1_AWID

moSHL_Mem_Mp1_AWID out std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 214 of file Role.vhdl.

◆ moSHL_Mem_Mp1_AWLEN

moSHL_Mem_Mp1_AWLEN out std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 216 of file Role.vhdl.

◆ moSHL_Mem_Mp1_AWREADY

moSHL_Mem_Mp1_AWREADY in std_ulogic
Port

Definition at line 220 of file Role.vhdl.

◆ moSHL_Mem_Mp1_AWSIZE

moSHL_Mem_Mp1_AWSIZE out std_ulogic_vector ( 2 downto 0 )
Port

Definition at line 217 of file Role.vhdl.

◆ moSHL_Mem_Mp1_AWVALID

moSHL_Mem_Mp1_AWVALID out std_ulogic
Port

Definition at line 219 of file Role.vhdl.

◆ moSHL_Mem_Mp1_BID

moSHL_Mem_Mp1_BID in std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 228 of file Role.vhdl.

◆ moSHL_Mem_Mp1_BREADY

moSHL_Mem_Mp1_BREADY out std_ulogic
Port

Definition at line 231 of file Role.vhdl.

◆ moSHL_Mem_Mp1_BRESP

moSHL_Mem_Mp1_BRESP in std_ulogic_vector ( 1 downto 0 )
Port

Definition at line 229 of file Role.vhdl.

◆ moSHL_Mem_Mp1_BVALID

moSHL_Mem_Mp1_BVALID in std_ulogic
Port

Definition at line 230 of file Role.vhdl.

◆ moSHL_Mem_Mp1_RDATA

moSHL_Mem_Mp1_RDATA in std_ulogic_vector ( 511 downto 0 )
Port

Definition at line 242 of file Role.vhdl.

◆ moSHL_Mem_Mp1_RID

moSHL_Mem_Mp1_RID in std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 241 of file Role.vhdl.

◆ moSHL_Mem_Mp1_RLAST

moSHL_Mem_Mp1_RLAST in std_ulogic
Port

Definition at line 244 of file Role.vhdl.

◆ moSHL_Mem_Mp1_RREADY

moSHL_Mem_Mp1_RREADY out std_ulogic
Port

Definition at line 246 of file Role.vhdl.

◆ moSHL_Mem_Mp1_RRESP

moSHL_Mem_Mp1_RRESP in std_ulogic_vector ( 1 downto 0 )
Port

Definition at line 243 of file Role.vhdl.

◆ moSHL_Mem_Mp1_RVALID

moSHL_Mem_Mp1_RVALID in std_ulogic
Port

Definition at line 245 of file Role.vhdl.

◆ moSHL_Mem_Mp1_WDATA

moSHL_Mem_Mp1_WDATA out std_ulogic_vector ( 511 downto 0 )
Port

Definition at line 222 of file Role.vhdl.

◆ moSHL_Mem_Mp1_WLAST

moSHL_Mem_Mp1_WLAST out std_ulogic
Port

Definition at line 224 of file Role.vhdl.

◆ moSHL_Mem_Mp1_WREADY

moSHL_Mem_Mp1_WREADY in std_ulogic
Port

Definition at line 226 of file Role.vhdl.

◆ moSHL_Mem_Mp1_WSTRB

moSHL_Mem_Mp1_WSTRB out std_ulogic_vector ( 63 downto 0 )
Port

Definition at line 223 of file Role.vhdl.

◆ moSHL_Mem_Mp1_WVALID

moSHL_Mem_Mp1_WVALID out std_ulogic
Port

Definition at line 225 of file Role.vhdl.

◆ numeric_std

numeric_std
use clause

Definition at line 61 of file Role.vhdl.

◆ piSHL_156_25Clk

piSHL_156_25Clk in std_ulogic
Port

Definition at line 80 of file Role.vhdl.

◆ piSHL_156_25Rst

piSHL_156_25Rst in std_ulogic
Port

Definition at line 81 of file Role.vhdl.

◆ piSHL_Mmio_Ly7En

piSHL_Mmio_Ly7En in std_ulogic
Port

Definition at line 245 of file Role.vhdl.

◆ piSHL_Mmio_Ly7Rst

piSHL_Mmio_Ly7Rst in std_ulogic
Port

Definition at line 243 of file Role.vhdl.

◆ piSHL_Mmio_Mc1_MemTestCtrl

piSHL_Mmio_Mc1_MemTestCtrl in std_ulogic_vector ( 1 downto 0 )
Port

Definition at line 247 of file Role.vhdl.

◆ piSHL_Mmio_TcpCaptSegEn

piSHL_Mmio_TcpCaptSegEn in std_ulogic
Port

Definition at line 256 of file Role.vhdl.

◆ piSHL_Mmio_TcpEchoCtrl

piSHL_Mmio_TcpEchoCtrl in std_ulogic_vector ( 1 downto 0 )
Port

Definition at line 254 of file Role.vhdl.

◆ piSHL_Mmio_TcpPostSegEn

piSHL_Mmio_TcpPostSegEn in std_ulogic
Port

Definition at line 255 of file Role.vhdl.

◆ piSHL_Mmio_UdpCaptDgmEn

piSHL_Mmio_UdpCaptDgmEn in std_ulogic
Port

Definition at line 253 of file Role.vhdl.

◆ piSHL_Mmio_UdpEchoCtrl

piSHL_Mmio_UdpEchoCtrl in std_ulogic_vector ( 1 downto 0 )
Port

Definition at line 251 of file Role.vhdl.

◆ piSHL_Mmio_UdpPostDgmEn

piSHL_Mmio_UdpPostDgmEn in std_ulogic
Port

Definition at line 252 of file Role.vhdl.

◆ piSHL_Mmio_WrReg

piSHL_Mmio_WrReg in std_ulogic_vector ( 15 downto 0 )
Port

Definition at line 260 of file Role.vhdl.

◆ piTOP_250_00Clk

piTOP_250_00Clk in std_ulogic
Port

Definition at line 265 of file Role.vhdl.

◆ poSHL_Mmio_Mc1_MemTestStat

poSHL_Mmio_Mc1_MemTestStat out std_ulogic_vector ( 1 downto 0 )
Port

Definition at line 249 of file Role.vhdl.

◆ poSHL_Mmio_RdReg

poSHL_Mmio_RdReg out std_ulogic_vector ( 15 downto 0 )
Port

Definition at line 258 of file Role.vhdl.

◆ poVoid

poVoid out std_ulogic
Port

Definition at line 269 of file Role.vhdl.

◆ siSHL_Mem_Mp0_RdSts_tdata

siSHL_Mem_Mp0_RdSts_tdata in std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 182 of file Role.vhdl.

◆ siSHL_Mem_Mp0_RdSts_tready

siSHL_Mem_Mp0_RdSts_tready out std_ulogic
Port

Definition at line 184 of file Role.vhdl.

◆ siSHL_Mem_Mp0_RdSts_tvalid

siSHL_Mem_Mp0_RdSts_tvalid in std_ulogic
Port

Definition at line 183 of file Role.vhdl.

◆ siSHL_Mem_Mp0_Read_tdata

siSHL_Mem_Mp0_Read_tdata in std_ulogic_vector ( 511 downto 0 )
Port

Definition at line 186 of file Role.vhdl.

◆ siSHL_Mem_Mp0_Read_tkeep

siSHL_Mem_Mp0_Read_tkeep in std_ulogic_vector ( 63 downto 0 )
Port

Definition at line 187 of file Role.vhdl.

◆ siSHL_Mem_Mp0_Read_tlast

siSHL_Mem_Mp0_Read_tlast in std_ulogic
Port

Definition at line 188 of file Role.vhdl.

◆ siSHL_Mem_Mp0_Read_tready

siSHL_Mem_Mp0_Read_tready out std_ulogic
Port

Definition at line 190 of file Role.vhdl.

◆ siSHL_Mem_Mp0_Read_tvalid

siSHL_Mem_Mp0_Read_tvalid in std_ulogic
Port

Definition at line 189 of file Role.vhdl.

◆ siSHL_Mem_Mp0_WrSts_tdata

siSHL_Mem_Mp0_WrSts_tdata in std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 196 of file Role.vhdl.

◆ siSHL_Mem_Mp0_WrSts_tready

siSHL_Mem_Mp0_WrSts_tready out std_ulogic
Port

Definition at line 198 of file Role.vhdl.

◆ siSHL_Mem_Mp0_WrSts_tvalid

siSHL_Mem_Mp0_WrSts_tvalid in std_ulogic
Port

Definition at line 197 of file Role.vhdl.

◆ siSHL_Mem_Mp1_RdSts_tdata

siSHL_Mem_Mp1_RdSts_tdata in std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 215 of file Role.vhdl.

◆ siSHL_Mem_Mp1_RdSts_tready

siSHL_Mem_Mp1_RdSts_tready out std_ulogic
Port

Definition at line 217 of file Role.vhdl.

◆ siSHL_Mem_Mp1_RdSts_tvalid

siSHL_Mem_Mp1_RdSts_tvalid in std_ulogic
Port

Definition at line 216 of file Role.vhdl.

◆ siSHL_Mem_Mp1_Read_tdata

siSHL_Mem_Mp1_Read_tdata in std_ulogic_vector ( 511 downto 0 )
Port

Definition at line 219 of file Role.vhdl.

◆ siSHL_Mem_Mp1_Read_tkeep

siSHL_Mem_Mp1_Read_tkeep in std_ulogic_vector ( 63 downto 0 )
Port

Definition at line 220 of file Role.vhdl.

◆ siSHL_Mem_Mp1_Read_tlast

siSHL_Mem_Mp1_Read_tlast in std_ulogic
Port

Definition at line 221 of file Role.vhdl.

◆ siSHL_Mem_Mp1_Read_tready

siSHL_Mem_Mp1_Read_tready out std_ulogic
Port

Definition at line 223 of file Role.vhdl.

◆ siSHL_Mem_Mp1_Read_tvalid

siSHL_Mem_Mp1_Read_tvalid in std_ulogic
Port

Definition at line 222 of file Role.vhdl.

◆ siSHL_Mem_Mp1_WrSts_tdata

siSHL_Mem_Mp1_WrSts_tdata in std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 230 of file Role.vhdl.

◆ siSHL_Mem_Mp1_WrSts_tready

siSHL_Mem_Mp1_WrSts_tready out std_ulogic
Port

Definition at line 231 of file Role.vhdl.

◆ siSHL_Mem_Mp1_WrSts_tvalid

siSHL_Mem_Mp1_WrSts_tvalid in std_ulogic
Port

Definition at line 229 of file Role.vhdl.

◆ siSHL_Nts_Tcp_Data_tdata

siSHL_Nts_Tcp_Data_tdata in std_ulogic_vector ( 63 downto 0 )
Port

Definition at line 123 of file Role.vhdl.

◆ siSHL_Nts_Tcp_Data_tkeep

siSHL_Nts_Tcp_Data_tkeep in std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 124 of file Role.vhdl.

◆ siSHL_Nts_Tcp_Data_tlast

siSHL_Nts_Tcp_Data_tlast in std_ulogic
Port

Definition at line 125 of file Role.vhdl.

◆ siSHL_Nts_Tcp_Data_tready

siSHL_Nts_Tcp_Data_tready out std_ulogic
Port

Definition at line 127 of file Role.vhdl.

◆ siSHL_Nts_Tcp_Data_tvalid

siSHL_Nts_Tcp_Data_tvalid in std_ulogic
Port

Definition at line 126 of file Role.vhdl.

◆ siSHL_Nts_Tcp_DSts_tdata

siSHL_Nts_Tcp_DSts_tdata in std_ulogic_vector ( 23 downto 0 )
Port

Definition at line 114 of file Role.vhdl.

◆ siSHL_Nts_Tcp_DSts_tready

siSHL_Nts_Tcp_DSts_tready out std_ulogic
Port

Definition at line 116 of file Role.vhdl.

◆ siSHL_Nts_Tcp_DSts_tvalid

siSHL_Nts_Tcp_DSts_tvalid in std_ulogic
Port

Definition at line 115 of file Role.vhdl.

◆ siSHL_Nts_Tcp_LsnAck_tdata

siSHL_Nts_Tcp_LsnAck_tdata in std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 169 of file Role.vhdl.

◆ siSHL_Nts_Tcp_LsnAck_tready

siSHL_Nts_Tcp_LsnAck_tready out std_ulogic
Port

Definition at line 171 of file Role.vhdl.

◆ siSHL_Nts_Tcp_LsnAck_tvalid

siSHL_Nts_Tcp_LsnAck_tvalid in std_ulogic
Port

Definition at line 170 of file Role.vhdl.

◆ siSHL_Nts_Tcp_LsnRep_tdata

siSHL_Nts_Tcp_LsnRep_tdata in std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 175 of file Role.vhdl.

◆ siSHL_Nts_Tcp_LsnRep_tready

siSHL_Nts_Tcp_LsnRep_tready out std_ulogic
Port

Definition at line 177 of file Role.vhdl.

◆ siSHL_Nts_Tcp_LsnRep_tvalid

siSHL_Nts_Tcp_LsnRep_tvalid in std_ulogic
Port

Definition at line 176 of file Role.vhdl.

◆ siSHL_Nts_Tcp_Meta_tdata

siSHL_Nts_Tcp_Meta_tdata in std_ulogic_vector ( 15 downto 0 )
Port

Definition at line 129 of file Role.vhdl.

◆ siSHL_Nts_Tcp_Meta_tkeep

siSHL_Nts_Tcp_Meta_tkeep in std_ulogic_vector ( 1 downto 0 )
Port

Definition at line 130 of file Role.vhdl.

◆ siSHL_Nts_Tcp_Meta_tlast

siSHL_Nts_Tcp_Meta_tlast in std_ulogic
Port

Definition at line 131 of file Role.vhdl.

◆ siSHL_Nts_Tcp_Meta_tready

siSHL_Nts_Tcp_Meta_tready out std_ulogic
Port

Definition at line 133 of file Role.vhdl.

◆ siSHL_Nts_Tcp_Meta_tvalid

siSHL_Nts_Tcp_Meta_tvalid in std_ulogic
Port

Definition at line 132 of file Role.vhdl.

◆ siSHL_Nts_Tcp_Notif_tdata

siSHL_Nts_Tcp_Notif_tdata in std_ulogic_vector ( 7 + 96 downto 0 )
Port

Definition at line 135 of file Role.vhdl.

◆ siSHL_Nts_Tcp_Notif_tready

siSHL_Nts_Tcp_Notif_tready out std_ulogic
Port

Definition at line 137 of file Role.vhdl.

◆ siSHL_Nts_Tcp_Notif_tvalid

siSHL_Nts_Tcp_Notif_tvalid in std_ulogic
Port

Definition at line 136 of file Role.vhdl.

◆ siSHL_Nts_Tcp_OpnRep_tdata

siSHL_Nts_Tcp_OpnRep_tdata in std_ulogic_vector ( 23 downto 0 )
Port

Definition at line 152 of file Role.vhdl.

◆ siSHL_Nts_Tcp_OpnRep_tready

siSHL_Nts_Tcp_OpnRep_tready out std_ulogic
Port

Definition at line 154 of file Role.vhdl.

◆ siSHL_Nts_Tcp_OpnRep_tvalid

siSHL_Nts_Tcp_OpnRep_tvalid in std_ulogic
Port

Definition at line 153 of file Role.vhdl.

◆ siSHL_Nts_Tcp_SndRep_tdata

siSHL_Nts_Tcp_SndRep_tdata in std_ulogic_vector ( 55 downto 0 )
Port

Definition at line 128 of file Role.vhdl.

◆ siSHL_Nts_Tcp_SndRep_tready

siSHL_Nts_Tcp_SndRep_tready out std_ulogic
Port

Definition at line 130 of file Role.vhdl.

◆ siSHL_Nts_Tcp_SndRep_tvalid

siSHL_Nts_Tcp_SndRep_tvalid in std_ulogic
Port

Definition at line 129 of file Role.vhdl.

◆ siSHL_Nts_Udp_ClsRep_tdata

siSHL_Nts_Udp_ClsRep_tdata in std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 111 of file Role.vhdl.

◆ siSHL_Nts_Udp_ClsRep_tready

siSHL_Nts_Udp_ClsRep_tready out std_ulogic
Port

Definition at line 113 of file Role.vhdl.

◆ siSHL_Nts_Udp_ClsRep_tvalid

siSHL_Nts_Udp_ClsRep_tvalid in std_ulogic
Port

Definition at line 112 of file Role.vhdl.

◆ siSHL_Nts_Udp_Data_tdata

siSHL_Nts_Udp_Data_tdata in std_ulogic_vector ( 63 downto 0 )
Port

Definition at line 87 of file Role.vhdl.

◆ siSHL_Nts_Udp_Data_tkeep

siSHL_Nts_Udp_Data_tkeep in std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 88 of file Role.vhdl.

◆ siSHL_Nts_Udp_Data_tlast

siSHL_Nts_Udp_Data_tlast in std_ulogic
Port

Definition at line 89 of file Role.vhdl.

◆ siSHL_Nts_Udp_Data_tready

siSHL_Nts_Udp_Data_tready out std_ulogic
Port

Definition at line 91 of file Role.vhdl.

◆ siSHL_Nts_Udp_Data_tvalid

siSHL_Nts_Udp_Data_tvalid in std_ulogic
Port

Definition at line 90 of file Role.vhdl.

◆ siSHL_Nts_Udp_DLen_tdata

siSHL_Nts_Udp_DLen_tdata in std_ulogic_vector ( 15 downto 0 )
Port

Definition at line 75 of file Role.vhdl.

◆ siSHL_Nts_Udp_DLen_tready

siSHL_Nts_Udp_DLen_tready out std_ulogic
Port

Definition at line 77 of file Role.vhdl.

◆ siSHL_Nts_Udp_DLen_tvalid

siSHL_Nts_Udp_DLen_tvalid in std_ulogic
Port

Definition at line 76 of file Role.vhdl.

◆ siSHL_Nts_Udp_LsnRep_tdata

siSHL_Nts_Udp_LsnRep_tdata in std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 103 of file Role.vhdl.

◆ siSHL_Nts_Udp_LsnRep_tready

siSHL_Nts_Udp_LsnRep_tready out std_ulogic
Port

Definition at line 105 of file Role.vhdl.

◆ siSHL_Nts_Udp_LsnRep_tvalid

siSHL_Nts_Udp_LsnRep_tvalid in std_ulogic
Port

Definition at line 104 of file Role.vhdl.

◆ siSHL_Nts_Udp_Meta_tdata

siSHL_Nts_Udp_Meta_tdata in std_ulogic_vector ( 95 downto 0 )
Port

Definition at line 71 of file Role.vhdl.

◆ siSHL_Nts_Udp_Meta_tready

siSHL_Nts_Udp_Meta_tready out std_ulogic
Port

Definition at line 73 of file Role.vhdl.

◆ siSHL_Nts_Udp_Meta_tvalid

siSHL_Nts_Udp_Meta_tvalid in std_ulogic
Port

Definition at line 72 of file Role.vhdl.

◆ soSHL_Mem_Mp0_RdCmd_tdata

soSHL_Mem_Mp0_RdCmd_tdata out std_ulogic_vector ( 79 downto 0 )
Port

Definition at line 178 of file Role.vhdl.

◆ soSHL_Mem_Mp0_RdCmd_tready

soSHL_Mem_Mp0_RdCmd_tready in std_ulogic
Port

Definition at line 180 of file Role.vhdl.

◆ soSHL_Mem_Mp0_RdCmd_tvalid

soSHL_Mem_Mp0_RdCmd_tvalid out std_ulogic
Port

Definition at line 179 of file Role.vhdl.

◆ soSHL_Mem_Mp0_WrCmd_tdata

soSHL_Mem_Mp0_WrCmd_tdata out std_ulogic_vector ( 79 downto 0 )
Port

Definition at line 192 of file Role.vhdl.

◆ soSHL_Mem_Mp0_WrCmd_tready

soSHL_Mem_Mp0_WrCmd_tready in std_ulogic
Port

Definition at line 194 of file Role.vhdl.

◆ soSHL_Mem_Mp0_WrCmd_tvalid

soSHL_Mem_Mp0_WrCmd_tvalid out std_ulogic
Port

Definition at line 193 of file Role.vhdl.

◆ soSHL_Mem_Mp0_Write_tdata

soSHL_Mem_Mp0_Write_tdata out std_ulogic_vector ( 511 downto 0 )
Port

Definition at line 200 of file Role.vhdl.

◆ soSHL_Mem_Mp0_Write_tkeep

soSHL_Mem_Mp0_Write_tkeep out std_ulogic_vector ( 63 downto 0 )
Port

Definition at line 201 of file Role.vhdl.

◆ soSHL_Mem_Mp0_Write_tlast

soSHL_Mem_Mp0_Write_tlast out std_ulogic
Port

Definition at line 202 of file Role.vhdl.

◆ soSHL_Mem_Mp0_Write_tready

soSHL_Mem_Mp0_Write_tready in std_ulogic
Port

Definition at line 204 of file Role.vhdl.

◆ soSHL_Mem_Mp0_Write_tvalid

soSHL_Mem_Mp0_Write_tvalid out std_ulogic
Port

Definition at line 203 of file Role.vhdl.

◆ soSHL_Mem_Mp1_RdCmd_tdata

soSHL_Mem_Mp1_RdCmd_tdata out std_ulogic_vector ( 79 downto 0 )
Port

Definition at line 211 of file Role.vhdl.

◆ soSHL_Mem_Mp1_RdCmd_tready

soSHL_Mem_Mp1_RdCmd_tready in std_ulogic
Port

Definition at line 213 of file Role.vhdl.

◆ soSHL_Mem_Mp1_RdCmd_tvalid

soSHL_Mem_Mp1_RdCmd_tvalid out std_ulogic
Port

Definition at line 212 of file Role.vhdl.

◆ soSHL_Mem_Mp1_WrCmd_tdata

soSHL_Mem_Mp1_WrCmd_tdata out std_ulogic_vector ( 79 downto 0 )
Port

Definition at line 225 of file Role.vhdl.

◆ soSHL_Mem_Mp1_WrCmd_tready

soSHL_Mem_Mp1_WrCmd_tready in std_ulogic
Port

Definition at line 227 of file Role.vhdl.

◆ soSHL_Mem_Mp1_WrCmd_tvalid

soSHL_Mem_Mp1_WrCmd_tvalid out std_ulogic
Port

Definition at line 226 of file Role.vhdl.

◆ soSHL_Mem_Mp1_Write_tdata

soSHL_Mem_Mp1_Write_tdata out std_ulogic_vector ( 511 downto 0 )
Port

Definition at line 233 of file Role.vhdl.

◆ soSHL_Mem_Mp1_Write_tkeep

soSHL_Mem_Mp1_Write_tkeep out std_ulogic_vector ( 63 downto 0 )
Port

Definition at line 234 of file Role.vhdl.

◆ soSHL_Mem_Mp1_Write_tlast

soSHL_Mem_Mp1_Write_tlast out std_ulogic
Port

Definition at line 235 of file Role.vhdl.

◆ soSHL_Mem_Mp1_Write_tready

soSHL_Mem_Mp1_Write_tready in std_ulogic
Port

Definition at line 237 of file Role.vhdl.

◆ soSHL_Mem_Mp1_Write_tvalid

soSHL_Mem_Mp1_Write_tvalid out std_ulogic
Port

Definition at line 236 of file Role.vhdl.

◆ soSHL_Nts_Tcp_ClsReq_tdata

soSHL_Nts_Tcp_ClsReq_tdata out std_ulogic_vector ( 15 downto 0 )
Port

Definition at line 156 of file Role.vhdl.

◆ soSHL_Nts_Tcp_ClsReq_tready

soSHL_Nts_Tcp_ClsReq_tready in std_ulogic
Port

Definition at line 158 of file Role.vhdl.

◆ soSHL_Nts_Tcp_ClsReq_tvalid

soSHL_Nts_Tcp_ClsReq_tvalid out std_ulogic
Port

Definition at line 157 of file Role.vhdl.

◆ soSHL_Nts_Tcp_Data_tdata

soSHL_Nts_Tcp_Data_tdata out std_ulogic_vector ( 63 downto 0 )
Port

Definition at line 104 of file Role.vhdl.

◆ soSHL_Nts_Tcp_Data_tkeep

soSHL_Nts_Tcp_Data_tkeep out std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 105 of file Role.vhdl.

◆ soSHL_Nts_Tcp_Data_tlast

soSHL_Nts_Tcp_Data_tlast out std_ulogic
Port

Definition at line 106 of file Role.vhdl.

◆ soSHL_Nts_Tcp_Data_tready

soSHL_Nts_Tcp_Data_tready in std_ulogic
Port

Definition at line 108 of file Role.vhdl.

◆ soSHL_Nts_Tcp_Data_tvalid

soSHL_Nts_Tcp_Data_tvalid out std_ulogic
Port

Definition at line 107 of file Role.vhdl.

◆ soSHL_Nts_Tcp_DReq_tdata

soSHL_Nts_Tcp_DReq_tdata out std_ulogic_vector ( 31 downto 0 )
Port

Definition at line 139 of file Role.vhdl.

◆ soSHL_Nts_Tcp_DReq_tready

soSHL_Nts_Tcp_DReq_tready in std_ulogic
Port

Definition at line 141 of file Role.vhdl.

◆ soSHL_Nts_Tcp_DReq_tvalid

soSHL_Nts_Tcp_DReq_tvalid out std_ulogic
Port

Definition at line 140 of file Role.vhdl.

◆ soSHL_Nts_Tcp_LsnReq_tdata

soSHL_Nts_Tcp_LsnReq_tdata out std_ulogic_vector ( 15 downto 0 )
Port

Definition at line 165 of file Role.vhdl.

◆ soSHL_Nts_Tcp_LsnReq_tready

soSHL_Nts_Tcp_LsnReq_tready in std_ulogic
Port

Definition at line 167 of file Role.vhdl.

◆ soSHL_Nts_Tcp_LsnReq_tvalid

soSHL_Nts_Tcp_LsnReq_tvalid out std_ulogic
Port

Definition at line 166 of file Role.vhdl.

◆ soSHL_Nts_Tcp_Meta_tdata

soSHL_Nts_Tcp_Meta_tdata out std_ulogic_vector ( 15 downto 0 )
Port

Definition at line 110 of file Role.vhdl.

◆ soSHL_Nts_Tcp_Meta_tready

soSHL_Nts_Tcp_Meta_tready in std_ulogic
Port

Definition at line 112 of file Role.vhdl.

◆ soSHL_Nts_Tcp_Meta_tvalid

soSHL_Nts_Tcp_Meta_tvalid out std_ulogic
Port

Definition at line 111 of file Role.vhdl.

◆ soSHL_Nts_Tcp_OpnReq_tdata

soSHL_Nts_Tcp_OpnReq_tdata out std_ulogic_vector ( 47 downto 0 )
Port

Definition at line 148 of file Role.vhdl.

◆ soSHL_Nts_Tcp_OpnReq_tready

soSHL_Nts_Tcp_OpnReq_tready in std_ulogic
Port

Definition at line 150 of file Role.vhdl.

◆ soSHL_Nts_Tcp_OpnReq_tvalid

soSHL_Nts_Tcp_OpnReq_tvalid out std_ulogic
Port

Definition at line 149 of file Role.vhdl.

◆ soSHL_Nts_Tcp_SndReq_tdata

soSHL_Nts_Tcp_SndReq_tdata out std_ulogic_vector ( 31 downto 0 )
Port

Definition at line 124 of file Role.vhdl.

◆ soSHL_Nts_Tcp_SndReq_tready

soSHL_Nts_Tcp_SndReq_tready in std_ulogic
Port

Definition at line 126 of file Role.vhdl.

◆ soSHL_Nts_Tcp_SndReq_tvalid

soSHL_Nts_Tcp_SndReq_tvalid out std_ulogic
Port

Definition at line 125 of file Role.vhdl.

◆ soSHL_Nts_Udp_ClsReq_tdata

soSHL_Nts_Udp_ClsReq_tdata out std_ulogic_vector ( 15 downto 0 )
Port

Definition at line 107 of file Role.vhdl.

◆ soSHL_Nts_Udp_ClsReq_tready

soSHL_Nts_Udp_ClsReq_tready in std_ulogic
Port

Definition at line 109 of file Role.vhdl.

◆ soSHL_Nts_Udp_ClsReq_tvalid

soSHL_Nts_Udp_ClsReq_tvalid out std_ulogic
Port

Definition at line 108 of file Role.vhdl.

◆ soSHL_Nts_Udp_Data_tdata

soSHL_Nts_Udp_Data_tdata out std_ulogic_vector ( 63 downto 0 )
Port

Definition at line 93 of file Role.vhdl.

◆ soSHL_Nts_Udp_Data_tkeep

soSHL_Nts_Udp_Data_tkeep out std_ulogic_vector ( 7 downto 0 )
Port

Definition at line 94 of file Role.vhdl.

◆ soSHL_Nts_Udp_Data_tlast

soSHL_Nts_Udp_Data_tlast out std_ulogic
Port

Definition at line 95 of file Role.vhdl.

◆ soSHL_Nts_Udp_Data_tready

soSHL_Nts_Udp_Data_tready in std_ulogic
Port

Definition at line 97 of file Role.vhdl.

◆ soSHL_Nts_Udp_Data_tvalid

soSHL_Nts_Udp_Data_tvalid out std_ulogic
Port

Definition at line 96 of file Role.vhdl.

◆ soSHL_Nts_Udp_DLen_tdata

soSHL_Nts_Udp_DLen_tdata out std_ulogic_vector ( 15 downto 0 )
Port

Definition at line 92 of file Role.vhdl.

◆ soSHL_Nts_Udp_DLen_tready

soSHL_Nts_Udp_DLen_tready in std_ulogic
Port

Definition at line 94 of file Role.vhdl.

◆ soSHL_Nts_Udp_DLen_tvalid

soSHL_Nts_Udp_DLen_tvalid out std_ulogic
Port

Definition at line 93 of file Role.vhdl.

◆ soSHL_Nts_Udp_LsnReq_tdata

soSHL_Nts_Udp_LsnReq_tdata out std_ulogic_vector ( 15 downto 0 )
Port

Definition at line 99 of file Role.vhdl.

◆ soSHL_Nts_Udp_LsnReq_tready

soSHL_Nts_Udp_LsnReq_tready in std_ulogic
Port

Definition at line 101 of file Role.vhdl.

◆ soSHL_Nts_Udp_LsnReq_tvalid

soSHL_Nts_Udp_LsnReq_tvalid out std_ulogic
Port

Definition at line 100 of file Role.vhdl.

◆ soSHL_Nts_Udp_Meta_tdata

soSHL_Nts_Udp_Meta_tdata out std_ulogic_vector ( 95 downto 0 )
Port

Definition at line 88 of file Role.vhdl.

◆ soSHL_Nts_Udp_Meta_tready

soSHL_Nts_Udp_Meta_tready in std_ulogic
Port

Definition at line 90 of file Role.vhdl.

◆ soSHL_Nts_Udp_Meta_tvalid

soSHL_Nts_Udp_Meta_tvalid out std_ulogic
Port

Definition at line 89 of file Role.vhdl.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 60 of file Role.vhdl.

◆ UNISIM

UNISIM
Library

Definition at line 63 of file Role.vhdl.

◆ vcomponents

vcomponents
use clause

Definition at line 64 of file Role.vhdl.

◆ XIL_DEFAULTLIB

XIL_DEFAULTLIB
Library

Definition at line 44 of file Role.vhdl.


The documentation for this class was generated from the following file: