: Port Table (PRt) of the TCP Offload Engine (TOE) More...

#include "port_table.hpp"

Include dependency graph for port_table.cpp:

Macros
#define	THIS_NAME "TOE/PRt"

#define	TRACE_OFF 0x0000

#define	TRACE_IRR 1 << 1

#define	TRACE_ORM 1 << 2

#define	TRACE_LPT 1 << 3

#define	TRACE_FPT 1 << 4

#define	TRACE_RDY 1 << 5

#define	TRACE_ALL 0xFFFF

#define	DEBUG_LEVEL (TRACE_OFF)

Functions
template<class T >
void	pAnd2 (T &pi1, T &pi2, T &po)
	A two inputs 'AND' gate. More...

void	pReady (StsBool &piLpt_Ready, StsBool &piFpt_Ready, StsBool &poTOE_Ready)
	Ready Logic (Rdy) More...

void	pListeningPortTable (StsBool &poRdy_Ready, stream< TcpPort > &siRAi_OpenLsnPortReq, stream< RepBit > &soRAi_OpenLsnPortRep, stream< TcpStaPort > &siIrr_GetPortStateCmd, stream< RspBit > &soOrm_GetPortStateRsp)
	Listening Port Table (Lpt) More...

void	pFreePortTable (StsBool &poRdy_Ready, stream< TcpPort > &siSLc_CloseActPortCmd, stream< TcpDynPort > &siIrr_GetPortStateCmd, stream< RspBit > &soOrm_GetPortStateRsp, stream< ReqBit > &siTAi_GetFreePortReq, stream< TcpPort > &soTAi_GetFreePortRep)
	Free Port Table (Fpt) More...

void	pInputRequestRouter (stream< TcpPort > &siRXe_GetPortStateCmd, stream< TcpStaPort > &soLpt_GetLsnPortStateCmd, stream< TcpDynPort > &soFpt_GetActPortStateCmd, stream< bool > &soOrm_QueryRange)
	Input Request Router (Irr) More...

void	pOutputReplyMultiplexer (stream< bool > &siIrr_QueryRange, stream< RspBit > &siLpt_GetLsnPortStateRsp, stream< RspBit > &siFpt_GetActPortStateRsp, stream< RspBit > &soRXe_GetPortStateRsp)
	Output Reply Multiplexer (Orm) More...

void	port_table (StsBool &poTOE_Ready, stream< TcpPort > &siRXe_GetPortStateReq, stream< RepBit > &soRXe_GetPortStateRep, stream< TcpPort > &siRAi_OpenLsnPortReq, stream< AckBit > &soRAi_OpenLsnPortAck, stream< ReqBit > &siTAi_GetFreePortReq, stream< TcpPort > &soTAi_GetFreePortRep, stream< TcpPort > &siSLc_CloseActPortCmd)
	Port Table (PRt) More...

Variables
bool	gTraceEvent

Detailed Description

: Port Table (PRt) of the TCP Offload Engine (TOE)

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. Copyright (c) 2015, Xilinx, Inc.

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System: : cloudFPGA Component : Shell, Network Transport Stack (NTS) Language : Vivado HLS

Definition in file port_table.cpp.

Macros

Functions

Variables

Detailed Description