68 #define THIS_NAME "TOE/PRt"
70 #define TRACE_OFF 0x0000
71 #define TRACE_IRR 1 << 1
72 #define TRACE_ORM 1 << 2
73 #define TRACE_LPT 1 << 3
74 #define TRACE_FPT 1 << 4
75 #define TRACE_RDY 1 << 5
76 #define TRACE_ALL 0xFFFF
78 #define DEBUG_LEVEL (TRACE_OFF)
90 #pragma HLS INLINE off
113 poTOE_Ready = piLpt_Ready and piFpt_Ready;
117 printInfo(myName,
"Process [PRt] is ready.\n");
143 stream<TcpPort> &siRAi_OpenLsnPortReq,
144 stream<RepBit> &soRAi_OpenLsnPortRep,
145 stream<TcpStaPort> &siIrr_GetPortStateCmd,
146 stream<RspBit> &soOrm_GetPortStateRsp)
149 #pragma HLS PIPELINE II=1 enable_flush
150 #pragma HLS INLINE off
155 static PortState LISTEN_PORT_TABLE[0x8000];
156 #pragma HLS RESOURCE variable=LISTEN_PORT_TABLE core=RAM_T2P_BRAM
157 #pragma HLS DEPENDENCE variable=LISTEN_PORT_TABLE inter false
160 static bool lpt_isLPtInit=
false;
161 #pragma HLS reset variable=lpt_isLPtInit
162 static TcpPort lpt_lsnPortNum=0;
163 #pragma HLS reset variable=lpt_lsnPortNum
166 if (!lpt_isLPtInit) {
167 LISTEN_PORT_TABLE[lpt_lsnPortNum(14, 0)] =
STS_CLOSED;
169 if (lpt_lsnPortNum == 0x8000) {
170 lpt_isLPtInit =
true;
172 printInfo(myName,
"Done with initialization of LISTEN_PORT_TABLE.\n");
177 if (!siRAi_OpenLsnPortReq.empty() and !soRAi_OpenLsnPortRep.full()) {
178 siRAi_OpenLsnPortReq.read(lpt_lsnPortNum);
180 if (lpt_lsnPortNum < 0x8000) {
183 LISTEN_PORT_TABLE[lpt_lsnPortNum] =
STS_OPENED;
187 printInfo(myName,
"[RAi] is requesting to open port #%d in listen mode.\n",
188 lpt_lsnPortNum.to_uint());
194 else if (!siIrr_GetPortStateCmd.empty()) {
197 TcpStaPort staticPortNum = siIrr_GetPortStateCmd.read();
199 soOrm_GetPortStateRsp.write(LISTEN_PORT_TABLE[staticPortNum]);
201 printInfo(myName,
"[RXe] is querying the state of listen port #%d \n",
202 staticPortNum.to_uint());
206 poRdy_Ready = lpt_isLPtInit;
234 stream<TcpPort> &siSLc_CloseActPortCmd,
235 stream<TcpDynPort> &siIrr_GetPortStateCmd,
236 stream<RspBit> &soOrm_GetPortStateRsp,
237 stream<ReqBit> &siTAi_GetFreePortReq,
238 stream<TcpPort> &soTAi_GetFreePortRep)
242 #pragma HLS PIPELINE II=1 enable_flush
243 #pragma HLS INLINE off
248 static PortRange ACTIVE_PORT_TABLE[0x8000];
249 #pragma HLS RESOURCE variable=ACTIVE_PORT_TABLE core=RAM_T2P_BRAM
250 #pragma HLS DEPENDENCE variable=ACTIVE_PORT_TABLE inter false
253 static bool fpt_isFPtInit=
false;
254 #pragma HLS reset variable=fpt_isFPtInit
255 static bool fpt_searching=
false;
256 #pragma HLS reset variable=fpt_searching
257 static bool fpt_eval=
false;
258 #pragma HLS reset variable=fpt_eval
260 #pragma HLS reset variable=fpt_dynPortNum
264 #pragma HLS DEPENDENCE variable=portState inter false
267 if (!fpt_isFPtInit) {
270 if (fpt_dynPortNum == 0) {
271 fpt_isFPtInit =
true;
273 printInfo(myName,
"Done with initialization of ACTIVE_PORT_TABLE.\n");
279 portState = ACTIVE_PORT_TABLE[fpt_dynPortNum];
280 fpt_searching =
false;
286 if (!soTAi_GetFreePortRep.full()) {
291 soTAi_GetFreePortRep.write(0x8000 + fpt_dynPortNum);
296 fpt_searching =
true;
300 else if (!siIrr_GetPortStateCmd.empty()) {
303 TcpDynPort portNum = siIrr_GetPortStateCmd.read();
304 soOrm_GetPortStateRsp.write(ACTIVE_PORT_TABLE[portNum]);
306 else if (!siTAi_GetFreePortReq.empty()) {
307 siTAi_GetFreePortReq.read();
308 fpt_searching =
true;
310 else if (!siSLc_CloseActPortCmd.empty()) {
311 TcpPort tcpPort = siSLc_CloseActPortCmd.read();
312 if (tcpPort.bit(15) == 1) {
316 #ifndef __SYNTHESIS__
318 printError(myName,
"SLc is not allowed to release a static port.\n");
325 poRdy_Ready = fpt_isFPtInit;
344 stream<TcpPort> &siRXe_GetPortStateCmd,
345 stream<TcpStaPort> &soLpt_GetLsnPortStateCmd,
346 stream<TcpDynPort> &soFpt_GetActPortStateCmd,
347 stream<PortRange> &soOrm_QueryRange)
350 #pragma HLS PIPELINE II=1 enable_flush
351 #pragma HLS INLINE off
356 if (!siRXe_GetPortStateCmd.empty()) {
357 TcpPort portToCheck = siRXe_GetPortStateCmd.read();
359 printInfo(myName,
"[RXe] is requesting the state of port #%d.\n", portToCheck.to_int());
361 if (portToCheck < 0x8000) {
363 soLpt_GetLsnPortStateCmd.write(portToCheck.range(14, 0));
368 soFpt_GetActPortStateCmd.write(portToCheck.range(14, 0));
388 stream<PortRange> &siIrr_QueryRange,
389 stream<RspBit> &siLpt_GetLsnPortStateRsp,
390 stream<RspBit> &siFpt_GetActPortStateRsp,
391 stream<RspBit> &soRXe_GetPortStateRsp)
394 #pragma HLS PIPELINE II=1 enable_flush
395 #pragma HLS INLINE off
398 static enum FsmStates { ORM_WAIT_FOR_QUERY_FROM_Irr=0,
399 ORM_FORWARD_LSN_PORT_STATE_RSP,
400 ORM_FORWARD_ACT_PORT_STATE_RSP } orm_fsmState=ORM_WAIT_FOR_QUERY_FROM_Irr;
403 switch (orm_fsmState) {
404 case ORM_WAIT_FOR_QUERY_FROM_Irr:
405 if (!siIrr_QueryRange.empty()) {
406 PortRange qryType = siIrr_QueryRange.read();
408 orm_fsmState = ORM_FORWARD_LSN_PORT_STATE_RSP;
410 orm_fsmState = ORM_FORWARD_ACT_PORT_STATE_RSP;
413 case ORM_FORWARD_LSN_PORT_STATE_RSP:
414 if (!siLpt_GetLsnPortStateRsp.empty() and !soRXe_GetPortStateRsp.full()) {
415 soRXe_GetPortStateRsp.write(siLpt_GetLsnPortStateRsp.read());
416 orm_fsmState = ORM_WAIT_FOR_QUERY_FROM_Irr;
419 case ORM_FORWARD_ACT_PORT_STATE_RSP:
420 if (!siFpt_GetActPortStateRsp.empty() and !soRXe_GetPortStateRsp.full()) {
421 soRXe_GetPortStateRsp.write(siFpt_GetActPortStateRsp.read());
422 orm_fsmState = ORM_WAIT_FOR_QUERY_FROM_Irr;
455 stream<TcpPort> &siRXe_GetPortStateReq,
456 stream<RepBit> &soRXe_GetPortStateRep,
457 stream<TcpPort> &siRAi_OpenLsnPortReq,
458 stream<AckBit> &soRAi_OpenLsnPortAck,
459 stream<ReqBit> &siTAi_GetFreePortReq,
460 stream<TcpPort> &soTAi_GetFreePortRep,
461 stream<TcpPort> &siSLc_CloseActPortCmd)
473 static stream<TcpStaPort> ssIrrToLpt_GetLsnPortStateCmd (
"ssIrrToLpt_GetLsnPortStateCmd");
474 #pragma HLS STREAM variable=ssIrrToLpt_GetLsnPortStateCmd depth=2
476 static stream<TcpDynPort> ssIrrToFpt_GetActPortStateCmd (
"ssIrrToFpt_GetActPortStateCmd");
477 #pragma HLS STREAM variable=ssIrrToFpt_GetActPortStateCmd depth=2
479 static stream<bool> ssIrrToOrm_QueryRange (
"ssIrrToOrm_QueryRange");
480 #pragma HLS STREAM variable=ssIrrToOrm_QueryRange depth=4
484 static stream<RspBit> ssLptToOrm_GetLsnPortStateRsp (
"ssLptToOrm_GetLsnPortStateRsp");
485 #pragma HLS STREAM variable=ssLptToOrm_GetLsnPortStateRsp depth=2
489 static stream<RspBit> ssFptToOrm_GetActPortStateRsp (
"ssFptToOrm_GetActPortStateRsp");
490 #pragma HLS STREAM variable=ssFptToOrm_GetActPortStateRsp depth=2
498 siRAi_OpenLsnPortReq,
499 soRAi_OpenLsnPortAck,
500 ssIrrToLpt_GetLsnPortStateCmd,
501 ssLptToOrm_GetLsnPortStateRsp);
505 siSLc_CloseActPortCmd,
506 ssIrrToFpt_GetActPortStateCmd,
507 ssFptToOrm_GetActPortStateRsp,
508 siTAi_GetFreePortReq,
509 soTAi_GetFreePortRep);
513 siRXe_GetPortStateReq,
514 ssIrrToLpt_GetLsnPortStateCmd,
515 ssIrrToFpt_GetActPortStateCmd,
516 ssIrrToOrm_QueryRange);
519 ssIrrToOrm_QueryRange,
520 ssLptToOrm_GetLsnPortStateRsp,
521 ssFptToOrm_GetActPortStateRsp,
522 soRXe_GetPortStateRep);
void pOutputReplyMultiplexer(stream< bool > &siIrr_QueryRange, stream< RspBit > &siLpt_GetLsnPortStateRsp, stream< RspBit > &siFpt_GetActPortStateRsp, stream< RspBit > &soRXe_GetPortStateRsp)
Output Reply Multiplexer (Orm)
void pListeningPortTable(StsBool &poRdy_Ready, stream< TcpPort > &siRAi_OpenLsnPortReq, stream< RepBit > &soRAi_OpenLsnPortRep, stream< TcpStaPort > &siIrr_GetPortStateCmd, stream< RspBit > &soOrm_GetPortStateRsp)
Listening Port Table (Lpt)
void port_table(StsBool &poTOE_Ready, stream< TcpPort > &siRXe_GetPortStateReq, stream< RepBit > &soRXe_GetPortStateRep, stream< TcpPort > &siRAi_OpenLsnPortReq, stream< AckBit > &soRAi_OpenLsnPortAck, stream< ReqBit > &siTAi_GetFreePortReq, stream< TcpPort > &soTAi_GetFreePortRep, stream< TcpPort > &siSLc_CloseActPortCmd)
Port Table (PRt)
void pReady(StsBool &piLpt_Ready, StsBool &piFpt_Ready, StsBool &poTOE_Ready)
Ready Logic (Rdy)
void pAnd2(T &pi1, T &pi2, T &po)
A two inputs 'AND' gate.
void pInputRequestRouter(stream< TcpPort > &siRXe_GetPortStateCmd, stream< TcpStaPort > &soLpt_GetLsnPortStateCmd, stream< TcpDynPort > &soFpt_GetActPortStateCmd, stream< bool > &soOrm_QueryRange)
Input Request Router (Irr)
void pFreePortTable(StsBool &poRdy_Ready, stream< TcpPort > &siSLc_CloseActPortCmd, stream< TcpDynPort > &siIrr_GetPortStateCmd, stream< RspBit > &soOrm_GetPortStateRsp, stream< ReqBit > &siTAi_GetFreePortReq, stream< TcpPort > &soTAi_GetFreePortRep)
Free Port Table (Fpt)
#define printError(callerName, format,...)
A macro to print an error message.
#define printInfo(callerName, format,...)
A macro to print an information message.
#define concat3(firstCharConst, secondCharConst, thirdCharConst)
: Port Table (PRt) of the TCP Offload Engine (TOE)