67 #define THIS_NAME "TOE/TXe"
71 #define TRACE_OFF 0x0000
72 #define TRACE_MDL 1 << 1
73 #define TRACE_IHC 1 << 2
74 #define TRACE_SPS 1 << 3
75 #define TRACE_PHC 1 << 4
76 #define TRACE_MRD 1 << 5
77 #define TRACE_TSS 1 << 6
78 #define TRACE_SCA 1 << 7
79 #define TRACE_TCA 1 << 8
80 #define TRACE_IPS 1 << 9
81 #define TRACE_ALL 0xFFFF
83 #define DEBUG_LEVEL (TRACE_OFF)
118 stream<ExtendedEvent> &siAKd_Event,
119 stream<SessionId> &soRSt_RxSarReq,
120 stream<RxSarReply> &siRSt_RxSarRep,
121 stream<TXeTxSarQuery> &soTSt_TxSarQry,
122 stream<TXeTxSarReply> &siTSt_TxSarRep,
123 stream<TXeReTransTimerCmd> &soTIm_ReTxTimerCmd,
124 stream<SessionId> &soTIm_SetProbeTimer,
125 stream<TcpDatLen> &soIhc_TcpDatLen,
126 stream<TXeMeta> &soPhc_TxeMeta,
127 stream<DmCmd> &soMrd_BufferRdCmd,
128 stream<SessionId> &soSLc_ReverseLkpReq,
129 stream<StsBool> &soSps_IsLookup,
131 stream<bool> &soTODO_IsDdrBypass,
133 stream<LE_SocketPair> &soSps_RstSockPair,
134 stream<SigBit> &soEVe_RxEventSig)
137 #pragma HLS INLINE off
138 #pragma HLS PIPELINE II=1 enable_flush
143 static enum FsmStates { MDL_WAIT_EVENT=0, MDL_PROCESS_EVENT } \
144 mdl_fsmState=MDL_WAIT_EVENT;
145 #pragma HLS RESET variable=mdl_fsmState
146 static FlagBool mdl_sarLoaded=
false;
147 #pragma HLS RESET variable=mdl_sarLoaded
148 static ap_uint<2> mdl_segmentCount=0;
149 #pragma HLS RESET variable=mdl_segmentCount
155 static ap_uint<32> mdl_randomValue = 100000;
162 ap_uint<16> slowstart_threshold;
165 switch (mdl_fsmState) {
167 if (!siAKd_Event.empty()) {
168 siAKd_Event.read(mdl_curEvent);
170 printInfo(myName,
"Received event '%s' for session #%d from [AKd].\n",
173 mdl_sarLoaded =
false;
174 assessSize(myName, soEVe_RxEventSig,
"soEVe_RxEventSig", 2);
175 soEVe_RxEventSig.write(1);
178 switch(mdl_curEvent.
type) {
186 soRSt_RxSarReq.write(mdl_curEvent.
sessionID);
192 resetEvent = mdl_curEvent;
207 mdl_fsmState = MDL_PROCESS_EVENT;
211 mdl_segmentCount = 0;
213 case MDL_PROCESS_EVENT:
214 switch(mdl_curEvent.
type) {
220 if ((!rxSar2txEng_rsp.empty() && !txSar2txEng_upd_rsp.empty()) || ml_sarLoaded) {
222 rxSar2txEng_rsp.read(rxSar);
223 txSar2txEng_upd_rsp.read(mdl_txSar);
227 winSize = (rxSar.appd - ((ap_uint<16>)rxSar.recvd)) - 1;
228 meta.ackNumb = rxSar.recvd;
230 meta.window_size = winSize;
237 if (0x7FFF < ml_curEvent.length) {
238 txEng2timer_setProbeTimer.write(ml_curEvent.sessionID);
241 meta.length = ml_curEvent.length;
244 mdl_txSar.
not_ackd += ml_curEvent.length;
246 txEng2txSar_upd_req.write(txTxSarQuery(ml_curEvent.sessionID, mdl_txSar.
not_ackd, 1));
250 if (meta.length != 0) {
251 txEng_ipMetaFifoOut.write(meta.length);
252 txEng_tcpMetaFifoOut.write(meta);
253 txEng_isLookUpFifoOut.write(
true);
254 txEng_isDDRbypass.write(
true);
255 txEng2sLookup_rev_req.write(ml_curEvent.sessionID);
258 txEng2timer_setRetransmitTimer.write(txRetransmitTimerSet(ml_curEvent.sessionID));
266 printInfo(myName,
"Entering the 'TX' processing.\n");
269 if ((!siRSt_RxSarRep.empty() and !siTSt_TxSarRep.empty()) or mdl_sarLoaded) {
270 if (!mdl_sarLoaded) {
271 siRSt_RxSarRep.read(mdl_rxSar);
272 siTSt_TxSarRep.read(mdl_txSar);
290 usableWindow = mdl_txSar.
min_window - usedLength;
298 TxMemPtr memSegAddr = TOE_TX_MEMORY_BASE;
299 memSegAddr(29, 16) = mdl_curEvent.
sessionID(13, 0);
300 memSegAddr(15, 0) = mdl_txSar.
not_ackd(15, 0);
303 if (currDatLen <= usableWindow) {
318 mdl_txeMeta.
length = currDatLen;
319 mdl_fsmState = MDL_WAIT_EVENT;
338 mdl_txeMeta.
length = usableWindow;
344 mdl_fsmState = MDL_WAIT_EVENT;
348 if (mdl_txeMeta.
length != 0) {
349 soMrd_BufferRdCmd.write(
DmCmd(memSegAddr, mdl_txeMeta.
length));
352 if (mdl_txeMeta.
length != 0) {
353 soIhc_TcpDatLen.write(mdl_txeMeta.
length);
354 soPhc_TxeMeta.write(mdl_txeMeta);
355 soSps_IsLookup.write(
true);
356 soSLc_ReverseLkpReq.write(mdl_curEvent.
sessionID);
361 mdl_sarLoaded =
true;
367 if ((!siRSt_RxSarRep.empty() && !siTSt_TxSarRep.empty()) || mdl_sarLoaded) {
368 if (!mdl_sarLoaded) {
369 siRSt_RxSarRep.read(mdl_rxSar);
370 siTSt_TxSarRep.read(mdl_txSar);
388 memSegAddr(31, 30) = 0x01;
389 memSegAddr(29, 16) = mdl_curEvent.
sessionID(13, 0);
390 memSegAddr(15, 0) = mdl_txSar.
ackd(15, 0);
392 if (!mdl_sarLoaded and (mdl_curEvent.
rt_count == 1)) {
393 if (currDatLen > (4*ZYC2_MSS)) {
394 slowstart_threshold = currDatLen/2;
397 slowstart_threshold = (2 * ZYC2_MSS);
409 if (mdl_segmentCount == 3) {
412 mdl_fsmState = MDL_WAIT_EVENT;
417 mdl_txeMeta.
length = currDatLen;
422 mdl_fsmState = MDL_WAIT_EVENT;
427 if (mdl_txeMeta.
length != 0) {
428 soMrd_BufferRdCmd.write(
DmCmd(memSegAddr, mdl_txeMeta.
length));
429 soIhc_TcpDatLen.write(mdl_txeMeta.
length);
430 soPhc_TxeMeta.write(mdl_txeMeta);
431 soSps_IsLookup.write(
true);
433 soTODO_isDDRbypass.write(
false);
435 soSLc_ReverseLkpReq.write(mdl_curEvent.
sessionID);
439 mdl_sarLoaded =
true;
445 if (!siRSt_RxSarRep.empty() and !siTSt_TxSarRep.empty()) {
446 siRSt_RxSarRep.read(mdl_rxSar);
447 siTSt_TxSarRep.read(mdl_txSar);
459 soIhc_TcpDatLen.write(mdl_txeMeta.
length);
460 soPhc_TxeMeta.write(mdl_txeMeta);
461 soSps_IsLookup.write(
true);
462 soSLc_ReverseLkpReq.write(mdl_curEvent.
sessionID);
463 mdl_fsmState = MDL_WAIT_EVENT;
468 if (((mdl_curEvent.
rt_count != 0) and !siTSt_TxSarRep.empty()) or (mdl_curEvent.
rt_count == 0)) {
470 siTSt_TxSarRep.read(mdl_txSar);
474 mdl_txSar.
not_ackd = mdl_randomValue;
475 mdl_randomValue = (mdl_randomValue* 8) xor mdl_randomValue;
488 soIhc_TcpDatLen.write(mdl_txeMeta.
length);
489 soPhc_TxeMeta.write(mdl_txeMeta);
490 soSps_IsLookup.write(
true);
491 soSLc_ReverseLkpReq.write(mdl_curEvent.
sessionID);
494 mdl_fsmState = MDL_WAIT_EVENT;
499 if (!siRSt_RxSarRep.empty() and !siTSt_TxSarRep.empty()) {
500 siRSt_RxSarRep.read(mdl_rxSar);
501 siTSt_TxSarRep.read(mdl_txSar);
505 mdl_txeMeta.
winSize = MY_MSS * 12;
515 mdl_txSar.
not_ackd = mdl_randomValue;
516 mdl_randomValue = (mdl_randomValue* 8) xor mdl_randomValue;
522 soIhc_TcpDatLen.write(mdl_txeMeta.
length);
523 soPhc_TxeMeta.write(mdl_txeMeta);
524 soSps_IsLookup.write(
true);
525 soSLc_ReverseLkpReq.write(mdl_curEvent.
sessionID);
528 mdl_fsmState = MDL_WAIT_EVENT;
533 if ((!siRSt_RxSarRep.empty() && !siTSt_TxSarRep.empty()) || mdl_sarLoaded) {
534 if (!mdl_sarLoaded) {
535 siRSt_RxSarRep.read(mdl_rxSar);
536 siTSt_TxSarRep.read(mdl_txSar);
566 if (mdl_txeMeta.
seqNumb(15, 0) == mdl_txSar.
app) {
567 soIhc_TcpDatLen.write(mdl_txeMeta.
length);
568 soPhc_TxeMeta.write(mdl_txeMeta);
569 soSps_IsLookup.write(
true);
570 soSLc_ReverseLkpReq.write(mdl_curEvent.
sessionID);
574 mdl_fsmState = MDL_WAIT_EVENT;
580 resetEvent = mdl_curEvent;
582 soIhc_TcpDatLen.write(0);
584 soSps_IsLookup.write(
false);
585 soSps_RstSockPair.write(mdl_curEvent.
tuple);
586 mdl_fsmState = MDL_WAIT_EVENT;
588 else if (!siTSt_TxSarRep.empty()) {
589 siTSt_TxSarRep.read(mdl_txSar);
590 soIhc_TcpDatLen.write(0);
591 soSps_IsLookup.write(
true);
592 soSLc_ReverseLkpReq.write(resetEvent.
sessionID);
595 mdl_fsmState = MDL_WAIT_EVENT;
625 stream<fourTuple> &siSLc_ReverseLkpRsp,
626 stream<LE_SocketPair> &siMdl_RstSockPair,
627 stream<StsBool> &siMdl_IsLookup,
628 stream<IpAddrPair> &soIhc_IpAddrPair,
629 stream<SocketPair> &soPhc_SocketPair)
632 #pragma HLS PIPELINE II=1 enable_flush
633 #pragma HLS INLINE off
638 static bool sps_getMeta=
false;
639 #pragma HLS RESET variable=sps_getMeta
647 if (not sps_getMeta) {
648 if (!siMdl_IsLookup.empty()) {
649 siMdl_IsLookup.read(sps_isLookUp);
654 if (!siSLc_ReverseLkpRsp.empty() && sps_isLookUp) {
655 siSLc_ReverseLkpRsp.read(tuple);
661 printInfo(myName,
"Received the following socket-pair from [SLc]: \n");
665 soPhc_SocketPair.write(socketPair);
668 else if(!siMdl_RstSockPair.empty() && !sps_isLookUp) {
670 siMdl_RstSockPair.read(leSocketPair);
676 printInfo(myName,
"Received the following socket-pair from [Mdl]: \n");
680 soPhc_SocketPair.write(socketPair);
711 stream<TcpDatLen> &siMdl_TcpDatLen,
712 stream<IpAddrPair> &siSps_IpAddrPair,
713 stream<AxisIp4> &soIPs_IpHeader)
716 #pragma HLS INLINE off
717 #pragma HLS PIPELINE II=1 enable_flush
722 static ap_uint<2> ihc_chunkCounter=0;
723 #pragma HLS RESET variable=ihc_chunkCounter
733 switch(ihc_chunkCounter) {
735 if (!siMdl_TcpDatLen.empty()) {
736 siMdl_TcpDatLen.read(tcpDatLen);
750 soIPs_IpHeader.write(currIpHdrChunk);
755 if (!siSps_IpAddrPair.empty()) {
756 siSps_IpAddrPair.read(ihc_ipAddrPair);
766 soIPs_IpHeader.write(currIpHdrChunk);
777 soIPs_IpHeader.write(currIpHdrChunk);
778 ihc_chunkCounter = 0;
819 stream<TXeMeta> &siMdl_TxeMeta,
820 stream<SocketPair> &siSps_SockPair,
821 stream<AxisPsd4> &soTss_PseudoHdr)
824 #pragma HLS INLINE off
825 #pragma HLS PIPELINE II=1 enable_flush
830 static ap_uint<3> phc_chunkCount=0;
831 #pragma HLS RESET variable=phc_chunkCount
841 switch(phc_chunkCount) {
844 if (!siSps_SockPair.empty() && !siMdl_TxeMeta.empty()) {
845 siSps_SockPair.read(phc_socketPair);
846 siMdl_TxeMeta.read(phc_meta);
849 assessSize(myName, soTss_PseudoHdr,
"soTss_PseudoHdr", 32);
850 soTss_PseudoHdr.write(currChunk);
864 assessSize(myName, soTss_PseudoHdr,
"soTss_PseudoHdr", 32);
865 soTss_PseudoHdr.write(currChunk);
873 assessSize(myName, soTss_PseudoHdr,
"soTss_PseudoHdr", 32);
874 soTss_PseudoHdr.write(currChunk);
895 assessSize(myName, soTss_PseudoHdr,
"soTss_PseudoHdr", 32);
896 soTss_PseudoHdr.write(currChunk);
913 assessSize(myName, soTss_PseudoHdr,
"soTss_PseudoHdr", 32);
914 soTss_PseudoHdr.write(currChunk);
938 stream<AxisPsd4> &siPhc_PseudoHdr,
939 stream<AxisApp> &siMEM_TxP_Data,
941 stream<bool> &txEng_isDDRbypass,
942 stream<axiWord> &txApp2txEng_data_stream,
944 stream<AxisPsd4> &soSca_PseudoPkt,
945 stream<FlagBool> &siMrd_SplitSegFlag)
948 #pragma HLS INLINE off
949 #pragma HLS PIPELINE II=1 enable_flush
954 static enum FsmState { TSS_PSD_HDR=0, TSS_PSD_OPT, TSS_DATA,
955 TSS_FWD_1ST_BUF, TSS_FWD_2ND_BUF,
956 TSS_JOIN_2ND_BUF, TSS_RESIDUE } \
957 tss_fsmState=TSS_PSD_HDR;
958 #pragma HLS RESET variable=tss_fsmState
959 static ap_uint<3> tss_psdHdrChunkCount = 0;
960 #pragma HLS RESET variable=tss_psdHdrChunkCount
964 static ap_uint<4> tss_memRdOffset;
968 bool isShortCutData =
false;
970 switch (tss_fsmState) {
973 if (!siPhc_PseudoHdr.empty() and !soSca_PseudoPkt.full()) {
974 AxisPsd4 currHdrChunk = siPhc_PseudoHdr.read();
975 soSca_PseudoPkt.write(currHdrChunk);
978 if (tss_psdHdrChunkCount == 3) {
980 tss_fsmState = TSS_PSD_OPT;
983 tss_fsmState = TSS_DATA;
985 tss_psdHdrChunkCount = 0;
988 tss_psdHdrChunkCount++;
991 tss_fsmState = TSS_PSD_HDR;
992 tss_psdHdrChunkCount = 0;
998 if (!siPhc_PseudoHdr.empty() and !soSca_PseudoPkt.full()) {
999 AxisPsd4 currHdrChunk = siPhc_PseudoHdr.read();
1000 soSca_PseudoPkt.write(currHdrChunk);
1004 printFatal(myName,
"Pseudo Header is malformed...\n");
1006 tss_fsmState = TSS_PSD_HDR;
1011 if (!siMEM_TxP_Data.empty() and !siMrd_SplitSegFlag.empty() and !soSca_PseudoPkt.full()) {
1012 siMrd_SplitSegFlag.read(tss_mustJoin);
1013 AxisApp currAppChunk = siMEM_TxP_Data.read();
1016 if (tss_mustJoin ==
false) {
1019 soSca_PseudoPkt.write((
AxisPsd4)currAppChunk);
1020 tss_fsmState = TSS_PSD_HDR;
1025 tss_memRdOffset = currAppChunk.
getLen();
1026 if (tss_memRdOffset != 8) {
1030 tss_prevChunk = currAppChunk;
1031 tss_fsmState = TSS_JOIN_2ND_BUF;
1037 soSca_PseudoPkt.write((
AxisPsd4)currAppChunk);
1039 tss_fsmState = TSS_FWD_2ND_BUF;
1045 soSca_PseudoPkt.write((
AxisPsd4)currAppChunk);
1047 tss_fsmState = TSS_FWD_1ST_BUF;
1051 case TSS_FWD_1ST_BUF:
1053 if (!siMEM_TxP_Data.empty() and !soSca_PseudoPkt.full()) {
1054 AxisApp currAppChunk = siMEM_TxP_Data.read();
1057 if (tss_mustJoin ==
false) {
1060 soSca_PseudoPkt.write((
AxisPsd4)currAppChunk);
1061 tss_fsmState = TSS_PSD_HDR;
1066 tss_memRdOffset = currAppChunk.
getLen();
1069 if (tss_memRdOffset != 8) {
1073 tss_prevChunk = currAppChunk;
1074 tss_fsmState = TSS_JOIN_2ND_BUF;
1080 soSca_PseudoPkt.write((
AxisPsd4)currAppChunk);
1082 tss_fsmState = TSS_FWD_2ND_BUF;
1088 soSca_PseudoPkt.write((
AxisPsd4)currAppChunk);
1093 case TSS_FWD_2ND_BUF:
1095 if (!siMEM_TxP_Data.empty() and !soSca_PseudoPkt.full()) {
1096 AxisApp currAppChunk = siMEM_TxP_Data.read();
1098 soSca_PseudoPkt.write((
AxisPsd4)currAppChunk);
1102 tss_fsmState = TSS_PSD_HDR;
1106 case TSS_JOIN_2ND_BUF:
1112 if (!siMEM_TxP_Data.empty() and !soSca_PseudoPkt.full()) {
1113 AxisApp currAppChunk = siMEM_TxP_Data.read();
1118 ((
int)tss_memRdOffset*8)-1, 0);
1120 (
int)tss_memRdOffset -1, 0);
1123 ARW -1,((
int)tss_memRdOffset*8));
1125 (
ARW/8)-1, (
int)tss_memRdOffset);
1126 if (currAppChunk.
getLE_TKeep()[8-(
int)tss_memRdOffset] == 0) {
1130 tss_fsmState = TSS_PSD_HDR;
1136 tss_fsmState = TSS_RESIDUE;
1139 soSca_PseudoPkt.write(joinedChunk);
1144 ((
int)tss_memRdOffset*8)-1, 0);
1146 (
int)tss_memRdOffset-1, 0);
1151 if (!soSca_PseudoPkt.full()) {
1154 ((
int)tss_memRdOffset*8)-1, 0);
1156 (
int)tss_memRdOffset-1, 0);
1158 soSca_PseudoPkt.write(lastChunk);
1160 tss_fsmState = TSS_PSD_HDR;
1166 if (!txApp2txEng_data_stream.empty() && !soSca_PseudoPkt.full()) {
1167 txApp2txEng_data_stream.read(currWord);
1168 soSca_PseudoPkt.write(currWord);
1169 if (currWord.last) {
1177 if (!txEng_isDDRbypass.empty()) {
1178 txEng_isDDRbypass.read(isShortCutData);
1179 if (isShortCutData) {
1207 stream<AxisPsd4> &siTss_PseudoPkt,
1208 stream<AxisPsd4> &soIps_PseudoPkt,
1209 stream<SubCSums> &soTca_4SubCsums)
1212 #pragma HLS INLINE off
1213 #pragma HLS PIPELINE II=1 enable_flush
1216 static bool sca_doForwardChunk=
false;
1217 #pragma HLS RESET variable=sca_doForwardChunk
1218 static ap_uint<17> sca_4CSums[4]={0, 0, 0, 0};
1219 #pragma HLS RESET variable=sca_4CSums
1220 #pragma HLS ARRAY_PARTITION \
1221 variable=sca_4CSums complete dim=1
1226 if (!siTss_PseudoPkt.empty()) {
1227 siTss_PseudoPkt.read(currPktChunk);
1228 if (sca_doForwardChunk) {
1231 soIps_PseudoPkt.write(currPktChunk);
1233 for (
int i = 0; i < 4; i++) {
1236 if (currPktChunk.
getLE_TKeep(i*2+1, i*2) == 0x3) {
1237 temp( 7, 0) = currPktChunk.
getLE_TData(i*16+15, i*16+8);
1238 temp(15, 8) = currPktChunk.
getLE_TData(i*16+ 7, i*16);
1239 sca_4CSums[i] += temp;
1240 sca_4CSums[i] = (sca_4CSums[i] + (sca_4CSums[i] >> 16)) & 0xFFFF;
1242 else if (currPktChunk.
getLE_TKeep()[i*2] == 0x1) {
1244 temp(15, 8) = currPktChunk.
getLE_TData(i*16+7, i*16);
1245 sca_4CSums[i] += temp;
1246 sca_4CSums[i] = (sca_4CSums[i] + (sca_4CSums[i] >> 16)) & 0xFFFF;
1250 sca_doForwardChunk =
true;
1253 soTca_4SubCsums.write(sca_4CSums);
1254 sca_doForwardChunk =
false;
1275 stream<SubCSums> &siSca_FourSubCsums,
1276 stream<TcpChecksum> &soIps_TcpCsum)
1279 #pragma HLS INLINE off
1280 #pragma HLS PIPELINE II=1 enable_flush
1284 if (!siSca_FourSubCsums.empty()) {
1285 SubCSums tca_4CSums = siSca_FourSubCsums.read();
1287 tca_4CSums.
sum0 += tca_4CSums.
sum2;
1288 tca_4CSums.
sum1 += tca_4CSums.
sum3;
1289 tca_4CSums.
sum0 = (tca_4CSums.
sum0 + (tca_4CSums.
sum0 >> 16)) & 0xFFFF;
1290 tca_4CSums.
sum1 = (tca_4CSums.
sum1 + (tca_4CSums.
sum1 >> 16)) & 0xFFFF;
1291 tca_4CSums.
sum0 += tca_4CSums.
sum1;
1292 tca_4CSums.
sum0 = (tca_4CSums.
sum0 + (tca_4CSums.
sum0 >> 16)) & 0xFFFF;
1293 tca_4CSums.
sum0 = ~tca_4CSums.
sum0;
1296 printInfo(myName,
"Checksum =0x%4.4X\n", tca_4CSums.
sum0.to_uint());
1298 soIps_TcpCsum.write(tca_4CSums.
sum0);
1317 stream<AxisIp4> &siIhc_IpHeader,
1318 stream<AxisPsd4> &siSca_PseudoPkt,
1319 stream<TcpChecksum> &siTca_TcpCsum,
1320 stream<AxisIp4> &soIPTX_Data)
1323 #pragma HLS INLINE off
1324 #pragma HLS PIPELINE II=1 enable_flush
1329 static ap_uint<3> ips_chunkCount=0;
1330 #pragma HLS RESET variable=ips_chunkCount
1335 AxisIp4 currChunk(0, 0xFF, 0);
1338 switch (ips_chunkCount) {
1341 if (!siIhc_IpHeader.empty() and !soIPTX_Data.full()) {
1342 siIhc_IpHeader.read(ip4HdrChunk);
1343 currChunk = ip4HdrChunk;
1344 soIPTX_Data.write(currChunk);
1351 if (!siIhc_IpHeader.empty() && !siSca_PseudoPkt.empty() and !soIPTX_Data.full()) {
1352 siIhc_IpHeader.read(ip4HdrChunk);
1353 siSca_PseudoPkt.read(tcpPsdChunk);
1357 soIPTX_Data.write(currChunk);
1363 if (!siSca_PseudoPkt.empty() and !soIPTX_Data.full()) {
1364 siSca_PseudoPkt.read(tcpPsdChunk);
1367 soIPTX_Data.write(currChunk);
1373 if (!siSca_PseudoPkt.empty() and !siTca_TcpCsum.empty() and !soIPTX_Data.full()) {
1374 siSca_PseudoPkt.read(tcpPsdChunk);
1375 siTca_TcpCsum.read(tcpCsum);
1377 currChunk = tcpPsdChunk;
1380 soIPTX_Data.write(currChunk);
1390 if (!siSca_PseudoPkt.empty() and !soIPTX_Data.full()) {
1391 siSca_PseudoPkt.read(tcpPsdChunk);
1392 currChunk = tcpPsdChunk;
1393 soIPTX_Data.write(currChunk);
1420 stream<DmCmd> &siMdl_BufferRdCmd,
1421 stream<DmCmd> &soMEM_TxpRdCmd,
1422 stream<FlagBool> &soTss_SplitMemAcc)
1425 #pragma HLS INLINE off
1426 #pragma HLS PIPELINE II=1 enable_flush
1431 static enum FsmState { MRD_1ST_ACCESS=0, MRD_2ND_ACCESS } \
1432 mrd_fsmState=MRD_1ST_ACCESS;
1433 #pragma HLS RESET variable=mrd_fsmState
1436 static DmCmd mrd_memRdCmd;
1438 static uint16_t mrd_debugCounter=1;
1440 switch (mrd_fsmState) {
1441 case MRD_1ST_ACCESS:
1442 if (!siMdl_BufferRdCmd.empty() and !soTss_SplitMemAcc.full() and !soMEM_TxpRdCmd.full()) {
1443 siMdl_BufferRdCmd.read(mrd_memRdCmd);
1445 if ((mrd_memRdCmd.
saddr(TOE_WINDOW_BITS-1, 0) + mrd_memRdCmd.
btt) > TOE_TX_BUFFER_SIZE) {
1447 mrd_firstAccLen = TOE_TX_BUFFER_SIZE - mrd_memRdCmd.
saddr;
1448 mrd_fsmState = MRD_2ND_ACCESS;
1450 soMEM_TxpRdCmd.write(
DmCmd(mrd_memRdCmd.
saddr, mrd_firstAccLen));
1451 soTss_SplitMemAcc.write(
true);
1452 mrd_fsmState = MRD_2ND_ACCESS;
1455 printInfo(myName,
"TCP Tx memory buffer wraps around: This segment is broken in two memory accesses.\n");
1456 printInfo(myName,
"Issuing 1st memory read command #%d - SADDR=0x%9.9x - BTT=%d\n",
1457 mrd_debugCounter, mrd_memRdCmd.
saddr.to_uint(), mrd_firstAccLen.to_uint());
1461 soMEM_TxpRdCmd.write(mrd_memRdCmd);
1462 soTss_SplitMemAcc.write(
false);
1465 printInfo(myName,
"Issuing memory read command #%d - SADDR=0x%9.9x - BTT=%d\n",
1466 mrd_debugCounter, mrd_memRdCmd.
saddr.to_uint(), mrd_memRdCmd.
btt.to_uint());
1472 case MRD_2ND_ACCESS:
1473 if (!soMEM_TxpRdCmd.full()) {
1475 mrd_memRdCmd.
saddr(TOE_WINDOW_BITS-1, 0) = 0;
1476 soMEM_TxpRdCmd.write(
DmCmd(mrd_memRdCmd.
saddr, mrd_memRdCmd.
btt - mrd_firstAccLen));
1477 mrd_fsmState = MRD_1ST_ACCESS;
1480 printInfo(myName,
"Issuing 2nd memory read command #%d - SADDR=0x%9.9x - BTT=%d\n",
1481 mrd_debugCounter, mrd_memRdCmd.
saddr.to_uint(),
1482 (mrd_memRdCmd.
btt - mrd_firstAccLen).to_uint());
1519 stream<ExtendedEvent> &siAKd_Event,
1520 stream<SigBit> &soEVe_RxEventSig,
1522 stream<SessionId> &soRSt_RxSarReq,
1523 stream<RxSarReply> &siRSt_RxSarRep,
1525 stream<TXeTxSarQuery> &soTSt_TxSarQry,
1526 stream<TXeTxSarReply> &siTSt_TxSarRep,
1528 stream<DmCmd> &soMEM_Txp_RdCmd,
1529 stream<AxisApp> &siMEM_TxP_Data,
1531 stream<TXeReTransTimerCmd> &soTIm_ReTxTimerCmd,
1532 stream<SessionId> &soTIm_SetProbeTimer,
1534 stream<SessionId> &soSLc_ReverseLkpReq,
1535 stream<fourTuple> &siSLc_ReverseLkpRep,
1537 stream<AxisIp4> &soIPTX_Data)
1540 #pragma HLS DATAFLOW
1541 #pragma HLS INTERFACE ap_ctrl_none port=return
1550 static stream<TcpDatLen> ssMdlToIhc_TcpDatLen (
"ssMdlToIhc_TcpDatLen");
1551 #pragma HLS stream variable=ssMdlToIhc_TcpDatLen depth=16
1553 static stream<TXeMeta> ssMdlToPhc_TxeMeta (
"ssMdlToPhc_TxeMeta");
1554 #pragma HLS stream variable=ssMdlToPhc_TxeMeta depth=16
1555 #pragma HLS DATA_PACK variable=ssMdlToPhc_TxeMeta
1557 static stream<bool> ssMdlToSpS_IsLookup (
"ssMdlToSpS_IsLookup");
1558 #pragma HLS stream variable=ssMdlToSpS_IsLookup depth=4
1560 static stream<DmCmd> ssMdlToMrd_BufferRdCmd (
"ssMdlToMrd_BufferRdCmd");
1561 #pragma HLS stream variable=ssMdlToMrd_BufferRdCmd depth=32
1562 #pragma HLS DATA_PACK variable=ssMdlToMrd_BufferRdCmd
1564 static stream<LE_SocketPair> ssMdlToSps_RstSockPair (
"ssMdlToSps_RstSockPair");
1565 #pragma HLS stream variable=ssMdlToSps_RstSockPair depth=2
1566 #pragma HLS DATA_PACK variable=ssMdlToSps_RstSockPair
1571 static stream<AxisIp4> ssIhcToIps_IpHeader (
"ssIhcToIps_IpHeader");
1572 #pragma HLS stream variable=ssIhcToIps_IpHeader depth=32
1573 #pragma HLS DATA_PACK variable=ssIhcToIps_IpHeader
1578 static stream<AxisPsd4> ssPhcToTss_PseudoHdr (
"ssPhcToTss_PseudoHdr");
1579 #pragma HLS stream variable=ssPhcToTss_PseudoHdr depth=32
1580 #pragma HLS DATA_PACK variable=ssPhcToTss_PseudoHdr
1585 static stream<IpAddrPair> ssSpsToIhc_IpAddrPair (
"ssSpsToIhc_IpAddrPair");
1586 #pragma HLS stream variable=ssSpsToIhc_IpAddrPair depth=4
1587 #pragma HLS DATA_PACK variable=ssSpsToIhc_IpAddrPair
1589 static stream<SocketPair> ssSpsToPhc_SockPair (
"ssSpsToPhc_SockPair");
1590 #pragma HLS stream variable=ssSpsToPhc_SockPair depth=4
1591 #pragma HLS DATA_PACK variable=ssSpsToPhc_SockPair
1596 static stream<AxisPsd4> ssTssToSca_PseudoPkt (
"ssTssToSca_PseudoPkt");
1597 #pragma HLS stream variable=ssTssToSca_PseudoPkt depth=16
1598 #pragma HLS DATA_PACK variable=ssTssToSca_PseudoPkt
1603 static stream<TcpChecksum> ssTcaToIps_TcpCsum (
"ssTcaToIps_TcpCsum");
1604 #pragma HLS stream variable=ssTcaToIps_TcpCsum depth=4
1609 static stream<AxisPsd4> ssScaToIps_PseudoPkt (
"ssScaToIps_PseudoPkt");
1610 #pragma HLS stream variable=ssScaToIps_PseudoPkt depth=256
1611 #pragma HLS DATA_PACK variable=ssScaToIps_PseudoPkt
1613 static stream<SubCSums> ssScaToTca_FourSubCsums (
"ssScaToTca_FourSubCsums");
1614 #pragma HLS stream variable=ssScaToTca_FourSubCsums depth=2
1615 #pragma HLS DATA_PACK variable=ssScaToTca_FourSubCsums
1620 static stream<FlagBool> ssMrdToTss_SplitMemAcc (
"ssMrdToTss_SplitMemAcc");
1621 #pragma HLS stream variable=ssMrdToTss_SplitMemAcc depth=32
1634 soTIm_SetProbeTimer,
1635 ssMdlToIhc_TcpDatLen,
1637 ssMdlToMrd_BufferRdCmd,
1638 soSLc_ReverseLkpReq,
1639 ssMdlToSpS_IsLookup,
1640 ssMdlToSps_RstSockPair,
1644 ssMdlToMrd_BufferRdCmd,
1646 ssMrdToTss_SplitMemAcc);
1649 siSLc_ReverseLkpRep,
1650 ssMdlToSps_RstSockPair,
1651 ssMdlToSpS_IsLookup,
1652 ssSpsToIhc_IpAddrPair,
1653 ssSpsToPhc_SockPair);
1656 ssMdlToIhc_TcpDatLen,
1657 ssSpsToIhc_IpAddrPair,
1658 ssIhcToIps_IpHeader);
1661 ssIhcToIps_IpHeader,
1662 ssScaToIps_PseudoPkt,
1668 ssSpsToPhc_SockPair,
1669 ssPhcToTss_PseudoHdr);
1672 ssPhcToTss_PseudoHdr,
1674 ssTssToSca_PseudoPkt,
1675 ssMrdToTss_SplitMemAcc);
1678 ssTssToSca_PseudoPkt,
1679 ssScaToIps_PseudoPkt,
1680 ssScaToTca_FourSubCsums);
1683 ssScaToTca_FourSubCsums,
1684 ssTcaToIps_TcpCsum);
void setTcpAckNum(TcpAckNum num)
void setIp4FragOff(Ip4FragOff offset)
void setTcpSeqNum(TcpSeqNum num)
void setIp4Prot(Ip4Prot prot)
void setIp4HdrLen(Ip4HdrLen ihl)
void setTcpDstPort(TcpPort port)
void setIp4HdrCsum(Ip4HdrCsum csum)
void setTcpChecksum(TcpChecksum csum)
void setIp4DstAddr(Ip4Addr addr)
void setIp4TotalLen(Ip4TotalLen len)
void setIp4Flags(Ip4Flags flags)
void setIp4Version(Ip4Version ver)
void setTcpSrcPort(TcpPort port)
void setIp4Ident(Ip4Ident id)
void setIp4ToS(Ip4ToS tos)
void setIp4SrcAddr(Ip4Addr addr)
void setIp4TtL(Ip4TtL ttl)
void setTcpWindow(TcpWindow win)
void setTcpResBits(TcpResBits res)
void setTcpCtrlPsh(TcpCtrlBit bit)
void setTcpUrgPtr(TcpUrgPtr ptr)
void setTcpChecksum(TcpChecksum csum)
void setTcpDstPort(TcpPort port)
void setPsd4Len(Ly4Len len)
void setPsd4DstAddr(Ip4Addr addr)
void setTcpCtrlAck(TcpCtrlBit bit)
void setTcpCtrlEce(TcpCtrlBit bit)
void setTcpSrcPort(TcpPort port)
void setTcpOptKind(TcpOptKind val)
void setTcpCtrlUrg(TcpCtrlBit bit)
void setTcpCtrlSyn(TcpCtrlBit bit)
void setTcpAckNum(TcpAckNum num)
void setTcpOptMss(TcpOptMss val)
void setPsd4ResBits(Psd4Res res)
void setTcpDataOff(TcpDataOff offset)
void setTcpCtrlFin(TcpCtrlBit bit)
void setTcpCtrlRst(TcpCtrlBit bit)
void setPsd4Prot(Ip4Prot prot)
void setTcpSeqNum(TcpSeqNum num)
void setTcpCtrlNs(TcpCtrlBit bit)
void setTcpCtrlCwr(TcpCtrlBit bit)
TcpCtrlBit getTcpCtrlSyn()
void setTcpOptLen(TcpOptLen len)
void setPsd4SrcAddr(Ip4Addr addr)
void setTLast(tLast last)
LE_tKeep getLE_TKeep(int leHi=64/8-1, int leLo=0) const
LE_tData getLE_TData(int leHi=64 -1, int leLo=0) const
void setLE_TLast(LE_tLast last)
void setLE_TData(LE_tData data, int leHi=64 -1, int leLo=0)
void setLE_TKeep(LE_tKeep keep, int leHi=64/8-1, int leLo=0)
LE_tLast getLE_TLast() const
void pTcpSegStitcher(stream< AxisPsd4 > &siPhc_PseudoHdr, stream< AxisApp > &siMEM_TxP_Data, stream< AxisPsd4 > &soSca_PseudoPkt, stream< FlagBool > &siMrd_SplitSegFlag)
void pTcpChecksumAccumulator(stream< SubCSums > &siSca_FourSubCsums, stream< TcpChecksum > &soIps_TcpCsum)
TCP Checksum Accumulator (Tca)
const int cDepth_TXeToRSt_Req
const char * getEventName(EventType evType)
Returns the name of an enum-based event as a user friendly string.
void pSubChecksumAccumulators(stream< AxisPsd4 > &siTss_PseudoPkt, stream< AxisPsd4 > &soIps_PseudoPkt, stream< SubCSums > &soTca_4SubCsums)
Sub-Checksum Accumulator (Sca)
void pMetaDataLoader(stream< ExtendedEvent > &siAKd_Event, stream< SessionId > &soRSt_RxSarReq, stream< RxSarReply > &siRSt_RxSarRep, stream< TXeTxSarQuery > &soTSt_TxSarQry, stream< TXeTxSarReply > &siTSt_TxSarRep, stream< TXeReTransTimerCmd > &soTIm_ReTxTimerCmd, stream< SessionId > &soTIm_SetProbeTimer, stream< TcpDatLen > &soIhc_TcpDatLen, stream< TXeMeta > &soPhc_TxeMeta, stream< DmCmd > &soMrd_BufferRdCmd, stream< SessionId > &soSLc_ReverseLkpReq, stream< StsBool > &soSps_IsLookup, stream< LE_SocketPair > &soSps_RstSockPair, stream< SigBit > &soEVe_RxEventSig)
Meta Data Loader (Mdl)
void pIpHeaderConstructor(stream< TcpDatLen > &siMdl_TcpDatLen, stream< IpAddrPair > &siSps_IpAddrPair, stream< AxisIp4 > &soIPs_IpHeader)
IPv4 Header Constructor (Ihc)
void tx_engine(stream< ExtendedEvent > &siAKd_Event, stream< SigBit > &soEVe_RxEventSig, stream< SessionId > &soRSt_RxSarReq, stream< RxSarReply > &siRSt_RxSarRep, stream< TXeTxSarQuery > &soTSt_TxSarQry, stream< TXeTxSarReply > &siTSt_TxSarRep, stream< DmCmd > &soMEM_Txp_RdCmd, stream< AxisApp > &siMEM_TxP_Data, stream< TXeReTransTimerCmd > &soTIm_ReTxTimerCmd, stream< SessionId > &soTIm_SetProbeTimer, stream< SessionId > &soSLc_ReverseLkpReq, stream< fourTuple > &siSLc_ReverseLkpRep, stream< AxisIp4 > &soIPTX_Data)
Transmit Engine (TXe)
void pIpPktStitcher(stream< AxisIp4 > &siIhc_IpHeader, stream< AxisPsd4 > &siSca_PseudoPkt, stream< TcpChecksum > &siTca_TcpCsum, stream< AxisIp4 > &soIPTX_Data)
IPv4 Packet Stitcher (Ips)
void pPseudoHeaderConstructor(stream< TXeMeta > &siMdl_TxeMeta, stream< SocketPair > &siSps_SockPair, stream< AxisPsd4 > &soTss_PseudoHdr)
Pseudo Header Constructor (Phc)
void pTxMemoryReader(stream< DmCmd > &siMdl_BufferRdCmd, stream< DmCmd > &soMEM_TxpRdCmd, stream< FlagBool > &soTss_SplitMemAcc)
Tx Memory Reader (Mrd)
void pSocketPairSplitter(stream< fourTuple > &siSLc_ReverseLkpRsp, stream< LE_SocketPair > &siMdl_RstSockPair, stream< StsBool > &siMdl_IsLookup, stream< IpAddrPair > &soIhc_IpAddrPair, stream< SocketPair > &soPhc_SocketPair)
const int cDepth_TXeToTSt_Qry
#define assessSize(callerName, stream, streamName, depth)
A macro that checks if a stream is full.
void printAxisRaw(const char *callerName, AxisRaw chunk)
Prints an Axis raw data chunk (used for debugging).
#define printInfo(callerName, format,...)
A macro to print an information message.
ap_uint< 16 > Ip4TotalLen
#define concat3(firstCharConst, secondCharConst, thirdCharConst)
void printSockPair(const char *callerName, SocketPair sockPair)
Print a socket pair association.
#define printFatal(callerName, format,...)
A macro to print a fatal error message and exit.
: Tx Engine (TXe) of the TCP Offload Engine (TOE)
ap_uint< 32 > byteSwap32(ap_uint< 32 > inputVector)
ap_uint< 16 > byteSwap16(ap_uint< 16 > inputVector)