cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
top.vhdl
Go to the documentation of this file.
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3 -- *
4 -- * Licensed under the Apache License, Version 2.0 (the "License");
5 -- * you may not use this file except in compliance with the License.
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12 -- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 -- * See the License for the specific language governing permissions and
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16 
17 
18 -- *
19 -- * cloudFPGA
20 -- * =============================================
21 -- * Created: Apr 2019
22 -- * Authors: FAB, WEI, NGL
23 -- *
24 -- * Description:
25 -- * TOP for Themisto SRA
26 -- *
27 
28 --******************************************************************************
29 --** CONTEXT CLAUSE ** FMKU60 FLASH
30 --******************************************************************************
31 library IEEE;
32 use IEEE.std_logic_1164.all;
33 use IEEE.numeric_std.all;
34 
35 library UNISIM;
36 use UNISIM.vcomponents.all;
37 
38 --library WORK;
39 --use WORK.topFlash_pkg.all; -- Not used
40 
41 library XIL_DEFAULTLIB;
42 use XIL_DEFAULTLIB.topFMKU_pkg.all;
43 
44 
45 --******************************************************************************
46 --** ENTITY ** FMKU60 FLASH
47 --******************************************************************************
48 
49 entity topFMKU60 is
50  generic (
51  -- Synthesis parameters ----------------------
52  gBitstreamUsage : string := "flash"; -- "user" or "flash"
53  gSecurityPriviledges : string := "super"; -- "user" or "super"
54  -- Build date --------------------------------
55  gTopDateYear : stDate := 8d"00"; -- Not used w/ Xilinx parts (see USR_ACCESSE2)
56  gTopDateMonth : stDate := 8d"00"; -- Not used w/ Xilinx parts (see USR_ACCESSE2)
57  gTopDateDay : stDate := 8d"00"; -- Not used w/ Xilinx parts (see USR_ACCESSE2)
58  -- External Memory Interface (EMIF) ----------
59  gEmifAddrWidth : integer := 8;
60  gEmifDataWidth : integer := 8
61  );
62  port (
63  ------------------------------------------------------
64  -- PSOC / FPGA Configuration Interface (Fcfg)
65  -- System reset controlled by the PSoC.
66  ------------------------------------------------------
67  piPSOC_Fcfg_Rst_n : in std_ulogic;
68 
69  ------------------------------------------------------
70  -- CLKT / DRAM clocks 0 and 1 (Mem. Channels 0 and 1)
71  ------------------------------------------------------
72  piCLKT_Mem0Clk_n : in std_ulogic;
73  piCLKT_Mem0Clk_p : in std_ulogic;
74  piCLKT_Mem1Clk_n : in std_ulogic;
75  piCLKT_Mem1Clk_p : in std_ulogic;
76 
77  ------------------------------------------------------
78  -- CLKT / GTH clocks (10Ge, Sata, Gtio Interfaces)
79  ------------------------------------------------------
80  piCLKT_10GeClk_n : in std_ulogic;
81  piCLKT_10GeClk_p : in std_ulogic;
82 
83  ------------------------------------------------------
84  -- CLKT / User clocks 0 and 1 (156.25MHz, 250MHz)
85  ------------------------------------------------------
86  piCLKT_Usr0Clk_n : in std_ulogic;
87  piCLKT_Usr0Clk_p : in std_ulogic;
88  piCLKT_Usr1Clk_n : in std_ulogic;
89  piCLKT_Usr1Clk_p : in std_ulogic;
90 
91  ------------------------------------------------------
92  -- PSOC / External Memory Interface (Emif)
93  ------------------------------------------------------
94  piPSOC_Emif_Clk : in std_ulogic;
95  piPSOC_Emif_Cs_n : in std_ulogic;
96  piPSOC_Emif_We_n : in std_ulogic;
97  piPSOC_Emif_Oe_n : in std_ulogic;
98  piPSOC_Emif_AdS_n : in std_ulogic;
99  piPSOC_Emif_Addr : in std_ulogic_vector(gEmifAddrWidth-1 downto 0);
100  pioPSOC_Emif_Data : inout std_ulogic_vector(gEmifDataWidth-1 downto 0);
101 
102  ------------------------------------------------------
103  -- LED / Heart Beat Interface (Yellow LED)
104  ------------------------------------------------------
105  poLED_HeartBeat_n : out std_ulogic;
106 
107  ------------------------------------------------------
108  -- -- DDR(4) / Memory Channel 0 Interface (Mc0)
109  ------------------------------------------------------
110  pioDDR4_Mem_Mc0_DmDbi_n : inout std_ulogic_vector( 8 downto 0);
111  pioDDR4_Mem_Mc0_Dq : inout std_ulogic_vector(71 downto 0);
112  pioDDR4_Mem_Mc0_Dqs_p : inout std_ulogic_vector( 8 downto 0);
113  pioDDR4_Mem_Mc0_Dqs_n : inout std_ulogic_vector( 8 downto 0);
114  poDDR4_Mem_Mc0_Act_n : out std_ulogic;
115  poDDR4_Mem_Mc0_Adr : out std_ulogic_vector(16 downto 0);
116  poDDR4_Mem_Mc0_Ba : out std_ulogic_vector( 1 downto 0);
117  poDDR4_Mem_Mc0_Bg : out std_ulogic_vector( 1 downto 0);
118  poDDR4_Mem_Mc0_Cke : out std_ulogic;
119  poDDR4_Mem_Mc0_Odt : out std_ulogic;
120  poDDR4_Mem_Mc0_Cs_n : out std_ulogic;
121  poDDR4_Mem_Mc0_Ck_p : out std_ulogic;
122  poDDR4_Mem_Mc0_Ck_n : out std_ulogic;
123  poDDR4_Mem_Mc0_Reset_n : out std_ulogic;
124 
125  ------------------------------------------------------
126  -- DDR(4) / Memory Channel 1 Interface (Mc1)
127  ------------------------------------------------------
128  pioDDR4_Mem_Mc1_DmDbi_n : inout std_ulogic_vector( 8 downto 0);
129  pioDDR4_Mem_Mc1_Dq : inout std_ulogic_vector(71 downto 0);
130  pioDDR4_Mem_Mc1_Dqs_p : inout std_ulogic_vector( 8 downto 0);
131  pioDDR4_Mem_Mc1_Dqs_n : inout std_ulogic_vector( 8 downto 0);
132  poDDR4_Mem_Mc1_Act_n : out std_ulogic;
133  poDDR4_Mem_Mc1_Adr : out std_ulogic_vector(16 downto 0);
134  poDDR4_Mem_Mc1_Ba : out std_ulogic_vector( 1 downto 0);
135  poDDR4_Mem_Mc1_Bg : out std_ulogic_vector( 1 downto 0);
136  poDDR4_Mem_Mc1_Cke : out std_ulogic;
137  poDDR4_Mem_Mc1_Odt : out std_ulogic;
138  poDDR4_Mem_Mc1_Cs_n : out std_ulogic;
139  poDDR4_Mem_Mc1_Ck_p : out std_ulogic;
140  poDDR4_Mem_Mc1_Ck_n : out std_ulogic;
141  poDDR4_Mem_Mc1_Reset_n : out std_ulogic;
142 
143  ------------------------------------------------------
144  -- ECON / Edge Connector Interface (SPD08-200)
145  ------------------------------------------------------
146  piECON_Eth_10Ge0_n : in std_ulogic;
147  piECON_Eth_10Ge0_p : in std_ulogic;
148  poECON_Eth_10Ge0_n : out std_ulogic;
149  poECON_Eth_10Ge0_p : out std_ulogic
150 
151  );
152 
153 end topFMKU60;
154 
155 
156 --*****************************************************************************
157 --** ARCHITECTURE ** FMKU60 FLASH
158 --*****************************************************************************
159 architecture structural of topFMKU60 is
160 
161  --------------------------------------------------------
162  -- [TOP] SIGNAL DECLARATIONS
163  --------------------------------------------------------
164 
165  -- Global User Clocks ----------------------------------
166  signal sTOP_156_25Clk : std_ulogic;
167  signal sTOP_250_00Clk : std_ulogic;
168 
169  -- Global Reset ----------------------------------------
170  signal sTOP_156_25Rst_n : std_ulogic;
171  signal sTOP_156_25Rst : std_ulogic;
172 
173  -- Global Source Synchronous Clock and Reset -----------
174  signal sSHL_156_25Clk : std_ulogic;
175  signal sSHL_156_25Rst : std_ulogic;
176 
177  -- Bitstream Identification Value ----------------------
178  signal sTOP_Timestamp : stTimeStamp;
179 
180  --------------------------------------------------------
181  -- SIGNAL DECLARATIONS : [SHELL/Nts] <--> [ROLE/Nts]
182  --------------------------------------------------------
183  ---- UDP Interface ---------------------------
184  ------ Input AXI-Write Stream Interface ------
185  signal sROL_Shl_Nts0_Udp_Axis_tdata : std_ulogic_vector( 63 downto 0);
186  signal sROL_Shl_Nts0_Udp_Axis_tkeep : std_ulogic_vector( 7 downto 0);
187  signal sROL_Shl_Nts0_Udp_Axis_tlast : std_ulogic;
188  signal sROL_Shl_Nts0_Udp_Axis_tvalid : std_ulogic;
189  signal sSHL_Rol_Nts0_Udp_Axis_tready : std_ulogic;
190  ------ Output AXI-Write Stream Interface -----
191  signal sROL_Shl_Nts0_Udp_Axis_tready : std_ulogic;
192  signal sSHL_Rol_Nts0_Udp_Axis_tdata : std_ulogic_vector( 63 downto 0);
193  signal sSHL_Rol_Nts0_Udp_Axis_tkeep : std_ulogic_vector( 7 downto 0);
194  signal sSHL_Rol_Nts0_Udp_Axis_tlast : std_ulogic;
195  signal sSHL_Rol_Nts0_Udp_Axis_tvalid : std_ulogic;
196  -- Open Port vector
197  signal sROL_Nrc_Udp_Rx_ports : std_ulogic_vector( 31 downto 0);
198  -- ROLE <-> NRC Meta Interface
199  signal sROLE_Nrc_Udp_Meta_TDATA : std_ulogic_vector( 63 downto 0);
200  signal sROLE_Nrc_Udp_Meta_TVALID : std_ulogic;
201  signal sROLE_Nrc_Udp_Meta_TREADY : std_ulogic;
202  signal sROLE_Nrc_Udp_Meta_TKEEP : std_ulogic_vector( 7 downto 0);
203  signal sROLE_Nrc_Udp_Meta_TLAST : std_ulogic;
204  signal sNRC_Role_Udp_Meta_TDATA : std_ulogic_vector( 63 downto 0);
205  signal sNRC_Role_Udp_Meta_TVALID : std_ulogic;
206  signal sNRC_Role_Udp_Meta_TREADY : std_ulogic;
207  signal sNRC_Role_Udp_Meta_TKEEP : std_ulogic_vector( 7 downto 0);
208  signal sNRC_Role_Udp_Meta_TLAST : std_ulogic;
209 
210  ---- TCP Interface ---------------------------
211  ------ Input AXI-Write Stream Interface ------
212  signal sROL_Shl_Nts0_Tcp_Axis_tdata : std_ulogic_vector( 63 downto 0);
213  signal sROL_Shl_Nts0_Tcp_Axis_tkeep : std_ulogic_vector( 7 downto 0);
214  signal sROL_Shl_Nts0_Tcp_Axis_tlast : std_ulogic;
215  signal sROL_Shl_Nts0_Tcp_Axis_tvalid : std_ulogic;
216  signal sSHL_Rol_Nts0_Tcp_Axis_tready : std_ulogic;
217  ------ Output AXI-Write Stream Interface -----
218  signal sROL_Shl_Nts0_Tcp_Axis_tready : std_ulogic;
219  signal sSHL_Rol_Nts0_Tcp_Axis_tdata : std_ulogic_vector( 63 downto 0);
220  signal sSHL_Rol_Nts0_Tcp_Axis_tkeep : std_ulogic_vector( 7 downto 0);
221  signal sSHL_Rol_Nts0_Tcp_Axis_tlast : std_ulogic;
222  signal sSHL_Rol_Nts0_Tcp_Axis_tvalid : std_ulogic;
223  -- Open Port vector
224  signal sROL_Nrc_Tcp_Rx_ports : std_ulogic_vector( 31 downto 0);
225  -- ROLE <-> NRC Meta Interface
226  signal sROLE_Nrc_Tcp_Meta_TDATA : std_ulogic_vector( 63 downto 0);
227  signal sROLE_Nrc_Tcp_Meta_TVALID : std_ulogic;
228  signal sROLE_Nrc_Tcp_Meta_TREADY : std_ulogic;
229  signal sROLE_Nrc_Tcp_Meta_TKEEP : std_ulogic_vector( 7 downto 0);
230  signal sROLE_Nrc_Tcp_Meta_TLAST : std_ulogic;
231  signal sNRC_Role_Tcp_Meta_TDATA : std_ulogic_vector( 63 downto 0);
232  signal sNRC_Role_Tcp_Meta_TVALID : std_ulogic;
233  signal sNRC_Role_Tcp_Meta_TREADY : std_ulogic;
234  signal sNRC_Role_Tcp_Meta_TKEEP : std_ulogic_vector( 7 downto 0);
235  signal sNRC_Role_Tcp_Meta_TLAST : std_ulogic;
236 
237 
238 
239  --------------------------------------------------------
240  -- SIGNAL DECLARATIONS : [SHELL/Mem] <--> [ROLE/Mem]
241  --------------------------------------------------------
242  -- Memory Port #0 ------------------------------
243  ------ Stream Read Command --------------
244  signal ssROL_SHL_Mem_Mp0_RdCmd_tdata : std_ulogic_vector( 79 downto 0);
245  signal ssROL_SHL_Mem_Mp0_RdCmd_tvalid : std_ulogic;
246  signal ssROL_SHL_Mem_Mp0_RdCmd_tready : std_ulogic;
247  ------ Stream Read Status ----------------
248  signal ssSHL_ROL_Mem_Mp0_RdSts_tdata : std_ulogic_vector( 7 downto 0);
249  signal ssSHL_ROL_Mem_Mp0_RdSts_tvalid : std_ulogic;
250  signal ssSHL_ROL_Mem_Mp0_RdSts_tready : std_ulogic;
251  ------ Stream Data Output Channel --------
252  signal ssSHL_ROL_Mem_Mp0_Read_tdata : std_ulogic_vector(511 downto 0);
253  signal ssSHL_ROL_Mem_Mp0_Read_tkeep : std_ulogic_vector( 63 downto 0);
254  signal ssSHL_ROL_Mem_Mp0_Read_tlast : std_ulogic;
255  signal ssSHL_ROL_Mem_Mp0_Read_tvalid : std_ulogic;
256  signal ssSHL_ROL_Mem_Mp0_Read_tready : std_ulogic;
257  ------ Stream Write Command --------------
258  signal ssROL_SHL_Mem_Mp0_WrCmd_tdata : std_ulogic_vector( 79 downto 0);
259  signal ssROL_SHL_Mem_Mp0_WrCmd_tvalid : std_ulogic;
260  signal ssROL_SHL_Mem_Mp0_WrCmd_tready : std_ulogic;
261  ------ Stream Write Status ---------------
262  signal ssSHL_ROL_Mem_Mp0_WrSts_tdata : std_ulogic_vector( 7 downto 0);
263  signal ssSHL_ROL_Mem_Mp0_WrSts_tvalid : std_ulogic;
264  signal ssSHL_ROL_Mem_Mp0_WrSts_tready : std_ulogic;
265  ------ Stream Data Input Channel ---------
266  signal ssROL_SHL_Mem_Mp0_Write_tdata : std_ulogic_vector(511 downto 0);
267  signal ssROL_SHL_Mem_Mp0_Write_tkeep : std_ulogic_vector( 63 downto 0);
268  signal ssROL_SHL_Mem_Mp0_Write_tlast : std_ulogic;
269  signal ssROL_SHL_Mem_Mp0_Write_tvalid : std_ulogic;
270  signal ssROL_SHL_Mem_Mp0_Write_tready : std_ulogic;
271  -- Memory Port #1 ------------------------------
272  signal smROL_SHL_Mem_Mp1_AWID : std_ulogic_vector(7 downto 0);
273  signal smROL_SHL_Mem_Mp1_AWADDR : std_ulogic_vector(32 downto 0);
274  signal smROL_SHL_Mem_Mp1_AWLEN : std_ulogic_vector(7 downto 0);
275  signal smROL_SHL_Mem_Mp1_AWSIZE : std_ulogic_vector(2 downto 0);
276  signal smROL_SHL_Mem_Mp1_AWBURST : std_ulogic_vector(1 downto 0);
277  signal smROL_SHL_Mem_Mp1_AWVALID : std_ulogic;
278  signal smROL_SHL_Mem_Mp1_AWREADY : std_ulogic;
279  signal smROL_SHL_Mem_Mp1_WDATA : std_ulogic_vector(511 downto 0);
280  signal smROL_SHL_Mem_Mp1_WSTRB : std_ulogic_vector(63 downto 0);
281  signal smROL_SHL_Mem_Mp1_WLAST : std_ulogic;
282  signal smROL_SHL_Mem_Mp1_WVALID : std_ulogic;
283  signal smROL_SHL_Mem_Mp1_WREADY : std_ulogic;
284  signal smROL_SHL_Mem_Mp1_BID : std_ulogic_vector(7 downto 0);
285  signal smROL_SHL_Mem_Mp1_BRESP : std_ulogic_vector(1 downto 0);
286  signal smROL_SHL_Mem_Mp1_BVALID : std_ulogic;
287  signal smROL_SHL_Mem_Mp1_BREADY : std_ulogic;
288  signal smROL_SHL_Mem_Mp1_ARID : std_ulogic_vector(7 downto 0);
289  signal smROL_SHL_Mem_Mp1_ARADDR : std_ulogic_vector(32 downto 0);
290  signal smROL_SHL_Mem_Mp1_ARLEN : std_ulogic_vector(7 downto 0);
291  signal smROL_SHL_Mem_Mp1_ARSIZE : std_ulogic_vector(2 downto 0);
292  signal smROL_SHL_Mem_Mp1_ARBURST : std_ulogic_vector(1 downto 0);
293  signal smROL_SHL_Mem_Mp1_ARVALID : std_ulogic;
294  signal smROL_SHL_Mem_Mp1_ARREADY : std_ulogic;
295  signal smROL_SHL_Mem_Mp1_RID : std_ulogic_vector(7 downto 0);
296  signal smROL_SHL_Mem_Mp1_RDATA : std_ulogic_vector(511 downto 0);
297  signal smROL_SHL_Mem_Mp1_RRESP : std_ulogic_vector(1 downto 0);
298  signal smROL_SHL_Mem_Mp1_RLAST : std_ulogic;
299  signal smROL_SHL_Mem_Mp1_RVALID : std_ulogic;
300  signal smROL_SHL_Mem_Mp1_RREADY : std_ulogic;
301 
302 
303  --------------------------------------------------------
304  -- SIGNAL DECLARATIONS : [MMIO] <--> [ROLE]
305  --------------------------------------------------------
306  ---- [PHY_RESET] -------------------------
307  signal sSHL_ROL_Mmio_Ly7Rst : std_ulogic;
308  ---- [PHY_ENABLE] ------------------------
309  signal sSHL_ROL_Mmio_Ly7En : std_ulogic;
310  ---- DIAG_CTRL_1 -------------------------
311  signal sSHL_ROL_Mmio_Mc1_MemTestCtrl : std_ulogic_vector( 1 downto 0);
312  ---- DIAG_STAT_1 -------------------------
313  signal sROL_SHL_Mmio_Mc1_MemTestStat : std_ulogic_vector( 1 downto 0);
314  ---- CTRL_2 Register ---------------------
315  signal sSHL_ROL_Mmio_UdpEchoCtrl : std_ulogic_vector( 1 downto 0);
316  signal sSHL_ROL_Mmio_UdpPostDgmEn : std_ulogic;
317  signal sSHL_ROL_Mmio_UdpCaptDgmEn : std_ulogic;
318  signal sSHL_ROL_Mmio_TcpEchoCtrl : std_ulogic_vector( 1 downto 0);
319  signal sSHL_ROL_Mmio_TcpPostSegEn : std_ulogic;
320  signal sSHL_ROL_Mmio_TcpCaptSegEn : std_ulogic;
321  ---- APP_RDROL[0:1] ---------------------
322  signal sROL_SHL_Mmio_RdReg : std_ulogic_vector( 15 downto 0);
323  ---- APP_WRROL[0:1] ---------------------
324  signal sSHL_ROL_Mmio_WrReg : std_ulogic_vector( 15 downto 0);
325 
326  --------------------------------------------------------
327  -- SIGNAL DECLARATION : [FMC] <--> [ROLE]
328  --------------------------------------------------------
329  signal sSHL_ROL_Fmc_Rank : std_ulogic_vector( 31 downto 0);
330  signal sSHL_ROL_Fmc_Size : std_ulogic_vector( 31 downto 0);
331 
332  signal sROL_reset_combinded : std_ulogic;
333 
334  --===========================================================================
335  --== COMPONENT DECLARATIONS
336  --===========================================================================
337 
338  -- [INFO] The SHELL component is declared in the corresponding TOP package.
339  -- not this time
340  -- to declare the component in the pkg seems not to work for Verilog or .dcp modules
341  component Shell_Themisto
342  generic (
343  gSecurityPriviledges : string := "super"; -- Can be "user" or "super"
344  gBitstreamUsage : string := "flash"; -- Can be "user" or "flash"
345  gMmioAddrWidth : integer := 8; -- Default is 8-bits
346  gMmioDataWidth : integer := 8 -- Default is 8-bits
347  );
348  port (
349  ------------------------------------------------------
350  -- TOP / Input Clocks and Resets from topFMKU60
351  ------------------------------------------------------
352  piTOP_156_25Rst : in std_ulogic;
353  piTOP_156_25Clk : in std_ulogic;
354 
355  ------------------------------------------------------
356  -- TOP / Bitstream Identification
357  ------------------------------------------------------
358  piTOP_Timestamp : in std_ulogic_vector( 31 downto 0);
359 
360  ------------------------------------------------------
361  -- CLKT / Clock Tree Interface
362  ------------------------------------------------------
363  piCLKT_Mem0Clk_n : in std_ulogic;
364  piCLKT_Mem0Clk_p : in std_ulogic;
365  piCLKT_Mem1Clk_n : in std_ulogic;
366  piCLKT_Mem1Clk_p : in std_ulogic;
367  piCLKT_10GeClk_n : in std_ulogic;
368  piCLKT_10GeClk_p : in std_ulogic;
369 
370  ------------------------------------------------------
371  -- PSOC / External Memory Interface (Emif)
372  ------------------------------------------------------
373  piPSOC_Emif_Clk : in std_ulogic;
374  piPSOC_Emif_Cs_n : in std_ulogic;
375  piPSOC_Emif_We_n : in std_ulogic;
376  piPSOC_Emif_Oe_n : in std_ulogic;
377  piPSOC_Emif_AdS_n : in std_ulogic;
378  piPSOC_Emif_Addr : in std_ulogic_vector(gMmioAddrWidth-1 downto 0);
379  pioPSOC_Emif_Data : inout std_ulogic_vector(gMmioDataWidth-1 downto 0);
380 
381  ------------------------------------------------------
382  -- LED / Heart Beat Interface (Yellow LED)
383  ------------------------------------------------------
384  poLED_HeartBeat_n : out std_ulogic;
385 
386  ------------------------------------------------------
387  -- DDR4 / Memory Channel 0 Interface (Mc0)
388  ------------------------------------------------------
389  pioDDR4_Mem_Mc0_DmDbi_n : inout std_ulogic_vector( 8 downto 0);
390  pioDDR4_Mem_Mc0_Dq : inout std_ulogic_vector( 71 downto 0);
391  pioDDR4_Mem_Mc0_Dqs_n : inout std_ulogic_vector( 8 downto 0);
392  pioDDR4_Mem_Mc0_Dqs_p : inout std_ulogic_vector( 8 downto 0);
393  poDDR4_Mem_Mc0_Act_n : out std_ulogic;
394  poDDR4_Mem_Mc0_Adr : out std_ulogic_vector( 16 downto 0);
395  poDDR4_Mem_Mc0_Ba : out std_ulogic_vector( 1 downto 0);
396  poDDR4_Mem_Mc0_Bg : out std_ulogic_vector( 1 downto 0);
397  poDDR4_Mem_Mc0_Cke : out std_ulogic;
398  poDDR4_Mem_Mc0_Odt : out std_ulogic;
399  poDDR4_Mem_Mc0_Cs_n : out std_ulogic;
400  poDDR4_Mem_Mc0_Ck_n : out std_ulogic;
401  poDDR4_Mem_Mc0_Ck_p : out std_ulogic;
402  poDDR4_Mem_Mc0_Reset_n : out std_ulogic;
403 
404  ------------------------------------------------------
405  -- DDR4 / Memory Channel 1 Interface (Mc1)
406  ------------------------------------------------------
407  pioDDR4_Mem_Mc1_DmDbi_n : inout std_ulogic_vector( 8 downto 0);
408  pioDDR4_Mem_Mc1_Dq : inout std_ulogic_vector( 71 downto 0);
409  pioDDR4_Mem_Mc1_Dqs_n : inout std_ulogic_vector( 8 downto 0);
410  pioDDR4_Mem_Mc1_Dqs_p : inout std_ulogic_vector( 8 downto 0);
411  poDDR4_Mem_Mc1_Act_n : out std_ulogic;
412  poDDR4_Mem_Mc1_Adr : out std_ulogic_vector( 16 downto 0);
413  poDDR4_Mem_Mc1_Ba : out std_ulogic_vector( 1 downto 0);
414  poDDR4_Mem_Mc1_Bg : out std_ulogic_vector( 1 downto 0);
415  poDDR4_Mem_Mc1_Cke : out std_ulogic;
416  poDDR4_Mem_Mc1_Odt : out std_ulogic;
417  poDDR4_Mem_Mc1_Cs_n : out std_ulogic;
418  poDDR4_Mem_Mc1_Ck_n : out std_ulogic;
419  poDDR4_Mem_Mc1_Ck_p : out std_ulogic;
420  poDDR4_Mem_Mc1_Reset_n : out std_ulogic;
421 
422  ------------------------------------------------------
423  -- ECON / Edge Connector Interface (SPD08-200)
424  ------------------------------------------------------
425  piECON_Eth_10Ge0_n : in std_ulogic;
426  piECON_Eth_10Ge0_p : in std_ulogic;
427  poECON_Eth_10Ge0_n : out std_ulogic;
428  poECON_Eth_10Ge0_p : out std_ulogic;
429 
430  ------------------------------------------------------
431  -- ROLE / Output Clock and Reset Interfaces
432  ------------------------------------------------------
433  poROL_156_25Clk : out std_ulogic;
434  poROL_156_25Rst : out std_ulogic;
435 
436  ------------------------------------------------------
437  -- ROLE / Nts / Udp Interface
438  ------------------------------------------------------
439  -- Input AXI-Write Stream Interface ----------
440  siROL_Nts_Udp_Data_tdata : in std_ulogic_vector( 63 downto 0);
441  siROL_Nts_Udp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
442  siROL_Nts_Udp_Data_tlast : in std_ulogic;
443  siROL_Nts_Udp_Data_tvalid : in std_ulogic;
444  siROL_Nts_Udp_Data_tready : out std_ulogic;
445  -- Output AXI-Write Stream Interface ---------
446  soROL_Nts_Udp_Data_tdata : out std_ulogic_vector( 63 downto 0);
447  soROL_Nts_Udp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
448  soROL_Nts_Udp_Data_tlast : out std_ulogic;
449  soROL_Nts_Udp_Data_tvalid : out std_ulogic;
450  soROL_Nts_Udp_Data_tready : in std_ulogic;
451  -- Open Port vector
452  piROL_Nrc_Udp_Rx_ports : in std_ulogic_vector( 31 downto 0);
453  -- ROLE <-> NRC Meta Interface
454  siROLE_Nrc_Udp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
455  siROLE_Nrc_Udp_Meta_TVALID : in std_ulogic;
456  siROLE_Nrc_Udp_Meta_TREADY : out std_ulogic;
457  siROLE_Nrc_Udp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
458  siROLE_Nrc_Udp_Meta_TLAST : in std_ulogic;
459  soNRC_Role_Udp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
460  soNRC_Role_Udp_Meta_TVALID : out std_ulogic;
461  soNRC_Role_Udp_Meta_TREADY : in std_ulogic;
462  soNRC_Role_Udp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
463  soNRC_Role_Udp_Meta_TLAST : out std_ulogic;
464 
465  ------------------------------------------------------
466  -- ROLE / Shl / Nts0 / Tcp Interfaces
467  ------------------------------------------------------
468  -- Input AXI-Write Stream Interface ----------
469  siROL_Nts_Tcp_Data_tdata : in std_ulogic_vector( 63 downto 0);
470  siROL_Nts_Tcp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
471  siROL_Nts_Tcp_Data_tlast : in std_ulogic;
472  siROL_Nts_Tcp_Data_tvalid : in std_ulogic;
473  siROL_Nts_Tcp_Data_tready : out std_ulogic;
474  -- Output AXI-Write Stream Interface ---------
475  soROL_Nts_Tcp_Data_tdata : out std_ulogic_vector( 63 downto 0);
476  soROL_Nts_Tcp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
477  soROL_Nts_Tcp_Data_tlast : out std_ulogic;
478  soROL_Nts_Tcp_Data_tvalid : out std_ulogic;
479  soROL_Nts_Tcp_Data_tready : in std_ulogic;
480  -- Open Port vector
481  piROL_Nrc_Tcp_Rx_ports : in std_ulogic_vector( 31 downto 0);
482  -- ROLE <-> NRC Meta Interface
483  siROLE_Nrc_Tcp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
484  siROLE_Nrc_Tcp_Meta_TVALID : in std_ulogic;
485  siROLE_Nrc_Tcp_Meta_TREADY : out std_ulogic;
486  siROLE_Nrc_Tcp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
487  siROLE_Nrc_Tcp_Meta_TLAST : in std_ulogic;
488  soNRC_Role_Tcp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
489  soNRC_Role_Tcp_Meta_TVALID : out std_ulogic;
490  soNRC_Role_Tcp_Meta_TREADY : in std_ulogic;
491  soNRC_Role_Tcp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
492  soNRC_Role_Tcp_Meta_TLAST : out std_ulogic;
493 
494  ------------------------------------------------------
495  -- ROLE / Mem / Mp0 Interface
496  ------------------------------------------------------
497  -- Memory Port #0 / S2MM-AXIS ------------------
498  ---- Stream Read Command -----------------
499  siROL_Mem_Mp0_RdCmd_tdata : in std_ulogic_vector( 79 downto 0);
500  siROL_Mem_Mp0_RdCmd_tvalid : in std_ulogic;
501  siROL_Mem_Mp0_RdCmd_tready : out std_ulogic;
502  ---- Stream Read Status ------------------
503  soROL_Mem_Mp0_RdSts_tdata : out std_ulogic_vector( 7 downto 0);
504  soROL_Mem_Mp0_RdSts_tvalid : out std_ulogic;
505  soROL_Mem_Mp0_RdSts_tready : in std_ulogic;
506  ---- Stream Data Output Channel ----------
507  soROL_Mem_Mp0_Read_tdata : out std_ulogic_vector(511 downto 0);
508  soROL_Mem_Mp0_Read_tkeep : out std_ulogic_vector( 63 downto 0);
509  soROL_Mem_Mp0_Read_tlast : out std_ulogic;
510  soROL_Mem_Mp0_Read_tvalid : out std_ulogic;
511  soROL_Mem_Mp0_Read_tready : in std_ulogic;
512  ---- Stream Write Command ----------------
513  siROL_Mem_Mp0_WrCmd_tdata : in std_ulogic_vector( 79 downto 0);
514  siROL_Mem_Mp0_WrCmd_tvalid : in std_ulogic;
515  siROL_Mem_Mp0_WrCmd_tready : out std_ulogic;
516  ---- Stream Write Status -----------------
517  soROL_Mem_Mp0_WrSts_tvalid : out std_ulogic;
518  soROL_Mem_Mp0_WrSts_tdata : out std_ulogic_vector( 7 downto 0);
519  soROL_Mem_Mp0_WrSts_tready : in std_ulogic;
520  ---- Stream Data Input Channel -----------
521  siROL_Mem_Mp0_Write_tdata : in std_ulogic_vector(511 downto 0);
522  siROL_Mem_Mp0_Write_tkeep : in std_ulogic_vector( 63 downto 0);
523  siROL_Mem_Mp0_Write_tlast : in std_ulogic;
524  siROL_Mem_Mp0_Write_tvalid : in std_ulogic;
525  siROL_Mem_Mp0_Write_tready : out std_ulogic;
526 
527  ------------------------------------------------------
528  -- ROLE / Mem / Mp1 Interface
529  ------------------------------------------------------
530  miROL_Mem_Mp1_AWID : in std_ulogic_vector(7 downto 0);
531  miROL_Mem_Mp1_AWADDR : in std_ulogic_vector(32 downto 0);
532  miROL_Mem_Mp1_AWLEN : in std_ulogic_vector(7 downto 0);
533  miROL_Mem_Mp1_AWSIZE : in std_ulogic_vector(2 downto 0);
534  miROL_Mem_Mp1_AWBURST : in std_ulogic_vector(1 downto 0);
535  miROL_Mem_Mp1_AWVALID : in std_ulogic;
536  miROL_Mem_Mp1_AWREADY : out std_ulogic;
537  miROL_Mem_Mp1_WDATA : in std_ulogic_vector(511 downto 0);
538  miROL_Mem_Mp1_WSTRB : in std_ulogic_vector(63 downto 0);
539  miROL_Mem_Mp1_WLAST : in std_ulogic;
540  miROL_Mem_Mp1_WVALID : in std_ulogic;
541  miROL_Mem_Mp1_WREADY : out std_ulogic;
542  miROL_Mem_Mp1_BID : out std_ulogic_vector(7 downto 0);
543  miROL_Mem_Mp1_BRESP : out std_ulogic_vector(1 downto 0);
544  miROL_Mem_Mp1_BVALID : out std_ulogic;
545  miROL_Mem_Mp1_BREADY : in std_ulogic;
546  miROL_Mem_Mp1_ARID : in std_ulogic_vector(7 downto 0);
547  miROL_Mem_Mp1_ARADDR : in std_ulogic_vector(32 downto 0);
548  miROL_Mem_Mp1_ARLEN : in std_ulogic_vector(7 downto 0);
549  miROL_Mem_Mp1_ARSIZE : in std_ulogic_vector(2 downto 0);
550  miROL_Mem_Mp1_ARBURST : in std_ulogic_vector(1 downto 0);
551  miROL_Mem_Mp1_ARVALID : in std_ulogic;
552  miROL_Mem_Mp1_ARREADY : out std_ulogic;
553  miROL_Mem_Mp1_RID : out std_ulogic_vector(7 downto 0);
554  miROL_Mem_Mp1_RDATA : out std_ulogic_vector(511 downto 0);
555  miROL_Mem_Mp1_RRESP : out std_ulogic_vector(1 downto 0);
556  miROL_Mem_Mp1_RLAST : out std_ulogic;
557  miROL_Mem_Mp1_RVALID : out std_ulogic;
558  miROL_Mem_Mp1_RREADY : in std_ulogic;
559 
560  --------------------------------------------------------
561  -- ROLE / Mmio / AppFlash Interface
562  --------------------------------------------------------
563  ---- PHY_RESET --------------------
564  poROL_Mmio_Ly7Rst : out std_ulogic;
565  ---- PHY_ENABLE -------------------
566  poROL_Mmio_Ly7En : out std_ulogic;
567  ---- DIAG_CTRL_1 ------------------
568  poROL_Mmio_Mc1_MemTestCtrl : out std_ulogic_vector( 1 downto 0);
569  ---- DIAG_STAT_1 -----------------
570  piROL_Mmio_Mc1_MemTestStat : in std_ulogic_vector( 1 downto 0); -- [FIXME: Why 7:0 and not 7:6 ? ]
571  ---- DIAG_CTRL_2 ------------------
572  poROL_Mmio_UdpEchoCtrl : out std_ulogic_vector( 1 downto 0);
573  poROL_Mmio_UdpPostDgmEn : out std_ulogic;
574  poROL_Mmio_UdpCaptDgmEn : out std_ulogic;
575  poROL_Mmio_TcpEchoCtrl : out std_ulogic_vector( 1 downto 0);
576  poROL_Mmio_TcpPostSegEn : out std_ulogic;
577  poROL_Mmio_TcpCaptSegEn : out std_ulogic;
578  ---- APP_RDROL --------------------
579  piROL_Mmio_RdReg : in std_ulogic_vector( 15 downto 0);
580  ---- APP_WRROL --------------------
581  poROL_Mmio_WrReg : out std_ulogic_vector( 15 downto 0);
582 
583  --------------------------------------------------------
584  -- ROLE / Fmc / Management Interface
585  --------------------------------------------------------
586  poROL_Fmc_Rank : out std_logic_vector(31 downto 0);
587  poROL_Fmc_Size : out std_logic_vector(31 downto 0);
588 
589  poVoid : out std_ulogic
590 
591  );
592  end component Shell_Themisto;
593 
594 
595  -- [INFO] The ROLE component is declared in the corresponding TOP package.
596  -- not this time
597  -- to declare the component in the pkg seems not to work for Verilog or .dcp modules
598  component Role_Themisto
599  port (
600 
601  ------------------------------------------------------
602  -- TOP / Global Input Clock and Reset Interface
603  ------------------------------------------------------
604  piSHL_156_25Clk : in std_ulogic;
605  piSHL_156_25Rst : in std_ulogic;
606  -- LY7 Enable and Reset
607  piMMIO_Ly7_Rst : in std_ulogic;
608  piMMIO_Ly7_En : in std_ulogic;
609 
610  ------------------------------------------------------
611  -- SHELL / Role / Nts0 / Udp Interface
612  ------------------------------------------------------
613  ---- Input AXI-Write Stream Interface ----------
614  siNRC_Udp_Data_tdata : in std_ulogic_vector( 63 downto 0);
615  siNRC_Udp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
616  siNRC_Udp_Data_tvalid : in std_ulogic;
617  siNRC_Udp_Data_tlast : in std_ulogic;
618  siNRC_Udp_Data_tready : out std_ulogic;
619  ---- Output AXI-Write Stream Interface ---------
620  soNRC_Udp_Data_tdata : out std_ulogic_vector( 63 downto 0);
621  soNRC_Udp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
622  soNRC_Udp_Data_tvalid : out std_ulogic;
623  soNRC_Udp_Data_tlast : out std_ulogic;
624  soNRC_Udp_Data_tready : in std_ulogic;
625  -- Open Port vector
626  poROL_Nrc_Udp_Rx_ports : out std_ulogic_vector( 31 downto 0);
627  -- ROLE <-> NRC Meta Interface
628  soROLE_Nrc_Udp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
629  soROLE_Nrc_Udp_Meta_TVALID : out std_ulogic;
630  soROLE_Nrc_Udp_Meta_TREADY : in std_ulogic;
631  soROLE_Nrc_Udp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
632  soROLE_Nrc_Udp_Meta_TLAST : out std_ulogic;
633  siNRC_Role_Udp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
634  siNRC_Role_Udp_Meta_TVALID : in std_ulogic;
635  siNRC_Role_Udp_Meta_TREADY : out std_ulogic;
636  siNRC_Role_Udp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
637  siNRC_Role_Udp_Meta_TLAST : in std_ulogic;
638 
639  ------------------------------------------------------
640  -- SHELL / Role / Nts0 / Tcp Interface
641  ------------------------------------------------------
642  ---- Input AXI-Write Stream Interface ----------
643  siNRC_Tcp_Data_tdata : in std_ulogic_vector( 63 downto 0);
644  siNRC_Tcp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
645  siNRC_Tcp_Data_tvalid : in std_ulogic;
646  siNRC_Tcp_Data_tlast : in std_ulogic;
647  siNRC_Tcp_Data_tready : out std_ulogic;
648  ---- Output AXI-Write Stream Interface ---------
649  soNRC_Tcp_Data_tdata : out std_ulogic_vector( 63 downto 0);
650  soNRC_Tcp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
651  soNRC_Tcp_Data_tvalid : out std_ulogic;
652  soNRC_Tcp_Data_tlast : out std_ulogic;
653  soNRC_Tcp_Data_tready : in std_ulogic;
654  -- Open Port vector
655  poROL_Nrc_Tcp_Rx_ports : out std_ulogic_vector( 31 downto 0);
656  -- ROLE <-> NRC Meta Interface
657  soROLE_Nrc_Tcp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
658  soROLE_Nrc_Tcp_Meta_TVALID : out std_ulogic;
659  soROLE_Nrc_Tcp_Meta_TREADY : in std_ulogic;
660  soROLE_Nrc_Tcp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
661  soROLE_Nrc_Tcp_Meta_TLAST : out std_ulogic;
662  siNRC_Role_Tcp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
663  siNRC_Role_Tcp_Meta_TVALID : in std_ulogic;
664  siNRC_Role_Tcp_Meta_TREADY : out std_ulogic;
665  siNRC_Role_Tcp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
666  siNRC_Role_Tcp_Meta_TLAST : in std_ulogic;
667 
668 
669  ------------------------------------------------------
670  -- SHELL / Mem / Mp0 Interface
671  ------------------------------------------------------
672  ---- Memory Port #0 / S2MM-AXIS -------------
673  ------ Stream Read Command ---------
674  soMEM_Mp0_RdCmd_tdata : out std_ulogic_vector( 79 downto 0);
675  soMEM_Mp0_RdCmd_tvalid : out std_ulogic;
676  soMEM_Mp0_RdCmd_tready : in std_ulogic;
677  ------ Stream Read Status ----------
678  siMEM_Mp0_RdSts_tdata : in std_ulogic_vector( 7 downto 0);
679  siMEM_Mp0_RdSts_tvalid : in std_ulogic;
680  siMEM_Mp0_RdSts_tready : out std_ulogic;
681  ------ Stream Data Input Channel ---
682  siMEM_Mp0_Read_tdata : in std_ulogic_vector(511 downto 0);
683  siMEM_Mp0_Read_tkeep : in std_ulogic_vector( 63 downto 0);
684  siMEM_Mp0_Read_tlast : in std_ulogic;
685  siMEM_Mp0_Read_tvalid : in std_ulogic;
686  siMEM_Mp0_Read_tready : out std_ulogic;
687  ------ Stream Write Command --------
688  soMEM_Mp0_WrCmd_tdata : out std_ulogic_vector( 79 downto 0);
689  soMEM_Mp0_WrCmd_tvalid : out std_ulogic;
690  soMEM_Mp0_WrCmd_tready : in std_ulogic;
691  ------ Stream Write Status ---------
692  siMEM_Mp0_WrSts_tvalid : in std_ulogic;
693  siMEM_Mp0_WrSts_tdata : in std_ulogic_vector( 7 downto 0);
694  siMEM_Mp0_WrSts_tready : out std_ulogic;
695  ------ Stream Data Output Channel --
696  soMEM_Mp0_Write_tdata : out std_ulogic_vector(511 downto 0);
697  soMEM_Mp0_Write_tkeep : out std_ulogic_vector( 63 downto 0);
698  soMEM_Mp0_Write_tlast : out std_ulogic;
699  soMEM_Mp0_Write_tvalid : out std_ulogic;
700  soMEM_Mp0_Write_tready : in std_ulogic;
701 
702  ------------------------------------------------------
703  -- SHELL / Mem / Mp1 Interface
704  ------------------------------------------------------
705  moMEM_Mp1_AWID : out std_ulogic_vector(7 downto 0);
706  moMEM_Mp1_AWADDR : out std_ulogic_vector(32 downto 0);
707  moMEM_Mp1_AWLEN : out std_ulogic_vector(7 downto 0);
708  moMEM_Mp1_AWSIZE : out std_ulogic_vector(2 downto 0);
709  moMEM_Mp1_AWBURST : out std_ulogic_vector(1 downto 0);
710  moMEM_Mp1_AWVALID : out std_ulogic;
711  moMEM_Mp1_AWREADY : in std_ulogic;
712  moMEM_Mp1_WDATA : out std_ulogic_vector(511 downto 0);
713  moMEM_Mp1_WSTRB : out std_ulogic_vector(63 downto 0);
714  moMEM_Mp1_WLAST : out std_ulogic;
715  moMEM_Mp1_WVALID : out std_ulogic;
716  moMEM_Mp1_WREADY : in std_ulogic;
717  moMEM_Mp1_BID : in std_ulogic_vector(7 downto 0);
718  moMEM_Mp1_BRESP : in std_ulogic_vector(1 downto 0);
719  moMEM_Mp1_BVALID : in std_ulogic;
720  moMEM_Mp1_BREADY : out std_ulogic;
721  moMEM_Mp1_ARID : out std_ulogic_vector(7 downto 0);
722  moMEM_Mp1_ARADDR : out std_ulogic_vector(32 downto 0);
723  moMEM_Mp1_ARLEN : out std_ulogic_vector(7 downto 0);
724  moMEM_Mp1_ARSIZE : out std_ulogic_vector(2 downto 0);
725  moMEM_Mp1_ARBURST : out std_ulogic_vector(1 downto 0);
726  moMEM_Mp1_ARVALID : out std_ulogic;
727  moMEM_Mp1_ARREADY : in std_ulogic;
728  moMEM_Mp1_RID : in std_ulogic_vector(7 downto 0);
729  moMEM_Mp1_RDATA : in std_ulogic_vector(511 downto 0);
730  moMEM_Mp1_RRESP : in std_ulogic_vector(1 downto 0);
731  moMEM_Mp1_RLAST : in std_ulogic;
732  moMEM_Mp1_RVALID : in std_ulogic;
733  moMEM_Mp1_RREADY : out std_ulogic;
734 
735  -- leave declarations here for higher privileged Roles?
736  ----------------------------------------------------------
737  ---- SHELL / Mmio / AppFlash Interface
738  ----------------------------------------------------------
739  ------ [DIAG_CTRL_1] -----------------
740  --piSHL_Mmio_Mc1_MemTestCtrl : in std_ulogic_vector( 1 downto 0);
741  ------ [DIAG_STAT_1] -----------------
742  --poSHL_Mmio_Mc1_MemTestStat : out std_ulogic_vector( 1 downto 0);
743  ------ [DIAG_CTRL_2] -----------------
744  --piSHL_Mmio_UdpEchoCtrl : in std_ulogic_vector( 1 downto 0);
745  --piSHL_Mmio_UdpPostDgmEn : in std_ulogic;
746  --piSHL_Mmio_UdpCaptDgmEn : in std_ulogic;
747  --piSHL_Mmio_TcpEchoCtrl : in std_ulogic_vector( 1 downto 0);
748  --piSHL_Mmio_TcpPostSegEn : in std_ulogic;
749  --piSHL_Mmio_TcpCaptSegEn : in std_ulogic;
750  ---- [APP_RDROL] -------------------
751  poSHL_Mmio_RdReg : out std_ulogic_vector( 15 downto 0);
752  ----- [APP_WRROL] --------------------
753  --piSHL_Mmio_WrReg : in std_ulogic_vector( 15 downto 0);
754 
755  --------------------------------------------------------
756  -- TOP : Secondary Clock (Asynchronous)
757  --------------------------------------------------------
758  piTOP_250_00Clk : in std_ulogic; -- Freerunning
759 
760  ------------------------------------------------
761  -- FMC Interface
762  ------------------------------------------------
763  piFMC_ROLE_rank : in std_logic_vector(31 downto 0);
764  piFMC_ROLE_size : in std_logic_vector(31 downto 0);
765 
766  ------------------------------------------------
767  -- DEBUG PORTS (see UG909)
768  ------------------------------------------------
769  dpBSCAN_drck : IN std_logic := '0';
770  dpBSCAN_shift : IN std_logic := '0';
771  dpBSCAN_tdi : IN std_logic := '0';
772  dpBSCAN_update : IN std_logic := '0';
773  dpBSCAN_sel : IN std_logic := '0';
774  dpBSCAN_tdo : OUT std_logic;
775  dpBSCAN_tms : IN std_logic := '0';
776  dpBSCAN_tck : IN std_logic := '0';
777  dpBSCAN_runtest : IN std_logic := '0';
778  dpBSCAN_reset : IN std_logic := '0';
779  dpBSCAN_capture : IN std_logic := '0';
780  dpBSCAN_bscanid_en : IN std_logic := '0';
781 
782  poVoid : out std_ulogic
783  );
784  end component Role_Themisto;
785 
786 begin
787 
788  --===========================================================================
789  --== INST: INPUT USER CLOCK BUFFERS
790  --===========================================================================
791  CLKBUF0 : IBUFDS
792  generic map (
793  DQS_BIAS => "FALSE" -- (FALSE, TRUE)
794  )
795  port map (
796  O => sTOP_156_25Clk,
797  I => piCLKT_Usr0Clk_p,
798  IB => piCLKT_Usr0Clk_n
799  );
800 
801  CLKBUF1 : IBUFDS
802  generic map (
803  DQS_BIAS => "FALSE" -- (FALSE, TRUE)
804  )
805  port map (
806  O => sTOP_250_00Clk,
807  I => piCLKT_Usr1Clk_p,
808  IB => piCLKT_Usr1Clk_n
809  );
810 
811  --===========================================================================
812  --== INST: METASTABILITY HARDENED BLOCK FOR THE SYSTEM RESET (Active high)
813  --== [INFO] Note that we instantiate 2 or 3 library primitives rather than
814  --== a VHDL process because it makes it easier to apply the "ASYNC_REG"
815  --== property to those instances.
816  --===========================================================================
817  TOP_META_RST : HARD_SYNC
818  generic map (
819  INIT => '0', -- Initial values, '0', '1'
820  IS_CLK_INVERTED => '0', -- Programmable inversion on CLK input
821  LATENCY => 2 -- 2-3
822  )
823  port map (
824  CLK => sTOP_156_25Clk,
825  DIN => piPSOC_Fcfg_Rst_n,
826  DOUT => sTOP_156_25Rst_n
827  );
828  sTOP_156_25Rst <= not sTOP_156_25Rst_n;
829 
830  --===========================================================================
831  --== INST: BITSTREAM IDENTIFICATION BLOCK with USR_ACCESSE2 PRIMITIVE
832  --== [INFO] This component provides direct FPGA logic access to the 32-bit
833  --== value stored by the FPGA bitstream. We use this register to retrieve
834  --== an accurate timestamp corresponding to the date of the bitstream
835  --== generation (note that we don't track the sminiutes and seconds).
836  --============================================================================
837  TOP_TIMESTAMP : USR_ACCESSE2
838  port map (
839  CFGCLK => open, -- Not used in the static mode
840  DATA => sTOP_Timestamp, -- 32-bit configuration data
841  DATAVALID => open -- Not used in the static mode
842  );
843 
844  --==========================================================================
845  --== INST: SHELL FOR FMKU60
846  --== This version of the SHELL has the following user interfaces:
847  --== - one UDP, one TCP, and two MemoryPort interfaces.
848  --==========================================================================
849  SHELL : Shell_Themisto
850  generic map (
851  gSecurityPriviledges => "super",
852  gBitstreamUsage => "flash",
853  gMmioAddrWidth => gEmifAddrWidth,
854  gMmioDataWidth => gEmifDataWidth
855  )
856  port map (
857  ------------------------------------------------------
858  -- TOP / Input Clocks and Resets from topFMKU60
859  ------------------------------------------------------
860  piTOP_156_25Rst => sTOP_156_25Rst,
861  piTOP_156_25Clk => sTOP_156_25Clk,
862 
863  ------------------------------------------------------
864  -- TOP / Bitstream Identification
865  ------------------------------------------------------
866  piTOP_Timestamp => sTOP_Timestamp,
867 
868  ------------------------------------------------------
869  -- CLKT / Clock Tree Interface
870  ------------------------------------------------------
871  piCLKT_Mem0Clk_n => piCLKT_Mem0Clk_n,
872  piCLKT_Mem0Clk_p => piCLKT_Mem0Clk_p,
873  piCLKT_Mem1Clk_n => piCLKT_Mem1Clk_n,
874  piCLKT_Mem1Clk_p => piCLKT_Mem1Clk_p,
875  piCLKT_10GeClk_n => piCLKT_10GeClk_n,
876  piCLKT_10GeClk_p => piCLKT_10GeClk_p,
877 
878  ------------------------------------------------------
879  -- PSOC / External Memory Interface => Emif)
880  ------------------------------------------------------
881  piPSOC_Emif_Clk => piPSOC_Emif_Clk,
882  piPSOC_Emif_Cs_n => piPSOC_Emif_Cs_n,
883  piPSOC_Emif_We_n => piPSOC_Emif_We_n,
884  piPSOC_Emif_Oe_n => piPSOC_Emif_Oe_n,
885  piPSOC_Emif_AdS_n => piPSOC_Emif_AdS_n,
886  piPSOC_Emif_Addr => piPSOC_Emif_Addr,
887  pioPSOC_Emif_Data => pioPSOC_Emif_Data,
888 
889  ------------------------------------------------------
890  -- LED / Shl / Heart Beat Interface => Yellow LED)
891  ------------------------------------------------------
892  poLED_HeartBeat_n => poLED_HeartBeat_n,
893 
894  ------------------------------------------------------
895  -- DDR4 / Memory Channel 0 Interface => (Mc0)
896  ------------------------------------------------------
897  pioDDR4_Mem_Mc0_DmDbi_n => pioDDR4_Mem_Mc0_DmDbi_n,
898  pioDDR4_Mem_Mc0_Dq => pioDDR4_Mem_Mc0_Dq,
899  pioDDR4_Mem_Mc0_Dqs_n => pioDDR4_Mem_Mc0_Dqs_n,
900  pioDDR4_Mem_Mc0_Dqs_p => pioDDR4_Mem_Mc0_Dqs_p,
901  poDDR4_Mem_Mc0_Act_n => poDDR4_Mem_Mc0_Act_n,
902  poDDR4_Mem_Mc0_Adr => poDDR4_Mem_Mc0_Adr,
903  poDDR4_Mem_Mc0_Ba => poDDR4_Mem_Mc0_Ba,
904  poDDR4_Mem_Mc0_Bg => poDDR4_Mem_Mc0_Bg,
905  poDDR4_Mem_Mc0_Cke => poDDR4_Mem_Mc0_Cke,
906  poDDR4_Mem_Mc0_Odt => poDDR4_Mem_Mc0_Odt,
907  poDDR4_Mem_Mc0_Cs_n => poDDR4_Mem_Mc0_Cs_n,
908  poDDR4_Mem_Mc0_Ck_n => poDDR4_Mem_Mc0_Ck_n,
909  poDDR4_Mem_Mc0_Ck_p => poDDR4_Mem_Mc0_Ck_p,
910  poDDR4_Mem_Mc0_Reset_n => poDDR4_Mem_Mc0_Reset_n,
911 
912  ------------------------------------------------------
913  -- DDR4 / Shl / Memory Channel 1 Interface (Mc1)
914  ------------------------------------------------------
915  pioDDR4_Mem_Mc1_DmDbi_n => pioDDR4_Mem_Mc1_DmDbi_n,
916  pioDDR4_Mem_Mc1_Dq => pioDDR4_Mem_Mc1_Dq,
917  pioDDR4_Mem_Mc1_Dqs_n => pioDDR4_Mem_Mc1_Dqs_n,
918  pioDDR4_Mem_Mc1_Dqs_p => pioDDR4_Mem_Mc1_Dqs_p,
919  poDDR4_Mem_Mc1_Act_n => poDDR4_Mem_Mc1_Act_n,
920  poDDR4_Mem_Mc1_Adr => poDDR4_Mem_Mc1_Adr,
921  poDDR4_Mem_Mc1_Ba => poDDR4_Mem_Mc1_Ba,
922  poDDR4_Mem_Mc1_Bg => poDDR4_Mem_Mc1_Bg,
923  poDDR4_Mem_Mc1_Cke => poDDR4_Mem_Mc1_Cke,
924  poDDR4_Mem_Mc1_Odt => poDDR4_Mem_Mc1_Odt,
925  poDDR4_Mem_Mc1_Cs_n => poDDR4_Mem_Mc1_Cs_n,
926  poDDR4_Mem_Mc1_Ck_n => poDDR4_Mem_Mc1_Ck_n,
927  poDDR4_Mem_Mc1_Ck_p => poDDR4_Mem_Mc1_Ck_p,
928  poDDR4_Mem_Mc1_Reset_n => poDDR4_Mem_Mc1_Reset_n,
929 
930  ------------------------------------------------------
931  -- ECON / Edge / Connector Interface (SPD08-200)
932  ------------------------------------------------------
933  piECON_Eth_10Ge0_n => piECON_Eth_10Ge0_n,
934  piECON_Eth_10Ge0_p => piECON_Eth_10Ge0_p,
935  poECON_Eth_10Ge0_n => poECON_Eth_10Ge0_n,
936  poECON_Eth_10Ge0_p => poECON_Eth_10Ge0_p,
937 
938  ------------------------------------------------------
939  -- ROLE / Reset and Clock Interfaces
940  ------------------------------------------------------
941  poROL_156_25Clk => sSHL_156_25Clk,
942  poROL_156_25Rst => sSHL_156_25Rst,
943 
944  ------------------------------------------------------
945  -- ROLE / Shl / Nts0 / Udp Interface
946  ------------------------------------------------------
947  -- Input AXI-Write Stream Interface ----------
948  siROL_Nts_Udp_Data_tdata => sROL_Shl_Nts0_Udp_Axis_tdata,
949  siROL_Nts_Udp_Data_tkeep => sROL_Shl_Nts0_Udp_Axis_tkeep,
950  siROL_Nts_Udp_Data_tlast => sROL_Shl_Nts0_Udp_Axis_tlast,
951  siROL_Nts_Udp_Data_tvalid => sROL_Shl_Nts0_Udp_Axis_tvalid,
952  siROL_Nts_Udp_Data_tready => sSHL_Rol_Nts0_Udp_Axis_tready,
953  -- Output AXI-Write Stream Interface ---------
954  soROL_Nts_Udp_Data_tdata => sSHL_Rol_Nts0_Udp_Axis_tdata ,
955  soROL_Nts_Udp_Data_tkeep => sSHL_Rol_Nts0_Udp_Axis_tkeep,
956  soROL_Nts_Udp_Data_tlast => sSHL_Rol_Nts0_Udp_Axis_tlast ,
957  soROL_Nts_Udp_Data_tvalid => sSHL_Rol_Nts0_Udp_Axis_tvalid,
958  soROL_Nts_Udp_Data_tready => sROL_Shl_Nts0_Udp_Axis_tready,
959  -- Open Port vector
960  piROL_Nrc_Udp_Rx_ports => sROL_Nrc_Udp_Rx_ports ,
961  -- ROLE <-> NRC Meta Interface
962  siROLE_Nrc_Udp_Meta_TDATA => sROLE_Nrc_Udp_Meta_TDATA ,
963  siROLE_Nrc_Udp_Meta_TVALID => sROLE_Nrc_Udp_Meta_TVALID ,
964  siROLE_Nrc_Udp_Meta_TREADY => sROLE_Nrc_Udp_Meta_TREADY ,
965  siROLE_Nrc_Udp_Meta_TKEEP => sROLE_Nrc_Udp_Meta_TKEEP ,
966  siROLE_Nrc_Udp_Meta_TLAST => sROLE_Nrc_Udp_Meta_TLAST ,
967  soNRC_Role_Udp_Meta_TDATA => sNRC_Role_Udp_Meta_TDATA ,
968  soNRC_Role_Udp_Meta_TVALID => sNRC_Role_Udp_Meta_TVALID ,
969  soNRC_Role_Udp_Meta_TREADY => sNRC_Role_Udp_Meta_TREADY ,
970  soNRC_Role_Udp_Meta_TKEEP => sNRC_Role_Udp_Meta_TKEEP ,
971  soNRC_Role_Udp_Meta_TLAST => sNRC_Role_Udp_Meta_TLAST ,
972 
973  ------------------------------------------------------
974  -- ROLE / Shl /Nts0 / Tcp Interfaces
975  ------------------------------------------------------
976  -- Input AXI-Write Stream Interface ----------
977  siROL_Nts_Tcp_Data_tdata => sROL_Shl_Nts0_Tcp_Axis_tdata,
978  siROL_Nts_Tcp_Data_tkeep => sROL_Shl_Nts0_Tcp_Axis_tkeep,
979  siROL_Nts_Tcp_Data_tlast => sROL_Shl_Nts0_Tcp_Axis_tlast,
980  siROL_Nts_Tcp_Data_tvalid => sROL_Shl_Nts0_Tcp_Axis_tvalid,
981  siROL_Nts_Tcp_Data_tready => sSHL_Rol_Nts0_Tcp_Axis_tready,
982  -- Output AXI-Write Stream Interface ---------
983  soROL_Nts_Tcp_Data_tdata => sSHL_Rol_Nts0_Tcp_Axis_tdata ,
984  soROL_Nts_Tcp_Data_tkeep => sSHL_Rol_Nts0_Tcp_Axis_tkeep,
985  soROL_Nts_Tcp_Data_tlast => sSHL_Rol_Nts0_Tcp_Axis_tlast ,
986  soROL_Nts_Tcp_Data_tvalid => sSHL_Rol_Nts0_Tcp_Axis_tvalid,
987  soROL_Nts_Tcp_Data_tready => sROL_Shl_Nts0_Tcp_Axis_tready,
988  -- Open Port vector
989  piROL_Nrc_Tcp_Rx_ports => sROL_Nrc_Tcp_Rx_ports ,
990  -- ROLE <-> NRC Meta Interface
991  siROLE_Nrc_Tcp_Meta_TDATA => sROLE_Nrc_Tcp_Meta_TDATA ,
992  siROLE_Nrc_Tcp_Meta_TVALID => sROLE_Nrc_Tcp_Meta_TVALID ,
993  siROLE_Nrc_Tcp_Meta_TREADY => sROLE_Nrc_Tcp_Meta_TREADY ,
994  siROLE_Nrc_Tcp_Meta_TKEEP => sROLE_Nrc_Tcp_Meta_TKEEP ,
995  siROLE_Nrc_Tcp_Meta_TLAST => sROLE_Nrc_Tcp_Meta_TLAST ,
996  soNRC_Role_Tcp_Meta_TDATA => sNRC_Role_Tcp_Meta_TDATA ,
997  soNRC_Role_Tcp_Meta_TVALID => sNRC_Role_Tcp_Meta_TVALID ,
998  soNRC_Role_Tcp_Meta_TREADY => sNRC_Role_Tcp_Meta_TREADY ,
999  soNRC_Role_Tcp_Meta_TKEEP => sNRC_Role_Tcp_Meta_TKEEP ,
1000  soNRC_Role_Tcp_Meta_TLAST => sNRC_Role_Tcp_Meta_TLAST ,
1001 
1002  ------------------------------------------------------
1003  -- ROLE / Mem / Mp0 Interface
1004  ------------------------------------------------------
1005  -- Memory Port #0 / S2MM-AXIS ------------------
1006  ---- Stream Read Command ---------
1007  siROL_Mem_Mp0_RdCmd_tdata => ssROL_SHL_Mem_Mp0_RdCmd_tdata,
1008  siROL_Mem_Mp0_RdCmd_tvalid => ssROL_SHL_Mem_Mp0_RdCmd_tvalid,
1009  siROL_Mem_Mp0_RdCmd_tready => ssROL_SHL_Mem_Mp0_RdCmd_tready,
1010  ---- Stream Read Status ----------
1011  soROL_Mem_Mp0_RdSts_tdata => ssSHL_ROL_Mem_Mp0_RdSts_tdata,
1012  soROL_Mem_Mp0_RdSts_tvalid => ssSHL_ROL_Mem_Mp0_RdSts_tvalid,
1013  soROL_Mem_Mp0_RdSts_tready => ssSHL_ROL_Mem_Mp0_RdSts_tready,
1014  ---- Stream Data Output Channel --
1015  soROL_Mem_Mp0_Read_tdata => ssSHL_ROL_Mem_Mp0_Read_tdata,
1016  soROL_Mem_Mp0_Read_tkeep => ssSHL_ROL_Mem_Mp0_Read_tkeep,
1017  soROL_Mem_Mp0_Read_tlast => ssSHL_ROL_Mem_Mp0_Read_tlast,
1018  soROL_Mem_Mp0_Read_tvalid => ssSHL_ROL_Mem_Mp0_Read_tvalid,
1019  soROL_Mem_Mp0_Read_tready => ssSHL_ROL_Mem_Mp0_Read_tready,
1020  ---- Stream Write Command --------
1021  siROL_Mem_Mp0_WrCmd_tdata => ssROL_SHL_Mem_Mp0_WrCmd_tdata,
1022  siROL_Mem_Mp0_WrCmd_tvalid => ssROL_SHL_Mem_Mp0_WrCmd_tvalid,
1023  siROL_Mem_Mp0_WrCmd_tready => ssROL_SHL_Mem_Mp0_WrCmd_tready,
1024  ---- Stream Write Status ---------
1025  soROL_Mem_Mp0_WrSts_tvalid => ssSHL_ROL_Mem_Mp0_WrSts_tvalid,
1026  soROL_Mem_Mp0_WrSts_tdata => ssSHL_ROL_Mem_Mp0_WrSts_tdata,
1027  soROL_Mem_Mp0_WrSts_tready => ssSHL_ROL_Mem_Mp0_WrSts_tready,
1028  ---- Stream Data Input Channel ---
1029  siROL_Mem_Mp0_Write_tdata => ssROL_SHL_Mem_Mp0_Write_tdata,
1030  siROL_Mem_Mp0_Write_tkeep => ssROL_SHL_Mem_Mp0_Write_tkeep,
1031  siROL_Mem_Mp0_Write_tlast => ssROL_SHL_Mem_Mp0_Write_tlast,
1032  siROL_Mem_Mp0_Write_tvalid => ssROL_SHL_Mem_Mp0_Write_tvalid,
1033  siROL_Mem_Mp0_Write_tready => ssROL_SHL_Mem_Mp0_Write_tready,
1034 
1035  ------------------------------------------------------
1036  -- ROLE / Mem / Mp1 Interface
1037  ------------------------------------------------------
1038  miROL_Mem_Mp1_AWID => smROL_SHL_Mem_Mp1_AWID ,
1039  miROL_Mem_Mp1_AWADDR => smROL_SHL_Mem_Mp1_AWADDR ,
1040  miROL_Mem_Mp1_AWLEN => smROL_SHL_Mem_Mp1_AWLEN ,
1041  miROL_Mem_Mp1_AWSIZE => smROL_SHL_Mem_Mp1_AWSIZE ,
1042  miROL_Mem_Mp1_AWBURST => smROL_SHL_Mem_Mp1_AWBURST ,
1043  miROL_Mem_Mp1_AWVALID => smROL_SHL_Mem_Mp1_AWVALID ,
1044  miROL_Mem_Mp1_AWREADY => smROL_SHL_Mem_Mp1_AWREADY ,
1045  miROL_Mem_Mp1_WDATA => smROL_SHL_Mem_Mp1_WDATA ,
1046  miROL_Mem_Mp1_WSTRB => smROL_SHL_Mem_Mp1_WSTRB ,
1047  miROL_Mem_Mp1_WLAST => smROL_SHL_Mem_Mp1_WLAST ,
1048  miROL_Mem_Mp1_WVALID => smROL_SHL_Mem_Mp1_WVALID ,
1049  miROL_Mem_Mp1_WREADY => smROL_SHL_Mem_Mp1_WREADY ,
1050  miROL_Mem_Mp1_BID => smROL_SHL_Mem_Mp1_BID ,
1051  miROL_Mem_Mp1_BRESP => smROL_SHL_Mem_Mp1_BRESP ,
1052  miROL_Mem_Mp1_BVALID => smROL_SHL_Mem_Mp1_BVALID ,
1053  miROL_Mem_Mp1_BREADY => smROL_SHL_Mem_Mp1_BREADY ,
1054  miROL_Mem_Mp1_ARID => smROL_SHL_Mem_Mp1_ARID ,
1055  miROL_Mem_Mp1_ARADDR => smROL_SHL_Mem_Mp1_ARADDR ,
1056  miROL_Mem_Mp1_ARLEN => smROL_SHL_Mem_Mp1_ARLEN ,
1057  miROL_Mem_Mp1_ARSIZE => smROL_SHL_Mem_Mp1_ARSIZE ,
1058  miROL_Mem_Mp1_ARBURST => smROL_SHL_Mem_Mp1_ARBURST ,
1059  miROL_Mem_Mp1_ARVALID => smROL_SHL_Mem_Mp1_ARVALID ,
1060  miROL_Mem_Mp1_ARREADY => smROL_SHL_Mem_Mp1_ARREADY ,
1061  miROL_Mem_Mp1_RID => smROL_SHL_Mem_Mp1_RID ,
1062  miROL_Mem_Mp1_RDATA => smROL_SHL_Mem_Mp1_RDATA ,
1063  miROL_Mem_Mp1_RRESP => smROL_SHL_Mem_Mp1_RRESP ,
1064  miROL_Mem_Mp1_RLAST => smROL_SHL_Mem_Mp1_RLAST ,
1065  miROL_Mem_Mp1_RVALID => smROL_SHL_Mem_Mp1_RVALID ,
1066  miROL_Mem_Mp1_RREADY => smROL_SHL_Mem_Mp1_RREADY ,
1067 
1068  ------------------------------------------------------
1069  -- ROLE / Mmio / AppFlash Interface
1070  ------------------------------------------------------
1071  ---- [PHY_RESET] -----------------
1072  poROL_Mmio_Ly7Rst => (sSHL_ROL_Mmio_Ly7Rst),
1073  ---- [PHY_ENABLE] --------------
1074  poROL_Mmio_Ly7En => (sSHL_ROL_Mmio_Ly7En),
1075  ---- [DIAG_CTRL_1] ---------------
1076  poROL_Mmio_Mc1_MemTestCtrl => sSHL_ROL_Mmio_Mc1_MemTestCtrl,
1077  ---- [DIAG_STAT_1] ---------------
1078  piROL_Mmio_Mc1_MemTestStat => sROL_SHL_Mmio_Mc1_MemTestStat,
1079  ---- [DIAG_CTRL_2] ---------------
1080  poROL_Mmio_UdpEchoCtrl => sSHL_ROL_Mmio_UdpEchoCtrl,
1081  poROL_Mmio_UdpPostDgmEn => sSHL_ROL_Mmio_UdpPostDgmEn,
1082  poROL_Mmio_UdpCaptDgmEn => sSHL_ROL_Mmio_UdpCaptDgmEn,
1083  poROL_Mmio_TcpEchoCtrl => sSHL_ROL_Mmio_TcpEchoCtrl,
1084  poROL_Mmio_TcpPostSegEn => sSHL_ROL_Mmio_TcpPostSegEn,
1085  poROL_Mmio_TcpCaptSegEn => sSHL_ROL_Mmio_TcpCaptSegEn,
1086  ---- [APP_RDROL] -----------------
1087  piROL_Mmio_RdReg => sROL_SHL_Mmio_RdReg,
1088  ---- [APP_WRROL] -----------------
1089  poROL_Mmio_WrReg => sSHL_ROL_Mmio_WrReg,
1090 
1091  --------------------------------------------------------
1092  -- ROLE / Fmc / Management Interface
1093  --------------------------------------------------------
1094  poROL_Fmc_Rank => sSHL_ROL_Fmc_Rank,
1095  poROL_Fmc_Size => sSHL_ROL_Fmc_Size,
1096 
1097  poVoid => open
1098 
1099  ); -- End of SuperShell instantiation
1100 
1101 
1102  --==========================================================================
1103  -- INST: ROLE FOR FMKU60
1104  --==========================================================================
1105 
1106  -- drive MMIO signals if NOT used by the ROLE
1107  sROL_SHL_Mmio_Mc1_MemTestStat <= (others => '0');
1108  --sROL_SHL_Mmio_RdReg <= x"CFCF";
1109 
1110  -- security consideration: if we want to reset layer 7, the user should not be able to avoid it
1111  sROL_reset_combinded <= sSHL_156_25Rst or sSHL_ROL_Mmio_Ly7Rst;
1112 
1113  ROLE : Role_Themisto
1114  port map (
1115 
1116  ------------------------------------------------------
1117  -- SHELL / Global Input Clock and Reset Interface
1118  ------------------------------------------------------
1119  piSHL_156_25Clk => sSHL_156_25Clk,
1120  --piSHL_156_25Rst => sSHL_156_25Rst,
1121  piSHL_156_25Rst => sROL_reset_combinded,
1122  -- LY7 Enable and Reset
1123  piMMIO_Ly7_Rst => sSHL_ROL_Mmio_Ly7Rst,
1124  piMMIO_Ly7_En => sSHL_ROL_Mmio_Ly7En,
1125 
1126  ------------------------------------------------------
1127  -- SHELL / Role / Nts0 / Udp Interface
1128  ------------------------------------------------------
1129  -- Input AXI-Write Stream Interface ----------
1130  siNRC_Udp_Data_tdata => sSHL_Rol_Nts0_Udp_Axis_tdata,
1131  siNRC_Udp_Data_tkeep => sSHL_Rol_Nts0_Udp_Axis_tkeep,
1132  siNRC_Udp_Data_tlast => sSHL_Rol_Nts0_Udp_Axis_tlast,
1133  siNRC_Udp_Data_tvalid => sSHL_Rol_Nts0_Udp_Axis_tvalid,
1134  siNRC_Udp_Data_tready => sROL_Shl_Nts0_Udp_Axis_tready,
1135  -- Output AXI-Write Stream Interface ---------
1136  soNRC_Udp_Data_tdata => sROL_Shl_Nts0_Udp_Axis_tdata,
1137  soNRC_Udp_Data_tkeep => sROL_Shl_Nts0_Udp_Axis_tkeep,
1138  soNRC_Udp_Data_tlast => sROL_Shl_Nts0_Udp_Axis_tlast,
1139  soNRC_Udp_Data_tvalid => sROL_Shl_Nts0_Udp_Axis_tvalid,
1140  soNRC_Udp_Data_tready => sSHL_Rol_Nts0_Udp_Axis_tready,
1141  -- Open Port vector
1142  poROL_Nrc_Udp_Rx_ports => sROL_Nrc_Udp_Rx_ports ,
1143  -- ROLE <-> NRC Meta Interface
1144  soROLE_Nrc_Udp_Meta_TDATA => sROLE_Nrc_Udp_Meta_TDATA ,
1145  soROLE_Nrc_Udp_Meta_TVALID => sROLE_Nrc_Udp_Meta_TVALID ,
1146  soROLE_Nrc_Udp_Meta_TREADY => sROLE_Nrc_Udp_Meta_TREADY ,
1147  soROLE_Nrc_Udp_Meta_TKEEP => sROLE_Nrc_Udp_Meta_TKEEP ,
1148  soROLE_Nrc_Udp_Meta_TLAST => sROLE_Nrc_Udp_Meta_TLAST ,
1149  siNRC_Role_Udp_Meta_TDATA => sNRC_Role_Udp_Meta_TDATA ,
1150  siNRC_Role_Udp_Meta_TVALID => sNRC_Role_Udp_Meta_TVALID ,
1151  siNRC_Role_Udp_Meta_TREADY => sNRC_Role_Udp_Meta_TREADY ,
1152  siNRC_Role_Udp_Meta_TKEEP => sNRC_Role_Udp_Meta_TKEEP ,
1153  siNRC_Role_Udp_Meta_TLAST => sNRC_Role_Udp_Meta_TLAST ,
1154 
1155  ------------------------------------------------------
1156  -- SHELL / Role / Nts0 / Tcp Interface
1157  ------------------------------------------------------
1158  -- Input AXI-Write Stream Interface ----------
1159  siNRC_Tcp_Data_tdata => sSHL_Rol_Nts0_Tcp_Axis_tdata,
1160  siNRC_Tcp_Data_tkeep => sSHL_Rol_Nts0_Tcp_Axis_tkeep,
1161  siNRC_Tcp_Data_tlast => sSHL_Rol_Nts0_Tcp_Axis_tlast,
1162  siNRC_Tcp_Data_tvalid => sSHL_Rol_Nts0_Tcp_Axis_tvalid,
1163  siNRC_Tcp_Data_tready => sROL_Shl_Nts0_Tcp_Axis_tready,
1164  -- Output AXI-Write Stream Interface ---------
1165  soNRC_Tcp_Data_tdata => sROL_Shl_Nts0_Tcp_Axis_tdata,
1166  soNRC_Tcp_Data_tkeep => sROL_Shl_Nts0_Tcp_Axis_tkeep,
1167  soNRC_Tcp_Data_tlast => sROL_Shl_Nts0_Tcp_Axis_tlast,
1168  soNRC_Tcp_Data_tvalid => sROL_Shl_Nts0_Tcp_Axis_tvalid,
1169  soNRC_Tcp_Data_tready => sSHL_Rol_Nts0_Tcp_Axis_tready,
1170  -- Open Port vector
1171  poROL_Nrc_Tcp_Rx_ports => sROL_Nrc_Tcp_Rx_ports ,
1172  -- ROLE <-> NRC Meta Interface
1173  soROLE_Nrc_Tcp_Meta_TDATA => sROLE_Nrc_Tcp_Meta_TDATA ,
1174  soROLE_Nrc_Tcp_Meta_TVALID => sROLE_Nrc_Tcp_Meta_TVALID ,
1175  soROLE_Nrc_Tcp_Meta_TREADY => sROLE_Nrc_Tcp_Meta_TREADY ,
1176  soROLE_Nrc_Tcp_Meta_TKEEP => sROLE_Nrc_Tcp_Meta_TKEEP ,
1177  soROLE_Nrc_Tcp_Meta_TLAST => sROLE_Nrc_Tcp_Meta_TLAST ,
1178  siNRC_Role_Tcp_Meta_TDATA => sNRC_Role_Tcp_Meta_TDATA ,
1179  siNRC_Role_Tcp_Meta_TVALID => sNRC_Role_Tcp_Meta_TVALID ,
1180  siNRC_Role_Tcp_Meta_TREADY => sNRC_Role_Tcp_Meta_TREADY ,
1181  siNRC_Role_Tcp_Meta_TKEEP => sNRC_Role_Tcp_Meta_TKEEP ,
1182  siNRC_Role_Tcp_Meta_TLAST => sNRC_Role_Tcp_Meta_TLAST ,
1183 
1184 
1185 ------------------------------------------------------
1186  -- SHELL / Mem / Mp0 Interface
1187  ------------------------------------------------------
1188  -- Memory Port #0 / S2MM-AXIS ------------------
1189  ---- Stream Read Command ---------
1190  soMEM_Mp0_RdCmd_tdata => ssROL_SHL_Mem_Mp0_RdCmd_tdata,
1191  soMEM_Mp0_RdCmd_tvalid => ssROL_SHL_Mem_Mp0_RdCmd_tvalid,
1192  soMEM_Mp0_RdCmd_tready => ssROL_SHL_Mem_Mp0_RdCmd_tready,
1193  ---- Stream Read Status ----------
1194  siMEM_Mp0_RdSts_tdata => ssSHL_ROL_Mem_Mp0_RdSts_tdata,
1195  siMEM_Mp0_RdSts_tvalid => ssSHL_ROL_Mem_Mp0_RdSts_tvalid,
1196  siMEM_Mp0_RdSts_tready => ssSHL_ROL_Mem_Mp0_RdSts_tready,
1197  ---- Stream Data Input Channel ---
1198  siMEM_Mp0_Read_tdata => ssSHL_ROL_Mem_Mp0_Read_tdata,
1199  siMEM_Mp0_Read_tkeep => ssSHL_ROL_Mem_Mp0_Read_tkeep,
1200  siMEM_Mp0_Read_tlast => ssSHL_ROL_Mem_Mp0_Read_tlast,
1201  siMEM_Mp0_Read_tvalid => ssSHL_ROL_Mem_Mp0_Read_tvalid,
1202  siMEM_Mp0_Read_tready => ssSHL_ROL_Mem_Mp0_Read_tready,
1203  ---- Stream Write Command --------
1204  soMEM_Mp0_WrCmd_tdata => ssROL_SHL_Mem_Mp0_WrCmd_tdata,
1205  soMEM_Mp0_WrCmd_tvalid => ssROL_SHL_Mem_Mp0_WrCmd_tvalid,
1206  soMEM_Mp0_WrCmd_tready => ssROL_SHL_Mem_Mp0_WrCmd_tready,
1207  ---- Stream Write Status ---------
1208  siMEM_Mp0_WrSts_tvalid => ssSHL_ROL_Mem_Mp0_WrSts_tvalid,
1209  siMEM_Mp0_WrSts_tdata => ssSHL_ROL_Mem_Mp0_WrSts_tdata,
1210  siMEM_Mp0_WrSts_tready => ssSHL_ROL_Mem_Mp0_WrSts_tready,
1211  ---- Stream Data Output Channel --
1212  soMEM_Mp0_Write_tdata => ssROL_SHL_Mem_Mp0_Write_tdata,
1213  soMEM_Mp0_Write_tkeep => ssROL_SHL_Mem_Mp0_Write_tkeep,
1214  soMEM_Mp0_Write_tlast => ssROL_SHL_Mem_Mp0_Write_tlast,
1215  soMEM_Mp0_Write_tvalid => ssROL_SHL_Mem_Mp0_Write_tvalid,
1216  soMEM_Mp0_Write_tready => ssROL_SHL_Mem_Mp0_Write_tready,
1217 
1218  ------------------------------------------------------
1219  -- SHELL / Role / Mem / Mp1 Interface
1220  ------------------------------------------------------
1221  moMEM_Mp1_AWID => smROL_SHL_Mem_Mp1_AWID ,
1222  moMEM_Mp1_AWADDR => smROL_SHL_Mem_Mp1_AWADDR ,
1223  moMEM_Mp1_AWLEN => smROL_SHL_Mem_Mp1_AWLEN ,
1224  moMEM_Mp1_AWSIZE => smROL_SHL_Mem_Mp1_AWSIZE ,
1225  moMEM_Mp1_AWBURST => smROL_SHL_Mem_Mp1_AWBURST ,
1226  moMEM_Mp1_AWVALID => smROL_SHL_Mem_Mp1_AWVALID ,
1227  moMEM_Mp1_AWREADY => smROL_SHL_Mem_Mp1_AWREADY ,
1228  moMEM_Mp1_WDATA => smROL_SHL_Mem_Mp1_WDATA ,
1229  moMEM_Mp1_WSTRB => smROL_SHL_Mem_Mp1_WSTRB ,
1230  moMEM_Mp1_WLAST => smROL_SHL_Mem_Mp1_WLAST ,
1231  moMEM_Mp1_WVALID => smROL_SHL_Mem_Mp1_WVALID ,
1232  moMEM_Mp1_WREADY => smROL_SHL_Mem_Mp1_WREADY ,
1233  moMEM_Mp1_BID => smROL_SHL_Mem_Mp1_BID ,
1234  moMEM_Mp1_BRESP => smROL_SHL_Mem_Mp1_BRESP ,
1235  moMEM_Mp1_BVALID => smROL_SHL_Mem_Mp1_BVALID ,
1236  moMEM_Mp1_BREADY => smROL_SHL_Mem_Mp1_BREADY ,
1237  moMEM_Mp1_ARID => smROL_SHL_Mem_Mp1_ARID ,
1238  moMEM_Mp1_ARADDR => smROL_SHL_Mem_Mp1_ARADDR ,
1239  moMEM_Mp1_ARLEN => smROL_SHL_Mem_Mp1_ARLEN ,
1240  moMEM_Mp1_ARSIZE => smROL_SHL_Mem_Mp1_ARSIZE ,
1241  moMEM_Mp1_ARBURST => smROL_SHL_Mem_Mp1_ARBURST ,
1242  moMEM_Mp1_ARVALID => smROL_SHL_Mem_Mp1_ARVALID ,
1243  moMEM_Mp1_ARREADY => smROL_SHL_Mem_Mp1_ARREADY ,
1244  moMEM_Mp1_RID => smROL_SHL_Mem_Mp1_RID ,
1245  moMEM_Mp1_RDATA => smROL_SHL_Mem_Mp1_RDATA ,
1246  moMEM_Mp1_RRESP => smROL_SHL_Mem_Mp1_RRESP ,
1247  moMEM_Mp1_RLAST => smROL_SHL_Mem_Mp1_RLAST ,
1248  moMEM_Mp1_RVALID => smROL_SHL_Mem_Mp1_RVALID ,
1249  moMEM_Mp1_RREADY => smROL_SHL_Mem_Mp1_RREADY ,
1250 
1251  -- leave declarations here for higher privileged Roles?
1252  --------------------------------------------------------
1253  ---- SHELL / Mmio / Flash Debug Interface
1254  --------------------------------------------------------
1255  ------ [DIAG_CTRL_1] ---------------
1256  --piSHL_Mmio_Mc1_MemTestCtrl => sSHL_ROL_Mmio_Mc1_MemTestCtrl,
1257  ------ [DIAG_STAT_1] ---------------
1258  --poSHL_Mmio_Mc1_MemTestStat => sROL_SHL_Mmio_Mc1_MemTestStat,
1259  ------ [DIAG_CTRL_2] ---------------
1260  --piSHL_Mmio_UdpEchoCtrl => sSHL_ROL_Mmio_UdpEchoCtrl,
1261  --piSHL_Mmio_UdpPostDgmEn => sSHL_ROL_Mmio_UdpPostDgmEn,
1262  --piSHL_Mmio_UdpCaptDgmEn => sSHL_ROL_Mmio_UdpCaptDgmEn,
1263  --piSHL_Mmio_TcpEchoCtrl => sSHL_ROL_Mmio_TcpEchoCtrl,
1264  --piSHL_Mmio_TcpPostSegEn => sSHL_ROL_Mmio_TcpPostSegEn,
1265  --piSHL_Mmio_TcpCaptSegEn => sSHL_ROL_Mmio_TcpCaptSegEn,
1266  ---- [APP_RDROL] -----------------
1267  poSHL_Mmio_RdReg => sROL_SHL_Mmio_RdReg,
1268  ----- [APP_WRROL] ------------------
1269  --piSHL_Mmio_WrReg => sSHL_ROL_Mmio_WrReg,
1270 
1271  ------------------------------------------------------
1272  ---- TOP : Secondary Clock (Asynchronous)
1273  ------------------------------------------------------
1274  piTOP_250_00Clk => sTOP_250_00Clk, -- Freerunning
1275 
1276  --------------------------------------------------------
1277  -- ROLE / Fmc / Management Interface
1278  --------------------------------------------------------
1279  piFMC_ROLE_rank => sSHL_ROL_Fmc_Rank,
1280  piFMC_ROLE_size => sSHL_ROL_Fmc_Size,
1281 
1282  ------------------------------------------------
1283  -- DEBUG PORTS (see UG909)
1284  ------------------------------------------------
1285  dpBSCAN_drck => open,
1286  dpBSCAN_shift => open,
1287  dpBSCAN_tdi => open,
1288  dpBSCAN_update => open,
1289  dpBSCAN_sel => open,
1290  dpBSCAN_tdo => open,
1291  dpBSCAN_tms => open,
1292  dpBSCAN_tck => open,
1293  dpBSCAN_runtest => open,
1294  dpBSCAN_reset => open,
1295  dpBSCAN_capture => open,
1296  dpBSCAN_bscanid_en => open,
1297 
1298  poVoid => open
1299 
1300  ); -- End of Role instantiation
1301 
1302 end structural;
1303 
Role_Themisto
Definition: Role.vhdl:43
Role_Themisto.soNRC_Tcp_Data_tready
in soNRC_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:98
Role_Themisto.moMEM_Mp1_ARSIZE
out moMEM_Mp1_ARSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:169
Role_Themisto.moMEM_Mp1_AWADDR
out moMEM_Mp1_AWADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:151
Role_Themisto.soNRC_Udp_Data_tdata
out soNRC_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:65
Role_Themisto.soROLE_Nrc_Udp_Meta_TREADY
in soROLE_Nrc_Udp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:75
Role_Themisto.piSHL_156_25Clk
in piSHL_156_25Clkstd_ulogic
Definition: Role.vhdl:49
Role_Themisto.moMEM_Mp1_RREADY
out moMEM_Mp1_RREADYstd_ulogic
Definition: Role.vhdl:178
Role_Themisto.soROLE_Nrc_Udp_Meta_TKEEP
out soROLE_Nrc_Udp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:76
Role_Themisto.piSHL_156_25Rst
in piSHL_156_25Rststd_ulogic
Definition: Role.vhdl:50
Role_Themisto.dpBSCAN_tdi
in dpBSCAN_tdistd_logic
Definition: Role.vhdl:200
Role_Themisto.moMEM_Mp1_RLAST
in moMEM_Mp1_RLASTstd_ulogic
Definition: Role.vhdl:176
Role_Themisto.siNRC_Udp_Data_tlast
in siNRC_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:62
Role_Themisto.siMEM_Mp0_Read_tready
out siMEM_Mp0_Read_treadystd_ulogic
Definition: Role.vhdl:131
Role_Themisto.siNRC_Role_Udp_Meta_TKEEP
in siNRC_Role_Udp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:81
Role_Themisto.siMEM_Mp0_Read_tkeep
in siMEM_Mp0_Read_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:128
Role_Themisto.dpBSCAN_reset
in dpBSCAN_resetstd_logic
Definition: Role.vhdl:207
Role_Themisto.dpBSCAN_sel
in dpBSCAN_selstd_logic
Definition: Role.vhdl:202
Role_Themisto.dpBSCAN_drck
in dpBSCAN_drckstd_logic
Definition: Role.vhdl:198
Role_Themisto.soNRC_Tcp_Data_tdata
out soNRC_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:94
Role_Themisto.soROLE_Nrc_Tcp_Meta_TREADY
in soROLE_Nrc_Tcp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:104
Role_Themisto.siNRC_Role_Tcp_Meta_TLAST
in siNRC_Role_Tcp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:111
Role_Themisto.siMEM_Mp0_WrSts_tdata
in siMEM_Mp0_WrSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:137
Role_Themisto.soMEM_Mp0_Write_tkeep
out soMEM_Mp0_Write_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:142
Role_Themisto.siNRC_Tcp_Data_tready
out siNRC_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:92
Role_Themisto.siNRC_Role_Udp_Meta_TDATA
in siNRC_Role_Udp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:78
Role_Themisto.moMEM_Mp1_AWVALID
out moMEM_Mp1_AWVALIDstd_ulogic
Definition: Role.vhdl:155
Role_Themisto.siNRC_Role_Tcp_Meta_TVALID
in siNRC_Role_Tcp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:108
Role_Themisto.siNRC_Role_Tcp_Meta_TDATA
in siNRC_Role_Tcp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:107
Role_Themisto.moMEM_Mp1_BVALID
in moMEM_Mp1_BVALIDstd_ulogic
Definition: Role.vhdl:164
Role_Themisto.moMEM_Mp1_WSTRB
out moMEM_Mp1_WSTRBstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:158
Role_Themisto.moMEM_Mp1_BREADY
out moMEM_Mp1_BREADYstd_ulogic
Definition: Role.vhdl:165
Role_Themisto.moMEM_Mp1_AWID
out moMEM_Mp1_AWIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:150
Role_Themisto.moMEM_Mp1_RVALID
in moMEM_Mp1_RVALIDstd_ulogic
Definition: Role.vhdl:177
Role_Themisto.soNRC_Udp_Data_tready
in soNRC_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:69
Role_Themisto.soMEM_Mp0_WrCmd_tready
in soMEM_Mp0_WrCmd_treadystd_ulogic
Definition: Role.vhdl:135
Role_Themisto.siNRC_Udp_Data_tvalid
in siNRC_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:61
Role_Themisto.piMMIO_Ly7_En
in piMMIO_Ly7_Enstd_ulogic
Definition: Role.vhdl:53
Role_Themisto.soMEM_Mp0_Write_tready
in soMEM_Mp0_Write_treadystd_ulogic
Definition: Role.vhdl:145
Role_Themisto.soNRC_Udp_Data_tlast
out soNRC_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:68
Role_Themisto.soROLE_Nrc_Udp_Meta_TVALID
out soROLE_Nrc_Udp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:74
Role_Themisto.soROLE_Nrc_Tcp_Meta_TVALID
out soROLE_Nrc_Tcp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:103
Role_Themisto.moMEM_Mp1_WLAST
out moMEM_Mp1_WLASTstd_ulogic
Definition: Role.vhdl:159
Role_Themisto.soNRC_Udp_Data_tvalid
out soNRC_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:67
Role_Themisto.moMEM_Mp1_WDATA
out moMEM_Mp1_WDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:157
Role_Themisto.siNRC_Tcp_Data_tdata
in siNRC_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:88
Role_Themisto.soMEM_Mp0_RdCmd_tdata
out soMEM_Mp0_RdCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:119
Role_Themisto.siMEM_Mp0_Read_tdata
in siMEM_Mp0_Read_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:127
Role_Themisto.soMEM_Mp0_Write_tdata
out soMEM_Mp0_Write_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:141
Role_Themisto.siMEM_Mp0_RdSts_tready
out siMEM_Mp0_RdSts_treadystd_ulogic
Definition: Role.vhdl:125
Role_Themisto.moMEM_Mp1_ARBURST
out moMEM_Mp1_ARBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:170
Role_Themisto.siNRC_Role_Tcp_Meta_TKEEP
in siNRC_Role_Tcp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:110
Role_Themisto.siMEM_Mp0_RdSts_tdata
in siMEM_Mp0_RdSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:123
Role_Themisto.poROL_Nrc_Tcp_Rx_ports
out poROL_Nrc_Tcp_Rx_portsstd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:100
Role_Themisto.siNRC_Tcp_Data_tvalid
in siNRC_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:90
Role_Themisto.siNRC_Role_Udp_Meta_TLAST
in siNRC_Role_Udp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:82
Role_Themisto.moMEM_Mp1_ARREADY
in moMEM_Mp1_ARREADYstd_ulogic
Definition: Role.vhdl:172
Role_Themisto.siNRC_Udp_Data_tready
out siNRC_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:63
Role_Themisto.dpBSCAN_tms
in dpBSCAN_tmsstd_logic
Definition: Role.vhdl:204
Role_Themisto.moMEM_Mp1_RRESP
in moMEM_Mp1_RRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:175
Role_Themisto.soMEM_Mp0_Write_tlast
out soMEM_Mp0_Write_tlaststd_ulogic
Definition: Role.vhdl:143
Role_Themisto.moMEM_Mp1_ARID
out moMEM_Mp1_ARIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:166
Role_Themisto.dpBSCAN_capture
in dpBSCAN_capturestd_logic
Definition: Role.vhdl:208
Role_Themisto.soMEM_Mp0_WrCmd_tvalid
out soMEM_Mp0_WrCmd_tvalidstd_ulogic
Definition: Role.vhdl:134
Role_Themisto.moMEM_Mp1_ARVALID
out moMEM_Mp1_ARVALIDstd_ulogic
Definition: Role.vhdl:171
Role_Themisto.soROLE_Nrc_Tcp_Meta_TDATA
out soROLE_Nrc_Tcp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:102
Role_Themisto.moMEM_Mp1_AWBURST
out moMEM_Mp1_AWBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:154
Role_Themisto.siNRC_Udp_Data_tkeep
in siNRC_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:60
Role_Themisto.soMEM_Mp0_RdCmd_tvalid
out soMEM_Mp0_RdCmd_tvalidstd_ulogic
Definition: Role.vhdl:120
Role_Themisto.soNRC_Tcp_Data_tkeep
out soNRC_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:95
Role_Themisto.siMEM_Mp0_Read_tvalid
in siMEM_Mp0_Read_tvalidstd_ulogic
Definition: Role.vhdl:130
Role_Themisto.dpBSCAN_bscanid_en
in dpBSCAN_bscanid_enstd_logic
Definition: Role.vhdl:209
Role_Themisto.dpBSCAN_tdo
out dpBSCAN_tdostd_logic
Definition: Role.vhdl:203
Role_Themisto.moMEM_Mp1_RID
in moMEM_Mp1_RIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:173
Role_Themisto.soROLE_Nrc_Udp_Meta_TDATA
out soROLE_Nrc_Udp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:73
Role_Themisto.piFMC_ROLE_rank
in piFMC_ROLE_rankstd_logic_vector(31 downto 0)
Definition: Role.vhdl:192
Role_Themisto.soROLE_Nrc_Tcp_Meta_TKEEP
out soROLE_Nrc_Tcp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:105
Role_Themisto.piTOP_250_00Clk
in piTOP_250_00Clkstd_ulogic
Definition: Role.vhdl:187
Role_Themisto.moMEM_Mp1_AWLEN
out moMEM_Mp1_AWLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:152
Role_Themisto.piFMC_ROLE_size
in piFMC_ROLE_sizestd_logic_vector(31 downto 0)
Definition: Role.vhdl:193
Role_Themisto.siNRC_Tcp_Data_tkeep
in siNRC_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:89
Role_Themisto.soMEM_Mp0_RdCmd_tready
in soMEM_Mp0_RdCmd_treadystd_ulogic
Definition: Role.vhdl:121
Role_Themisto.moMEM_Mp1_WREADY
in moMEM_Mp1_WREADYstd_ulogic
Definition: Role.vhdl:161
Role_Themisto.siNRC_Role_Udp_Meta_TREADY
out siNRC_Role_Udp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:80
Role_Themisto.soNRC_Tcp_Data_tlast
out soNRC_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:97
Role_Themisto.siMEM_Mp0_RdSts_tvalid
in siMEM_Mp0_RdSts_tvalidstd_ulogic
Definition: Role.vhdl:124
Role_Themisto.soROLE_Nrc_Udp_Meta_TLAST
out soROLE_Nrc_Udp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:77
Role_Themisto.moMEM_Mp1_AWSIZE
out moMEM_Mp1_AWSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:153
Role_Themisto.dpBSCAN_shift
in dpBSCAN_shiftstd_logic
Definition: Role.vhdl:199
Role_Themisto.moMEM_Mp1_RDATA
in moMEM_Mp1_RDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:174
Role_Themisto.moMEM_Mp1_BID
in moMEM_Mp1_BIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:162
Role_Themisto.soMEM_Mp0_WrCmd_tdata
out soMEM_Mp0_WrCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:133
Role_Themisto.piMMIO_Ly7_Rst
in piMMIO_Ly7_Rststd_ulogic
Definition: Role.vhdl:52
Role_Themisto.poSHL_Mmio_RdReg
out poSHL_Mmio_RdRegstd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:182
Role_Themisto.siNRC_Role_Tcp_Meta_TREADY
out siNRC_Role_Tcp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:109
Role_Themisto.siNRC_Role_Udp_Meta_TVALID
in siNRC_Role_Udp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:79
Role_Themisto.moMEM_Mp1_BRESP
in moMEM_Mp1_BRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:163
Role_Themisto.moMEM_Mp1_WVALID
out moMEM_Mp1_WVALIDstd_ulogic
Definition: Role.vhdl:160
Role_Themisto.dpBSCAN_update
in dpBSCAN_updatestd_logic
Definition: Role.vhdl:201
Role_Themisto.siNRC_Udp_Data_tdata
in siNRC_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:59
Role_Themisto.moMEM_Mp1_ARLEN
out moMEM_Mp1_ARLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:168
Role_Themisto.soROLE_Nrc_Tcp_Meta_TLAST
out soROLE_Nrc_Tcp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:106
Role_Themisto.soNRC_Udp_Data_tkeep
out soNRC_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:66
Role_Themisto.siNRC_Tcp_Data_tlast
in siNRC_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:91
Role_Themisto.siMEM_Mp0_WrSts_tready
out siMEM_Mp0_WrSts_treadystd_ulogic
Definition: Role.vhdl:139
Role_Themisto.dpBSCAN_runtest
in dpBSCAN_runteststd_logic
Definition: Role.vhdl:206
Role_Themisto.siMEM_Mp0_WrSts_tvalid
in siMEM_Mp0_WrSts_tvalidstd_ulogic
Definition: Role.vhdl:138
Role_Themisto.soMEM_Mp0_Write_tvalid
out soMEM_Mp0_Write_tvalidstd_ulogic
Definition: Role.vhdl:144
Role_Themisto.moMEM_Mp1_ARADDR
out moMEM_Mp1_ARADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:167
Role_Themisto.poVoid
out poVoidstd_ulogic
Definition: Role.vhdl:213
Role_Themisto.moMEM_Mp1_AWREADY
in moMEM_Mp1_AWREADYstd_ulogic
Definition: Role.vhdl:156
Role_Themisto.poROL_Nrc_Udp_Rx_ports
out poROL_Nrc_Udp_Rx_portsstd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:71
Role_Themisto.siMEM_Mp0_Read_tlast
in siMEM_Mp0_Read_tlaststd_ulogic
Definition: Role.vhdl:129
Role_Themisto.dpBSCAN_tck
in dpBSCAN_tckstd_logic
Definition: Role.vhdl:205
Role_Themisto.soNRC_Tcp_Data_tvalid
out soNRC_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:96
topFMKU60.poDDR4_Mem_Mc0_Reset_n
out poDDR4_Mem_Mc0_Reset_nstd_ulogic
Definition: top.vhdl:149
topFMKU60.pioPSOC_Emif_Data
inout pioPSOC_Emif_Datastd_ulogic_vector( gEmifDataWidth- 1 downto 0)
Definition: top.vhdl:126
topFMKU60.poDDR4_Mem_Mc0_Odt
out poDDR4_Mem_Mc0_Odtstd_ulogic
Definition: top.vhdl:145
topFMKU60.poDDR4_Mem_Mc0_Act_n
out poDDR4_Mem_Mc0_Act_nstd_ulogic
Definition: top.vhdl:140
topFMKU60.piPSOC_Emif_Addr
in piPSOC_Emif_Addrstd_ulogic_vector( gEmifAddrWidth- 1 downto 0)
Definition: top.vhdl:125
topFMKU60.piPSOC_Emif_Clk
in piPSOC_Emif_Clkstd_ulogic
Definition: top.vhdl:120
topFMKU60.pioDDR4_Mem_Mc0_Dqs_n
inout pioDDR4_Mem_Mc0_Dqs_nstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:139
topFMKU60.piPSOC_Emif_Cs_n
in piPSOC_Emif_Cs_nstd_ulogic
Definition: top.vhdl:121
topFMKU60.gBitstreamUsage
gBitstreamUsagestring := "flash"
Definition: top.vhdl:78
topFMKU60.poDDR4_Mem_Mc1_Ck_n
out poDDR4_Mem_Mc1_Ck_nstd_ulogic
Definition: top.vhdl:166
topFMKU60.pioDDR4_Mem_Mc0_DmDbi_n
inout pioDDR4_Mem_Mc0_DmDbi_nstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:136
topFMKU60.gEmifDataWidth
gEmifDataWidthinteger :=8
Definition: top.vhdl:87
topFMKU60.piCLKT_Usr1Clk_n
in piCLKT_Usr1Clk_nstd_ulogic
Definition: top.vhdl:114
topFMKU60.poDDR4_Mem_Mc0_Ck_n
out poDDR4_Mem_Mc0_Ck_nstd_ulogic
Definition: top.vhdl:148
topFMKU60.piCLKT_10GeClk_p
in piCLKT_10GeClk_pstd_ulogic
Definition: top.vhdl:107
topFMKU60.poDDR4_Mem_Mc0_Ck_p
out poDDR4_Mem_Mc0_Ck_pstd_ulogic
Definition: top.vhdl:147
topFMKU60.piPSOC_Emif_AdS_n
in piPSOC_Emif_AdS_nstd_ulogic
Definition: top.vhdl:124
topFMKU60.piPSOC_Emif_We_n
in piPSOC_Emif_We_nstd_ulogic
Definition: top.vhdl:122
topFMKU60.poDDR4_Mem_Mc0_Adr
out poDDR4_Mem_Mc0_Adrstd_ulogic_vector(16 downto 0)
Definition: top.vhdl:141
topFMKU60.poLED_HeartBeat_n
out poLED_HeartBeat_nstd_ulogic
Definition: top.vhdl:131
topFMKU60.piPSOC_Emif_Oe_n
in piPSOC_Emif_Oe_nstd_ulogic
Definition: top.vhdl:123
topFMKU60.gTopDateMonth
gTopDateMonthstDate :=8d"00"
Definition: top.vhdl:82
topFMKU60.pioDDR4_Mem_Mc1_Dqs_n
inout pioDDR4_Mem_Mc1_Dqs_nstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:157
topFMKU60.piCLKT_Mem0Clk_n
in piCLKT_Mem0Clk_nstd_ulogic
Definition: top.vhdl:98
topFMKU60.pioDDR4_Mem_Mc1_Dq
inout pioDDR4_Mem_Mc1_Dqstd_ulogic_vector(71 downto 0)
Definition: top.vhdl:155
topFMKU60.pioDDR4_Mem_Mc1_DmDbi_n
inout pioDDR4_Mem_Mc1_DmDbi_nstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:154
topFMKU60.piCLKT_Usr0Clk_n
in piCLKT_Usr0Clk_nstd_ulogic
Definition: top.vhdl:112
topFMKU60.pioDDR4_Mem_Mc0_Dq
inout pioDDR4_Mem_Mc0_Dqstd_ulogic_vector(71 downto 0)
Definition: top.vhdl:137
topFMKU60.poDDR4_Mem_Mc1_Cke
out poDDR4_Mem_Mc1_Ckestd_ulogic
Definition: top.vhdl:162
topFMKU60.piCLKT_Mem1Clk_p
in piCLKT_Mem1Clk_pstd_ulogic
Definition: top.vhdl:101
topFMKU60.pioDDR4_Mem_Mc0_Dqs_p
inout pioDDR4_Mem_Mc0_Dqs_pstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:138
topFMKU60.poDDR4_Mem_Mc1_Adr
out poDDR4_Mem_Mc1_Adrstd_ulogic_vector(16 downto 0)
Definition: top.vhdl:159
topFMKU60.gTopDateDay
gTopDateDaystDate :=8d"00"
Definition: top.vhdl:83
topFMKU60.gSecurityPriviledges
gSecurityPriviledgesstring := "super"
Definition: top.vhdl:79
topFMKU60.poDDR4_Mem_Mc1_Ck_p
out poDDR4_Mem_Mc1_Ck_pstd_ulogic
Definition: top.vhdl:165
topFMKU60.gEmifAddrWidth
gEmifAddrWidthinteger :=8
Definition: top.vhdl:85
topFMKU60.piCLKT_Usr1Clk_p
in piCLKT_Usr1Clk_pstd_ulogic
Definition: top.vhdl:115
topFMKU60.poDDR4_Mem_Mc1_Cs_n
out poDDR4_Mem_Mc1_Cs_nstd_ulogic
Definition: top.vhdl:164
topFMKU60.poDDR4_Mem_Mc0_Bg
out poDDR4_Mem_Mc0_Bgstd_ulogic_vector(1 downto 0)
Definition: top.vhdl:143
topFMKU60.piECON_Eth_10Ge0_p
in piECON_Eth_10Ge0_pstd_ulogic
Definition: top.vhdl:173
topFMKU60.poDDR4_Mem_Mc0_Cs_n
out poDDR4_Mem_Mc0_Cs_nstd_ulogic
Definition: top.vhdl:146
topFMKU60.piCLKT_Usr0Clk_p
in piCLKT_Usr0Clk_pstd_ulogic
Definition: top.vhdl:113
topFMKU60.poECON_Eth_10Ge0_n
out poECON_Eth_10Ge0_nstd_ulogic
Definition: top.vhdl:174
topFMKU60.piECON_Eth_10Ge0_n
in piECON_Eth_10Ge0_nstd_ulogic
Definition: top.vhdl:172
topFMKU60.piPSOC_Fcfg_Rst_n
in piPSOC_Fcfg_Rst_nstd_ulogic
Definition: top.vhdl:93
topFMKU60.gTopDateYear
gTopDateYearstDate :=8d"00"
Definition: top.vhdl:81
topFMKU60.piCLKT_Mem0Clk_p
in piCLKT_Mem0Clk_pstd_ulogic
Definition: top.vhdl:99
topFMKU60.poECON_Eth_10Ge0_p
out poECON_Eth_10Ge0_pstd_ulogic
Definition: top.vhdl:177
topFMKU60.poDDR4_Mem_Mc1_Act_n
out poDDR4_Mem_Mc1_Act_nstd_ulogic
Definition: top.vhdl:158
topFMKU60.pioDDR4_Mem_Mc1_Dqs_p
inout pioDDR4_Mem_Mc1_Dqs_pstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:156
topFMKU60.poDDR4_Mem_Mc0_Ba
out poDDR4_Mem_Mc0_Bastd_ulogic_vector(1 downto 0)
Definition: top.vhdl:142
topFMKU60.poDDR4_Mem_Mc1_Ba
out poDDR4_Mem_Mc1_Bastd_ulogic_vector(1 downto 0)
Definition: top.vhdl:160
topFMKU60.poDDR4_Mem_Mc1_Bg
out poDDR4_Mem_Mc1_Bgstd_ulogic_vector(1 downto 0)
Definition: top.vhdl:161
topFMKU60.poDDR4_Mem_Mc1_Odt
out poDDR4_Mem_Mc1_Odtstd_ulogic
Definition: top.vhdl:163
topFMKU60.poDDR4_Mem_Mc1_Reset_n
out poDDR4_Mem_Mc1_Reset_nstd_ulogic
Definition: top.vhdl:167
topFMKU60.piCLKT_10GeClk_n
in piCLKT_10GeClk_nstd_ulogic
Definition: top.vhdl:106
topFMKU60.poDDR4_Mem_Mc0_Cke
out poDDR4_Mem_Mc0_Ckestd_ulogic
Definition: top.vhdl:144
topFMKU60.piCLKT_Mem1Clk_n
in piCLKT_Mem1Clk_nstd_ulogic
Definition: top.vhdl:100