cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
top.vhdl
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1 -- *******************************************************************************
2 -- * Copyright 2016 -- 2022 IBM Corporation
3 -- *
4 -- * Licensed under the Apache License, Version 2.0 (the "License");
5 -- * you may not use this file except in compliance with the License.
6 -- * You may obtain a copy of the License at
7 -- *
8 -- * http://www.apache.org/licenses/LICENSE-2.0
9 -- *
10 -- * Unless required by applicable law or agreed to in writing, software
11 -- * distributed under the License is distributed on an "AS IS" BASIS,
12 -- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 -- * See the License for the specific language governing permissions and
14 -- * limitations under the License.
15 -- *******************************************************************************
16 
17 
18 -- *****************************************************************************
19 -- *
20 -- * cloudFPGA
21 -- *
22 -- *----------------------------------------------------------------------------
23 -- *
24 -- * Title : Generic top level design for a cloudFPGA project implemented on a
25 -- * FMKU60 module and based on a shell 'Kale'.
26 -- *
27 -- * Created : Feb. 2018
28 -- * Authors : Francois Abel <fab@zurich.ibm.com>
29 -- *
30 -- * Device : xcku060-ffva1156-2-i
31 -- * Tools : Vivado v2016.4 / 2017.4 / 2019.2 (64-bit)
32 -- *
33 -- * Dependencies : cloudFPGA Shell IP v1.0.
34 -- *
35 -- * Description : This top level implements a shell af type 'Kale' (Shell_Kale)
36 -- * and a corresponding role of type 'Kale' (Role_Kale). The user is expected
37 -- * to specify the architecture of the role while the architecture of the
38 -- * shell is provided by the cloudFPGA Development Kit (cFDK).
39 -- *
40 -- * Warning:
41 -- * This file is copied in the directory 'cFp_<ProjectName>/TOP/hdl' every
42 -- * time the script 'cFPBuild' is invoked by the user. This happens when the
43 -- * project is built the first time, but also upon any update required by
44 -- * the cFDK.
45 -- *
46 -- * Clocking:
47 -- * The shell and the role operate with a source synchronous clock called
48 -- * 'sSHL_156_25Clk'. This clock is generated by the 10Gb PCS/PMA subsystem
49 -- * and is also listed as follows after synthesis:
50 -- * SHELL/../xpcs/U0/ten_gig_eth_pcs_pma_shared_clock_reset_block/CLK
51 -- *****************************************************************************
52 
53 
54 --******************************************************************************
55 --** CONTEXT CLAUSE ** FMKU60 FLASH
56 --******************************************************************************
57 library IEEE;
58 use IEEE.std_logic_1164.all;
59 use IEEE.numeric_std.all;
60 
61 library UNISIM;
62 use UNISIM.vcomponents.all;
63 
64 --library WORK;
65 --use WORK.topFlash_pkg.all; -- Not used
66 
67 library XIL_DEFAULTLIB;
68 use XIL_DEFAULTLIB.topFMKU_pkg.all;
69 
70 
71 --******************************************************************************
72 --** ENTITY ** FMKU60 FLASH
73 --******************************************************************************
74 
75 entity topFMKU60 is
76  generic (
77  -- Synthesis parameters ----------------------
78  gBitstreamUsage : string := "flash"; -- "user" or "flash"
79  gSecurityPriviledges : string := "super"; -- "user" or "super"
80  -- Build date --------------------------------
81  gTopDateYear : stDate := 8d"00"; -- Not used w/ Xilinx parts (see USR_ACCESSE2)
82  gTopDateMonth : stDate := 8d"00"; -- Not used w/ Xilinx parts (see USR_ACCESSE2)
83  gTopDateDay : stDate := 8d"00"; -- Not used w/ Xilinx parts (see USR_ACCESSE2)
84  -- External Memory Interface (EMIF) ----------
85  gEmifAddrWidth : integer := 8;
86  gEmifDataWidth : integer := 8
87  );
88  port (
89  ------------------------------------------------------
90  -- PSOC / FPGA Configuration Interface (Fcfg)
91  -- System reset controlled by the PSoC.
92  ------------------------------------------------------
93  piPSOC_Fcfg_Rst_n : in std_ulogic;
94 
95  ------------------------------------------------------
96  -- CLKT / DRAM clocks 0 and 1 (Mem. Channels 0 and 1)
97  ------------------------------------------------------
98  piCLKT_Mem0Clk_n : in std_ulogic;
99  piCLKT_Mem0Clk_p : in std_ulogic;
100  piCLKT_Mem1Clk_n : in std_ulogic;
101  piCLKT_Mem1Clk_p : in std_ulogic;
102 
103  ------------------------------------------------------
104  -- CLKT / GTH clocks (10Ge, Sata, Gtio Interfaces)
105  ------------------------------------------------------
106  piCLKT_10GeClk_n : in std_ulogic;
107  piCLKT_10GeClk_p : in std_ulogic;
108 
109  ------------------------------------------------------
110  -- CLKT / User clocks 0 and 1 (156.25MHz, 250MHz)
111  ------------------------------------------------------
112  piCLKT_Usr0Clk_n : in std_ulogic;
113  piCLKT_Usr0Clk_p : in std_ulogic;
114  piCLKT_Usr1Clk_n : in std_ulogic;
115  piCLKT_Usr1Clk_p : in std_ulogic;
116 
117  ------------------------------------------------------
118  -- PSOC / External Memory Interface (Emif)
119  ------------------------------------------------------
120  piPSOC_Emif_Clk : in std_ulogic;
121  piPSOC_Emif_Cs_n : in std_ulogic;
122  piPSOC_Emif_We_n : in std_ulogic;
123  piPSOC_Emif_Oe_n : in std_ulogic;
124  piPSOC_Emif_AdS_n : in std_ulogic;
125  piPSOC_Emif_Addr : in std_ulogic_vector(gEmifAddrWidth-1 downto 0);
126  pioPSOC_Emif_Data : inout std_ulogic_vector(gEmifDataWidth-1 downto 0);
127 
128  ------------------------------------------------------
129  -- LED / Heart Beat Interface (Yellow LED)
130  ------------------------------------------------------
131  poLED_HeartBeat_n : out std_ulogic;
132 
133  ------------------------------------------------------
134  -- -- DDR(4) / Memory Channel 0 Interface (Mc0)
135  ------------------------------------------------------
136  pioDDR4_Mem_Mc0_DmDbi_n : inout std_ulogic_vector( 8 downto 0);
137  pioDDR4_Mem_Mc0_Dq : inout std_ulogic_vector(71 downto 0);
138  pioDDR4_Mem_Mc0_Dqs_p : inout std_ulogic_vector( 8 downto 0);
139  pioDDR4_Mem_Mc0_Dqs_n : inout std_ulogic_vector( 8 downto 0);
140  poDDR4_Mem_Mc0_Act_n : out std_ulogic;
141  poDDR4_Mem_Mc0_Adr : out std_ulogic_vector(16 downto 0);
142  poDDR4_Mem_Mc0_Ba : out std_ulogic_vector( 1 downto 0);
143  poDDR4_Mem_Mc0_Bg : out std_ulogic_vector( 1 downto 0);
144  poDDR4_Mem_Mc0_Cke : out std_ulogic;
145  poDDR4_Mem_Mc0_Odt : out std_ulogic;
146  poDDR4_Mem_Mc0_Cs_n : out std_ulogic;
147  poDDR4_Mem_Mc0_Ck_p : out std_ulogic;
148  poDDR4_Mem_Mc0_Ck_n : out std_ulogic;
149  poDDR4_Mem_Mc0_Reset_n : out std_ulogic;
150 
151  ------------------------------------------------------
152  -- DDR(4) / Memory Channel 1 Interface (Mc1)
153  ------------------------------------------------------
154  pioDDR4_Mem_Mc1_DmDbi_n : inout std_ulogic_vector( 8 downto 0);
155  pioDDR4_Mem_Mc1_Dq : inout std_ulogic_vector(71 downto 0);
156  pioDDR4_Mem_Mc1_Dqs_p : inout std_ulogic_vector( 8 downto 0);
157  pioDDR4_Mem_Mc1_Dqs_n : inout std_ulogic_vector( 8 downto 0);
158  poDDR4_Mem_Mc1_Act_n : out std_ulogic;
159  poDDR4_Mem_Mc1_Adr : out std_ulogic_vector(16 downto 0);
160  poDDR4_Mem_Mc1_Ba : out std_ulogic_vector( 1 downto 0);
161  poDDR4_Mem_Mc1_Bg : out std_ulogic_vector( 1 downto 0);
162  poDDR4_Mem_Mc1_Cke : out std_ulogic;
163  poDDR4_Mem_Mc1_Odt : out std_ulogic;
164  poDDR4_Mem_Mc1_Cs_n : out std_ulogic;
165  poDDR4_Mem_Mc1_Ck_p : out std_ulogic;
166  poDDR4_Mem_Mc1_Ck_n : out std_ulogic;
167  poDDR4_Mem_Mc1_Reset_n : out std_ulogic;
168 
169  ------------------------------------------------------
170  -- ECON / Edge Connector Interface (SPD08-200)
171  ------------------------------------------------------
172  piECON_Eth_10Ge0_n : in std_ulogic;
173  piECON_Eth_10Ge0_p : in std_ulogic;
174  poECON_Eth_10Ge0_n : out std_ulogic;
175  poECON_Eth_10Ge0_p : out std_ulogic
176 
177  );
178 
179 end topFMKU60;
180 
181 
182 --*****************************************************************************
183 --** ARCHITECTURE ** FMKU60 FLASH
184 --*****************************************************************************
185 architecture structural of topFMKU60 is
186 
187  --------------------------------------------------------n
188  -- [TOP] SIGNAL DECLARATIONS
189  --------------------------------------------------------
190 
191  -- Global User Clocks ----------------------------------
192  signal sTOP_156_25Clk : std_ulogic;
193  signal sTOP_250_00Clk : std_ulogic;
194 
195  -- Global Reset ----------------------------------------
196  signal sTOP_156_25Rst_n : std_ulogic;
197  signal sTOP_156_25Rst : std_ulogic;
198 
199  -- Global Source Synchronous Clock and Reset -----------
200  signal sSHL_156_25Clk : std_ulogic;
201  signal sSHL_156_25Rst : std_ulogic;
202 
203  -- Bitstream Identification Value ----------------------
204  signal sTOP_Timestamp : stTimeStamp;
205 
206  --------------------------------------------------------
207  -- SIGNAL DECLARATIONS : [SHELL/Nts] <--> [ROLE/Nts]
208  --------------------------------------------------------
209 
210  -- ROLE-->SHELL / Nts / Udp / Tx Data Interfaces
211  ---- Axi4-Stream UDP Data ---------------
212  signal ssROL_SHL_Nts_Udp_Data_tdata : std_ulogic_vector( 63 downto 0);
213  signal ssROL_SHL_Nts_Udp_Data_tkeep : std_ulogic_vector( 7 downto 0);
214  signal ssROL_SHL_Nts_Udp_Data_tlast : std_ulogic;
215  signal ssROL_SHL_Nts_Udp_Data_tvalid : std_ulogic;
216  signal ssROL_SHL_Nts_Udp_Data_tready : std_ulogic;
217  ---- Axi4-Stream UDP Metadata -----------
218  signal ssROL_SHL_Nts_Udp_Meta_tdata : std_ulogic_vector( 95 downto 0);
219  signal ssROL_SHL_Nts_Udp_Meta_tvalid : std_ulogic;
220  signal ssROL_SHL_Nts_Udp_Meta_tready : std_ulogic;
221  ---- Axis4Stream UDP Data Length ---------
222  signal ssROL_SHL_Nts_Udp_DLen_tdata : std_ulogic_vector( 15 downto 0);
223  signal ssROL_SHL_Nts_Udp_DLen_tvalid : std_ulogic;
224  signal ssROL_SHL_Nts_Udp_DLen_tready : std_ulogic;
225 
226  -- SHELL-->ROLE / Nts / Udp / Rx Data Interfaces
227  ---- UDP Data (AXI4S) --------------------
228  signal ssSHL_ROL_Nts_Udp_Data_tdata : std_ulogic_vector( 63 downto 0);
229  signal ssSHL_ROL_Nts_Udp_Data_tkeep : std_ulogic_vector( 7 downto 0);
230  signal ssSHL_ROL_Nts_Udp_Data_tlast : std_ulogic;
231  signal ssSHL_ROL_Nts_Udp_Data_tvalid : std_ulogic;
232  signal ssSHL_ROL_Nts_Udp_Data_tready : std_ulogic;
233  ---- Axi4-Stream UDP Metadata -----------
234  signal ssSHL_ROL_Nts_Udp_Meta_tdata : std_ulogic_vector( 95 downto 0);
235  signal ssSHL_ROL_Nts_Udp_Meta_tvalid : std_ulogic;
236  signal ssSHL_ROL_Nts_Udp_Meta_tready : std_ulogic;
237 
238  -- SHELL-->ROLE / Nts/ Udp / Rx Ctrl Interfaces
239  ---- Axi4-Stream UDP Listen Request -----
240  signal ssROL_SHL_Nts_Udp_LsnReq_tdata : std_ulogic_vector( 15 downto 0);
241  signal ssROL_SHL_Nts_Udp_LsnReq_tvalid : std_ulogic;
242  signal ssROL_SHL_Nts_Udp_LsnReq_tready : std_ulogic;
243  ---- Axi4-Stream UDP Listen Reply --------
244  signal ssSHL_ROL_Nts_Udp_LsnRep_tdata : std_ulogic_vector( 7 downto 0);
245  signal ssSHL_ROL_Nts_Udp_LsnRep_tvalid : std_ulogic;
246  signal ssSHL_ROL_Nts_Udp_LsnRep_tready : std_ulogic;
247  ---- Axi4-Stream UDP Close Request ------
248  signal ssROL_SHL_Nts_Udp_ClsReq_tdata : std_ulogic_vector( 15 downto 0);
249  signal ssROL_SHL_Nts_Udp_ClsReq_tvalid : std_ulogic;
250  signal ssROL_SHL_Nts_Udp_ClsReq_tready : std_ulogic;
251  ---- Axi4-Stream UDP Close Reply ---------
252  signal ssSHL_ROL_Nts_Udp_ClsRep_tdata : std_ulogic_vector( 7 downto 0);
253  signal ssSHL_ROL_Nts_Udp_ClsRep_tvalid : std_ulogic;
254  signal ssSHL_ROL_Nts_Udp_ClsRep_tready : std_ulogic;
255 
256  -- ROLE-->SHELL / Nts / Tcp / Tx Data Interfaces
257  ---- Axi4-Stream TCP Data ----------------
258  signal ssROL_SHL_Nts_Tcp_Data_tdata : std_ulogic_vector( 63 downto 0);
259  signal ssROL_SHL_Nts_Tcp_Data_tkeep : std_ulogic_vector( 7 downto 0);
260  signal ssROL_SHL_Nts_Tcp_Data_tlast : std_ulogic;
261  signal ssROL_SHL_Nts_Tcp_Data_tvalid : std_ulogic;
262  signal ssROL_SHL_Nts_Tcp_Data_tready : std_ulogic;
263  ---- Axi4-Stream TCP Send Request --------
264  signal ssROL_SHL_Nts_Tcp_SndReq_tdata : std_ulogic_vector( 31 downto 0);
265  signal ssROL_SHL_Nts_Tcp_SndReq_tvalid : std_ulogic;
266  signal ssROL_SHL_Nts_Tcp_SndReq_tready : std_ulogic;
267  ---- Axi4-Stream TCP Send Reply ----------
268  signal ssSHL_ROL_Nts_Tcp_SndRep_tdata : std_ulogic_vector( 55 downto 0);
269  signal ssSHL_ROL_Nts_Tcp_SndRep_tvalid : std_ulogic;
270  signal ssSHL_ROL_Nts_Tcp_SndRep_tready : std_ulogic;
271 
272  -- SHELL-->ROLE / Nts / Tcp / Rx Data Interfaces
273  ---- Axi4-Stream TCP Data -----------------
274  signal ssSHL_ROL_Nts_Tcp_Data_tdata : std_ulogic_vector( 63 downto 0);
275  signal ssSHL_ROL_Nts_Tcp_Data_tkeep : std_ulogic_vector( 7 downto 0);
276  signal ssSHL_ROL_Nts_Tcp_Data_tlast : std_ulogic;
277  signal ssSHL_ROL_Nts_Tcp_Data_tvalid : std_ulogic;
278  signal ssSHL_ROL_Nts_Tcp_Data_tready : std_ulogic;
279  ---- Axi4-Stream TCP Metadata ------------
280  signal ssSHL_ROL_Nts_Tcp_Meta_tdata : std_ulogic_vector( 15 downto 0);
281  signal ssSHL_ROL_Nts_Tcp_Meta_tvalid : std_ulogic;
282  signal ssSHL_ROL_Nts_Tcp_Meta_tready : std_ulogic;
283  ---- Axi4-Stream TCP Data Notification ---
284  signal ssSHL_ROL_Nts_Tcp_Notif_tdata : std_ulogic_vector(7+96 downto 0); -- 8-bits boundary
285  signal ssSHL_ROL_Nts_Tcp_Notif_tvalid : std_ulogic;
286  signal ssSHL_ROL_Nts_Tcp_Notif_tready : std_ulogic;
287  ---- Axi4-Stream TCP Data Request --------
288  signal ssROL_SHL_Nts_Tcp_DReq_tdata : std_ulogic_vector( 31 downto 0);
289  signal ssROL_SHL_Nts_Tcp_DReq_tvalid : std_ulogic;
290  signal ssROL_SHL_Nts_Tcp_DReq_tready : std_ulogic;
291 
292  -- ROLE-->SHELL / Nts / Tcp / TxP Ctlr Interfaces
293  ---- Axi4-Stream TCP Open Session Request
294  signal ssROL_SHL_Nts_Tcp_OpnReq_tdata : std_ulogic_vector( 47 downto 0);
295  signal ssROL_SHL_Nts_Tcp_OpnReq_tvalid : std_ulogic;
296  signal ssROL_SHL_Nts_Tcp_OpnReq_tready : std_ulogic;
297  ---- Axi4-Stream TCP Open Session Reply
298  signal ssSHL_ROL_Nts_Tcp_OpnRep_tdata : std_ulogic_vector( 23 downto 0);
299  signal ssSHL_ROL_Nts_Tcp_OpnRep_tvalid : std_ulogic;
300  signal ssSHL_ROL_Nts_Tcp_OpnRep_tready : std_ulogic;
301  ---- Axi4-Stream TCP Close Request ------
302  signal ssROL_SHL_Nts_Tcp_ClsReq_tdata : std_ulogic_vector( 15 downto 0);
303  signal ssROL_SHL_Nts_Tcp_ClsReq_tvalid : std_ulogic;
304  signal ssROL_SHL_Nts_Tcp_ClsReq_tready : std_ulogic;
305 
306  -- SHELL-->ROLE / Nts / Tcp / Rx Ctlr Interfaces
307  ---- Axi4-Stream TCP Listen Request ----
308  signal ssROL_SHL_Nts_Tcp_LsnReq_tdata : std_ulogic_vector( 15 downto 0);
309  signal ssROL_SHL_Nts_Tcp_LsnReq_tvalid : std_ulogic;
310  signal ssROL_SHL_Nts_Tcp_LsnReq_tready : std_ulogic;
311  ---- Axi4-Stream TCP Listen Rep --------
312  signal ssSHL_ROL_Nts_Tcp_LsnRep_tdata : std_ulogic_vector( 7 downto 0);
313  signal ssSHL_ROL_Nts_Tcp_LsnRep_tvalid : std_ulogic;
314  signal ssSHL_ROL_Nts_Tcp_LsnRep_tready : std_ulogic;
315 
316  --------------------------------------------------------
317  -- SIGNAL DECLARATIONS : [SHELL/Mem] <--> [ROLE/Mem]
318  --------------------------------------------------------
319  -- Memory Port #0 ------------------------------
320  ------ Stream Read Command --------------
321  signal ssROL_SHL_Mem_Mp0_RdCmd_tdata : std_ulogic_vector( 79 downto 0);
322  signal ssROL_SHL_Mem_Mp0_RdCmd_tvalid : std_ulogic;
323  signal ssROL_SHL_Mem_Mp0_RdCmd_tready : std_ulogic;
324  ------ Stream Read Status ----------------
325  signal ssSHL_ROL_Mem_Mp0_RdSts_tdata : std_ulogic_vector( 7 downto 0);
326  signal ssSHL_ROL_Mem_Mp0_RdSts_tvalid : std_ulogic;
327  signal ssSHL_ROL_Mem_Mp0_RdSts_tready : std_ulogic;
328  ------ Stream Data Output Channel --------
329  signal ssSHL_ROL_Mem_Mp0_Read_tdata : std_ulogic_vector(511 downto 0);
330  signal ssSHL_ROL_Mem_Mp0_Read_tkeep : std_ulogic_vector( 63 downto 0);
331  signal ssSHL_ROL_Mem_Mp0_Read_tlast : std_ulogic;
332  signal ssSHL_ROL_Mem_Mp0_Read_tvalid : std_ulogic;
333  signal ssSHL_ROL_Mem_Mp0_Read_tready : std_ulogic;
334  ------ Stream Write Command --------------
335  signal ssROL_SHL_Mem_Mp0_WrCmd_tdata : std_ulogic_vector( 79 downto 0);
336  signal ssROL_SHL_Mem_Mp0_WrCmd_tvalid : std_ulogic;
337  signal ssROL_SHL_Mem_Mp0_WrCmd_tready : std_ulogic;
338  ------ Stream Write Status ---------------
339  signal ssSHL_ROL_Mem_Mp0_WrSts_tdata : std_ulogic_vector( 7 downto 0);
340  signal ssSHL_ROL_Mem_Mp0_WrSts_tvalid : std_ulogic;
341  signal ssSHL_ROL_Mem_Mp0_WrSts_tready : std_ulogic;
342  ------ Stream Data Input Channel ---------
343  signal ssROL_SHL_Mem_Mp0_Write_tdata : std_ulogic_vector(511 downto 0);
344  signal ssROL_SHL_Mem_Mp0_Write_tkeep : std_ulogic_vector( 63 downto 0);
345  signal ssROL_SHL_Mem_Mp0_Write_tlast : std_ulogic;
346  signal ssROL_SHL_Mem_Mp0_Write_tvalid : std_ulogic;
347  signal ssROL_SHL_Mem_Mp0_Write_tready : std_ulogic;
348  -- Memory Port #1 ------------------------------
349  signal smROL_SHL_Mem_Mp1_AWID : std_ulogic_vector(3 downto 0);
350  signal smROL_SHL_Mem_Mp1_AWADDR : std_ulogic_vector(32 downto 0);
351  signal smROL_SHL_Mem_Mp1_AWLEN : std_ulogic_vector(7 downto 0);
352  signal smROL_SHL_Mem_Mp1_AWSIZE : std_ulogic_vector(2 downto 0);
353  signal smROL_SHL_Mem_Mp1_AWBURST : std_ulogic_vector(1 downto 0);
354  signal smROL_SHL_Mem_Mp1_AWVALID : std_ulogic;
355  signal smROL_SHL_Mem_Mp1_AWREADY : std_ulogic;
356  signal smROL_SHL_Mem_Mp1_WDATA : std_ulogic_vector(511 downto 0);
357  signal smROL_SHL_Mem_Mp1_WSTRB : std_ulogic_vector(63 downto 0);
358  signal smROL_SHL_Mem_Mp1_WLAST : std_ulogic;
359  signal smROL_SHL_Mem_Mp1_WVALID : std_ulogic;
360  signal smROL_SHL_Mem_Mp1_WREADY : std_ulogic;
361  signal smROL_SHL_Mem_Mp1_BID : std_ulogic_vector(3 downto 0);
362  signal smROL_SHL_Mem_Mp1_BRESP : std_ulogic_vector(1 downto 0);
363  signal smROL_SHL_Mem_Mp1_BVALID : std_ulogic;
364  signal smROL_SHL_Mem_Mp1_BREADY : std_ulogic;
365  signal smROL_SHL_Mem_Mp1_ARID : std_ulogic_vector(3 downto 0);
366  signal smROL_SHL_Mem_Mp1_ARADDR : std_ulogic_vector(32 downto 0);
367  signal smROL_SHL_Mem_Mp1_ARLEN : std_ulogic_vector(7 downto 0);
368  signal smROL_SHL_Mem_Mp1_ARSIZE : std_ulogic_vector(2downto 0);
369  signal smROL_SHL_Mem_Mp1_ARBURST : std_ulogic_vector(1 downto 0);
370  signal smROL_SHL_Mem_Mp1_ARVALID : std_ulogic;
371  signal smROL_SHL_Mem_Mp1_ARREADY : std_ulogic;
372  signal smROL_SHL_Mem_Mp1_RID : std_ulogic_vector(3 downto 0);
373  signal smROL_SHL_Mem_Mp1_RDATA : std_ulogic_vector(511 downto 0);
374  signal smROL_SHL_Mem_Mp1_RRESP : std_ulogic_vector(1 downto 0);
375  signal smROL_SHL_Mem_Mp1_RLAST : std_ulogic;
376  signal smROL_SHL_Mem_Mp1_RVALID : std_ulogic;
377  signal smROL_SHL_Mem_Mp1_RREADY : std_ulogic;
378 
379  --------------------------------------------------------
380  -- SIGNAL DECLARATIONS : [MMIO] <--> [ROLE]
381  --------------------------------------------------------
382  ---- [PHY_RESET] -------------------------
383  signal sSHL_ROL_Mmio_Ly7Rst : std_ulogic;
384  ---- [PHY_ENABLE] ------------------------
385  signal sSHL_ROL_Mmio_Ly7En : std_ulogic;
386  ---- DIAG_CTRL_1 -------------------------
387  signal sSHL_ROL_Mmio_Mc1_MemTestCtrl : std_ulogic_vector( 1 downto 0);
388  ---- DIAG_STAT_1 -------------------------
389  signal sROL_SHL_Mmio_Mc1_MemTestStat : std_ulogic_vector( 1 downto 0);
390  ---- CTRL_2 Register ---------------------
391  signal sSHL_ROL_Mmio_UdpEchoCtrl : std_ulogic_vector( 1 downto 0);
392  signal sSHL_ROL_Mmio_UdpPostDgmEn : std_ulogic;
393  signal sSHL_ROL_Mmio_UdpCaptDgmEn : std_ulogic;
394  signal sSHL_ROL_Mmio_TcpEchoCtrl : std_ulogic_vector( 1 downto 0);
395  signal sSHL_ROL_Mmio_TcpPostSegEn : std_ulogic;
396  signal sSHL_ROL_Mmio_TcpCaptSegEn : std_ulogic;
397  ---- APP_RDROL[0:1] ---------------------
398  signal sROL_SHL_Mmio_RdReg : std_ulogic_vector( 15 downto 0);
399  ---- APP_WRROL[0:1] ---------------------
400  signal sSHL_ROL_Mmio_WrReg : std_ulogic_vector( 15 downto 0);
401  -- Delayed reset counter
402  signal sRstDelayCounter : std_ulogic_vector(5 downto 0);
403 
404  --===========================================================================
405  --== COMPONENT DECLARATIONS
406  --===========================================================================
407 
408  -- [INFO] The SHELL component is declared in the corresponding TOP package.
409  -- not this time
410  -- to declare the component in the pkg seems not to work for Verilog or .dcp modules
411  component Shell_Kale
412  generic (
413  gSecurityPriviledges : string := "super"; -- Can be "user" or "super"
414  gBitstreamUsage : string := "flash"; -- Can be "user" or "flash"
415  gMmioAddrWidth : integer := 8; -- Default is 8-bits
416  gMmioDataWidth : integer := 8 -- Default is 8-bits
417  );
418  port (
419  ------------------------------------------------------
420  -- TOP / Input Clocks and Resets from topFMKU60
421  ------------------------------------------------------
422  piTOP_156_25Rst : in std_ulogic;
423  piTOP_156_25Clk : in std_ulogic;
424  ------------------------------------------------------
425  -- TOP / Bitstream Identification
426  ------------------------------------------------------
427  piTOP_Timestamp : in std_ulogic_vector( 31 downto 0);
428  ------------------------------------------------------
429  -- CLKT / Clock Tree Interface
430  ------------------------------------------------------
431  piCLKT_Mem0Clk_n : in std_ulogic;
432  piCLKT_Mem0Clk_p : in std_ulogic;
433  piCLKT_Mem1Clk_n : in std_ulogic;
434  piCLKT_Mem1Clk_p : in std_ulogic;
435  piCLKT_10GeClk_n : in std_ulogic;
436  piCLKT_10GeClk_p : in std_ulogic;
437  ------------------------------------------------------
438  -- PSOC / External Memory Interface (Emif)
439  ------------------------------------------------------
440  piPSOC_Emif_Clk : in std_ulogic;
441  piPSOC_Emif_Cs_n : in std_ulogic;
442  piPSOC_Emif_We_n : in std_ulogic;
443  piPSOC_Emif_Oe_n : in std_ulogic;
444  piPSOC_Emif_AdS_n : in std_ulogic;
445  piPSOC_Emif_Addr : in std_ulogic_vector(gMmioAddrWidth-1 downto 0);
446  pioPSOC_Emif_Data : inout std_ulogic_vector(gMmioDataWidth-1 downto 0);
447  ------------------------------------------------------
448  -- LED / Heart Beat Interface (Yellow LED)
449  ------------------------------------------------------
450  poLED_HeartBeat_n : out std_ulogic;
451  ------------------------------------------------------
452  -- DDR4 / Memory Channel 0 Interface (Mc0)
453  ------------------------------------------------------
454  pioDDR4_Mem_Mc0_DmDbi_n : inout std_ulogic_vector( 8 downto 0);
455  pioDDR4_Mem_Mc0_Dq : inout std_ulogic_vector( 71 downto 0);
456  pioDDR4_Mem_Mc0_Dqs_n : inout std_ulogic_vector( 8 downto 0);
457  pioDDR4_Mem_Mc0_Dqs_p : inout std_ulogic_vector( 8 downto 0);
458  poDDR4_Mem_Mc0_Act_n : out std_ulogic;
459  poDDR4_Mem_Mc0_Adr : out std_ulogic_vector( 16 downto 0);
460  poDDR4_Mem_Mc0_Ba : out std_ulogic_vector( 1 downto 0);
461  poDDR4_Mem_Mc0_Bg : out std_ulogic_vector( 1 downto 0);
462  poDDR4_Mem_Mc0_Cke : out std_ulogic;
463  poDDR4_Mem_Mc0_Odt : out std_ulogic;
464  poDDR4_Mem_Mc0_Cs_n : out std_ulogic;
465  poDDR4_Mem_Mc0_Ck_n : out std_ulogic;
466  poDDR4_Mem_Mc0_Ck_p : out std_ulogic;
467  poDDR4_Mem_Mc0_Reset_n : out std_ulogic;
468  ------------------------------------------------------
469  -- DDR4 / Memory Channel 1 Interface (Mc1)
470  ------------------------------------------------------
471  pioDDR4_Mem_Mc1_DmDbi_n : inout std_ulogic_vector( 8 downto 0);
472  pioDDR4_Mem_Mc1_Dq : inout std_ulogic_vector( 71 downto 0);
473  pioDDR4_Mem_Mc1_Dqs_n : inout std_ulogic_vector( 8 downto 0);
474  pioDDR4_Mem_Mc1_Dqs_p : inout std_ulogic_vector( 8 downto 0);
475  poDDR4_Mem_Mc1_Act_n : out std_ulogic;
476  poDDR4_Mem_Mc1_Adr : out std_ulogic_vector( 16 downto 0);
477  poDDR4_Mem_Mc1_Ba : out std_ulogic_vector( 1 downto 0);
478  poDDR4_Mem_Mc1_Bg : out std_ulogic_vector( 1 downto 0);
479  poDDR4_Mem_Mc1_Cke : out std_ulogic;
480  poDDR4_Mem_Mc1_Odt : out std_ulogic;
481  poDDR4_Mem_Mc1_Cs_n : out std_ulogic;
482  poDDR4_Mem_Mc1_Ck_n : out std_ulogic;
483  poDDR4_Mem_Mc1_Ck_p : out std_ulogic;
484  poDDR4_Mem_Mc1_Reset_n : out std_ulogic;
485  ------------------------------------------------------
486  -- ECON / Edge Connector Interface (SPD08-200)
487  ------------------------------------------------------
488  piECON_Eth_10Ge0_n : in std_ulogic;
489  piECON_Eth_10Ge0_p : in std_ulogic;
490  poECON_Eth_10Ge0_n : out std_ulogic;
491  poECON_Eth_10Ge0_p : out std_ulogic;
492  ------------------------------------------------------
493  -- ROLE / Output Clock and Reset Interfaces
494  ------------------------------------------------------
495  poROL_156_25Clk : out std_ulogic;
496  poROL_156_25Rst : out std_ulogic;
497  ------------------------------------------------------
498  -- ROLE / Nts / Udp / Tx Data Interfaces (.i.e ROLE-->SHELL)
499  ------------------------------------------------------
500  ---- Axi4-Stream UDP Data ---------------
501  siROL_Nts_Udp_Data_tdata : in std_ulogic_vector( 63 downto 0);
502  siROL_Nts_Udp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
503  siROL_Nts_Udp_Data_tlast : in std_ulogic;
504  siROL_Nts_Udp_Data_tvalid : in std_ulogic;
505  siROL_Nts_Udp_Data_tready : out std_ulogic;
506  ---- Axi4-Stream UDP Metadata -----------
507  siROL_Nts_Udp_Meta_tdata : in std_logic_vector( 95 downto 0);
508  siROL_Nts_Udp_Meta_tvalid : in std_ulogic;
509  siROL_Nts_Udp_Meta_tready : out std_ulogic;
510  ---- Axis4Stream UDP Data Length ---------
511  siROL_Nts_Udp_DLen_tdata : in std_logic_vector( 15 downto 0);
512  siROL_Nts_Udp_DLen_tvalid : in std_ulogic;
513  siROL_Nts_Udp_DLen_tready : out std_ulogic;
514  ------------------------------------------------------
515  -- ROLE / Nts / Udp / Rx Data Interfaces (.i.e SHELL-->ROLE)
516  ------------------------------------------------------
517  ---- Axi4-Stream UDP Data ---------------
518  soROL_Nts_Udp_Data_tdata : out std_ulogic_vector( 63 downto 0);
519  soROL_Nts_Udp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
520  soROL_Nts_Udp_Data_tlast : out std_ulogic;
521  soROL_Nts_Udp_Data_tvalid : out std_ulogic;
522  soROL_Nts_Udp_Data_tready : in std_ulogic;
523  ---- Axi4-Stream UDP Metadata -----------
524  soROL_Nts_Udp_Meta_tdata : out std_logic_vector( 95 downto 0);
525  soROL_Nts_Udp_Meta_tvalid : out std_ulogic;
526  soROL_Nts_Udp_Meta_tready : in std_ulogic;
527  ------------------------------------------------------
528  -- ROLE / Nts/ Udp / Rx Ctrl Interfaces (.i.e SHELL<-->ROLE)
529  ------------------------------------------------------
530  ---- Axi4-Stream UDP Listen Request -----
531  siROL_Nts_Udp_LsnReq_tdata : in std_ulogic_vector( 15 downto 0);
532  siROL_Nts_Udp_LsnReq_tvalid : in std_ulogic;
533  siROL_Nts_Udp_LsnReq_tready : out std_ulogic;
534  ---- Axi4-Stream UDP Listen Reply --------
535  soROL_Nts_Udp_LsnRep_tdata : out std_ulogic_vector( 7 downto 0);
536  soROL_Nts_Udp_LsnRep_tvalid : out std_ulogic;
537  soROL_Nts_Udp_LsnRep_tready : in std_ulogic;
538  ---- Axi4-Stream UDP Close Request ------
539  siROL_Nts_Udp_ClsReq_tdata : in std_ulogic_vector( 15 downto 0);
540  siROL_Nts_Udp_ClsReq_tvalid : in std_ulogic;
541  siROL_Nts_Udp_ClsReq_tready : out std_ulogic;
542  ---- Axi4-Stream UDP Close Reply ---------
543  soROL_Nts_Udp_ClsRep_tdata : out std_ulogic_vector( 7 downto 0);
544  soROL_Nts_Udp_ClsRep_tvalid : out std_ulogic;
545  soROL_Nts_Udp_ClsRep_tready : in std_ulogic;
546  ------------------------------------------------------
547  -- ROLE / Nts / Tcp / Tx Data Interfaces (.i.e ROLE-->SHELL)
548  ------------------------------------------------------
549  ---- Axi4-Stream TCP Data ---------------
550  siROL_Nts_Tcp_Data_tdata : in std_ulogic_vector( 63 downto 0);
551  siROL_Nts_Tcp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
552  siROL_Nts_Tcp_Data_tlast : in std_ulogic;
553  siROL_Nts_Tcp_Data_tvalid : in std_ulogic;
554  siROL_Nts_Tcp_Data_tready : out std_ulogic;
555  ---- Axi4-Stream TCP Send Request -------
556  siROL_Nts_Tcp_SndReq_tdata : in std_ulogic_vector( 31 downto 0);
557  siROL_Nts_Tcp_SndReq_tvalid : in std_ulogic;
558  siROL_Nts_Tcp_SndReq_tready : out std_ulogic;
559  ---- Axi4-Stream TCP Send Reply ---------
560  soROL_Nts_Tcp_SndRep_tdata : out std_ulogic_vector( 55 downto 0);
561  soROL_Nts_Tcp_SndRep_tvalid : out std_ulogic;
562  soROL_Nts_Tcp_SndRep_tready : in std_ulogic;
563  ------------------------------------------------------
564  -- ROLE / Nts / Tcp / Rx Data Interfaces (.i.e SHELL-->ROLE)
565  ------------------------------------------------------
566  -- Axi4-Stream TCP Data -----------------
567  soROL_Nts_Tcp_Data_tdata : out std_ulogic_vector( 63 downto 0);
568  soROL_Nts_Tcp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
569  soROL_Nts_Tcp_Data_tlast : out std_ulogic;
570  soROL_Nts_Tcp_Data_tvalid : out std_ulogic;
571  soROL_Nts_Tcp_Data_tready : in std_ulogic;
572  -- Axi4-Stream TCP Metadata ------------
573  soROL_Nts_Tcp_Meta_tdata : out std_ulogic_vector( 15 downto 0);
574  soROL_Nts_Tcp_Meta_tvalid : out std_ulogic;
575  soROL_Nts_Tcp_Meta_tready : in std_ulogic;
576  -- Axi4-Stream TCP Data Notification ---
577  soROL_Nts_Tcp_Notif_tdata : out std_ulogic_vector(7+96 downto 0); -- 8-bits boundary
578  soROL_Nts_Tcp_Notif_tvalid : out std_ulogic;
579  soROL_Nts_Tcp_Notif_tready : in std_ulogic;
580  ---- Stream TCP Data Request -------
581  siROL_Nts_Tcp_DReq_tdata : in std_ulogic_vector( 31 downto 0);
582  siROL_Nts_Tcp_DReq_tvalid : in std_ulogic;
583  siROL_Nts_Tcp_DReq_tready : out std_ulogic;
584  ------------------------------------------------------
585  -- ROLE / Nts / Tcp / TxP Ctlr Interfaces (.i.e ROLE-->SHELL)
586  ------------------------------------------------------
587  ---- Axi4-Stream TCP Open Session Request
588  siROL_Nts_Tcp_OpnReq_tdata : in std_ulogic_vector( 47 downto 0);
589  siROL_Nts_Tcp_OpnReq_tvalid : in std_ulogic;
590  siROL_Nts_Tcp_OpnReq_tready : out std_ulogic;
591  ----- Axi4-Stream TCP Open Session Reply
592  soROL_Nts_Tcp_OpnRep_tdata : out std_ulogic_vector( 23 downto 0);
593  soROL_Nts_Tcp_OpnRep_tvalid : out std_ulogic;
594  soROL_Nts_Tcp_OpnRep_tready : in std_ulogic;
595  ---- Axi4-Stream TCP Close Request ------
596  siROL_Nts_Tcp_ClsReq_tdata : in std_ulogic_vector( 15 downto 0);
597  siROL_Nts_Tcp_ClsReq_tvalid : in std_ulogic;
598  siROL_Nts_Tcp_ClsReq_tready : out std_ulogic;
599  ------------------------------------------------------
600  -- ROLE / Nts / Tcp / Rx Ctlr Interfaces (.i.e SHELL-->ROLE)
601  ------------------------------------------------------
602  ---- Axi4-Stream TCP Listen Request ----
603  siROL_Nts_Tcp_LsnReq_tdata : in std_ulogic_vector( 15 downto 0);
604  siROL_Nts_Tcp_LsnReq_tvalid : in std_ulogic;
605  siROL_Nts_Tcp_LsnReq_tready : out std_ulogic;
606  ---- Axi4-Stream TCP Listen Rep --------
607  soROL_Nts_Tcp_LsnRep_tdata : out std_ulogic_vector( 7 downto 0);
608  soROL_Nts_Tcp_LsnRep_tvalid : out std_ulogic;
609  soROL_Nts_Tcp_LsnRep_tready : in std_ulogic;
610  ------------------------------------------------------
611  -- ROLE / Mem / Mp0 Interface
612  ------------------------------------------------------
613  -- Memory Port #0 / S2MM-AXIS ------------------
614  ---- Stream Read Command -----------------
615  siROL_Mem_Mp0_RdCmd_tdata : in std_ulogic_vector( 79 downto 0);
616  siROL_Mem_Mp0_RdCmd_tvalid : in std_ulogic;
617  siROL_Mem_Mp0_RdCmd_tready : out std_ulogic;
618  ---- Stream Read Status ------------------
619  soROL_Mem_Mp0_RdSts_tdata : out std_ulogic_vector( 7 downto 0);
620  soROL_Mem_Mp0_RdSts_tvalid : out std_ulogic;
621  soROL_Mem_Mp0_RdSts_tready : in std_ulogic;
622  ---- Stream Data Output Channel ----------
623  soROL_Mem_Mp0_Read_tdata : out std_ulogic_vector(511 downto 0);
624  soROL_Mem_Mp0_Read_tkeep : out std_ulogic_vector( 63 downto 0);
625  soROL_Mem_Mp0_Read_tlast : out std_ulogic;
626  soROL_Mem_Mp0_Read_tvalid : out std_ulogic;
627  soROL_Mem_Mp0_Read_tready : in std_ulogic;
628  ---- Stream Write Command ----------------
629  siROL_Mem_Mp0_WrCmd_tdata : in std_ulogic_vector( 79 downto 0);
630  siROL_Mem_Mp0_WrCmd_tvalid : in std_ulogic;
631  siROL_Mem_Mp0_WrCmd_tready : out std_ulogic;
632  ---- Stream Write Status -----------------
633  soROL_Mem_Mp0_WrSts_tvalid : out std_ulogic;
634  soROL_Mem_Mp0_WrSts_tdata : out std_ulogic_vector( 7 downto 0);
635  soROL_Mem_Mp0_WrSts_tready : in std_ulogic;
636  ---- Stream Data Input Channel -----------
637  siROL_Mem_Mp0_Write_tdata : in std_ulogic_vector(511 downto 0);
638  siROL_Mem_Mp0_Write_tkeep : in std_ulogic_vector( 63 downto 0);
639  siROL_Mem_Mp0_Write_tlast : in std_ulogic;
640  siROL_Mem_Mp0_Write_tvalid : in std_ulogic;
641  siROL_Mem_Mp0_Write_tready : out std_ulogic;
642  ------------------------------------------------------
643  -- ROLE / Mem / Mp1 Interface
644  ------------------------------------------------------
645  miROL_Mem_Mp1_AWID : in std_ulogic_vector( 3 downto 0);
646  miROL_Mem_Mp1_AWADDR : in std_ulogic_vector( 32 downto 0);
647  miROL_Mem_Mp1_AWLEN : in std_ulogic_vector( 7 downto 0);
648  miROL_Mem_Mp1_AWSIZE : in std_ulogic_vector( 2 downto 0);
649  miROL_Mem_Mp1_AWBURST : in std_ulogic_vector( 1 downto 0);
650  miROL_Mem_Mp1_AWVALID : in std_ulogic;
651  miROL_Mem_Mp1_AWREADY : out std_ulogic;
652  miROL_Mem_Mp1_WDATA : in std_ulogic_vector(511 downto 0);
653  miROL_Mem_Mp1_WSTRB : in std_ulogic_vector( 63 downto 0);
654  miROL_Mem_Mp1_WLAST : in std_ulogic;
655  miROL_Mem_Mp1_WVALID : in std_ulogic;
656  miROL_Mem_Mp1_WREADY : out std_ulogic;
657  miROL_Mem_Mp1_BID : out std_ulogic_vector( 3 downto 0);
658  miROL_Mem_Mp1_BRESP : out std_ulogic_vector( 1 downto 0);
659  miROL_Mem_Mp1_BVALID : out std_ulogic;
660  miROL_Mem_Mp1_BREADY : in std_ulogic;
661  miROL_Mem_Mp1_ARID : in std_ulogic_vector( 3 downto 0);
662  miROL_Mem_Mp1_ARADDR : in std_ulogic_vector( 32 downto 0);
663  miROL_Mem_Mp1_ARLEN : in std_ulogic_vector( 7 downto 0);
664  miROL_Mem_Mp1_ARSIZE : in std_ulogic_vector( 2 downto 0);
665  miROL_Mem_Mp1_ARBURST : in std_ulogic_vector( 1 downto 0);
666  miROL_Mem_Mp1_ARVALID : in std_ulogic;
667  miROL_Mem_Mp1_ARREADY : out std_ulogic;
668  miROL_Mem_Mp1_RID : out std_ulogic_vector( 3 downto 0);
669  miROL_Mem_Mp1_RDATA : out std_ulogic_vector(511 downto 0);
670  miROL_Mem_Mp1_RRESP : out std_ulogic_vector( 1 downto 0);
671  miROL_Mem_Mp1_RLAST : out std_ulogic;
672  miROL_Mem_Mp1_RVALID : out std_ulogic;
673  miROL_Mem_Mp1_RREADY : in std_ulogic;
674  --------------------------------------------------------
675  -- ROLE / Mmio / AppFlash Interface
676  --------------------------------------------------------
677  ---- PHY_RESET --------------------
678  poROL_Mmio_Ly7Rst : out std_ulogic;
679  ---- PHY_ENABLE -------------------
680  poROL_Mmio_Ly7En : out std_ulogic;
681  ---- DIAG_CTRL_1 ------------------
682  poROL_Mmio_Mc1_MemTestCtrl : out std_ulogic_vector( 1 downto 0);
683  ---- DIAG_STAT_1 -----------------
684  piROL_Mmio_Mc1_MemTestStat : in std_ulogic_vector( 1 downto 0); -- [FIXME: Why 7:0 and not 7:6 ? ]
685  ---- DIAG_CTRL_2 ------------------
686  poROL_Mmio_UdpEchoCtrl : out std_ulogic_vector( 1 downto 0);
687  poROL_Mmio_UdpPostDgmEn : out std_ulogic;
688  poROL_Mmio_UdpCaptDgmEn : out std_ulogic;
689  poROL_Mmio_TcpEchoCtrl : out std_ulogic_vector( 1 downto 0);
690  poROL_Mmio_TcpPostSegEn : out std_ulogic;
691  poROL_Mmio_TcpCaptSegEn : out std_ulogic;
692  ---- APP_RDROL --------------------
693  piROL_Mmio_RdReg : in std_ulogic_vector( 15 downto 0);
694  ---- APP_WRROL --------------------
695  poROL_Mmio_WrReg : out std_ulogic_vector( 15 downto 0)
696  );
697  end component Shell_Kale;
698 
699  -- [INFO] The ROLE component is declared in the corresponding TOP package.
700  -- not this time
701  -- to declare the component in the pkg seems not to work for Verilog or .dcp modules
702  component Role_Kale
703  port (
704  ------------------------------------------------------
705  -- TOP / Global Input Clock and Reset Interface
706  ------------------------------------------------------
707  piSHL_156_25Clk : in std_ulogic;
708  piSHL_156_25Rst : in std_ulogic;
709  ------------------------------------------------------
710  --- SHELL / Nts / Udp / Tx Data Interfaces (.i.e SHELL-->ROLE)
711  ------------------------------------------------------
712  ---- Axi4-Stream UDP Data ----------------
713  siSHL_Nts_Udp_Data_tdata : in std_ulogic_vector( 63 downto 0);
714  siSHL_Nts_Udp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
715  siSHL_Nts_Udp_Data_tvalid : in std_ulogic;
716  siSHL_Nts_Udp_Data_tlast : in std_ulogic;
717  siSHL_Nts_Udp_Data_tready : out std_ulogic;
718  ---- Axi4-Stream UDP Metadata ------------
719  siSHL_Nts_Udp_Meta_tdata : in std_ulogic_vector( 95 downto 0);
720  siSHL_Nts_Udp_Meta_tvalid : in std_ulogic;
721  siSHL_Nts_Udp_Meta_tready : out std_ulogic;
722  ------------------------------------------------------
723  -- SHELL / Nts / Udp / Rx Data Interfaces (.i.e ROLE-->SHELL)
724  -----------------------------------------------------
725  ---- Axi4-Stream UDP Data ---------------
726  soSHL_Nts_Udp_Data_tdata : out std_ulogic_vector( 63 downto 0);
727  soSHL_Nts_Udp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
728  soSHL_Nts_Udp_Data_tvalid : out std_ulogic;
729  soSHL_Nts_Udp_Data_tlast : out std_ulogic;
730  soSHL_Nts_Udp_Data_tready : in std_ulogic;
731  ---- Axi4-Stream UDP Meta ---------------
732  soSHL_Nts_Udp_Meta_tdata : out std_ulogic_vector( 95 downto 0);
733  soSHL_Nts_Udp_Meta_tvalid : out std_ulogic;
734  soSHL_Nts_Udp_Meta_tready : in std_ulogic;
735  ---- Axi4-Stream UDP Data Length ---------
736  soSHL_Nts_Udp_DLen_tdata : out std_ulogic_vector( 15 downto 0);
737  soSHL_Nts_Udp_DLen_tvalid : out std_ulogic;
738  soSHL_Nts_Udp_DLen_tready : in std_ulogic;
739  ------------------------------------------------------
740  -- SHELL / Nts/ Udp / Rx Ctrl Interfaces (.i.e ROLE<-->SHELL)
741  ------------------------------------------------------
742  ---- Axi4-Stream UDP Listen Request -----
743  soSHL_Nts_Udp_LsnReq_tdata : out std_ulogic_vector( 15 downto 0);
744  soSHL_Nts_Udp_LsnReq_tvalid : out std_ulogic;
745  soSHL_Nts_Udp_LsnReq_tready : in std_ulogic;
746  ---- Axi4-Stream UDP Listen Reply --------
747  siSHL_Nts_Udp_LsnRep_tdata : in std_ulogic_vector( 7 downto 0);
748  siSHL_Nts_Udp_LsnRep_tvalid : in std_ulogic;
749  siSHL_Nts_Udp_LsnRep_tready : out std_ulogic;
750  ---- Axi4-Stream UDP Close Request ------
751  soSHL_Nts_Udp_ClsReq_tdata : out std_ulogic_vector( 15 downto 0);
752  soSHL_Nts_Udp_ClsReq_tvalid : out std_ulogic;
753  soSHL_Nts_Udp_ClsReq_tready : in std_ulogic;
754  --- Axi4-Stream UDP Close Reply ---------
755  siSHL_Nts_Udp_ClsRep_tdata : in std_ulogic_vector( 7 downto 0);
756  siSHL_Nts_Udp_ClsRep_tvalid : in std_ulogic;
757  siSHL_Nts_Udp_ClsRep_tready : out std_ulogic;
758  ------------------------------------------------------
759  -- SHELL / Nts / Tcp / Tx Data Interfaces (.i.e ROLE-->SHELL)
760  ------------------------------------------------------
761  ---- Axi4-Stream TCP Data ---------------
762  soSHL_Nts_Tcp_Data_tdata : out std_ulogic_vector( 63 downto 0);
763  soSHL_Nts_Tcp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
764  soSHL_Nts_Tcp_Data_tlast : out std_ulogic;
765  soSHL_Nts_Tcp_Data_tvalid : out std_ulogic;
766  soSHL_Nts_Tcp_Data_tready : in std_ulogic;
767  ---- Axi4-Stream TCP Send Request -------
768  soSHL_Nts_Tcp_SndReq_tdata : out std_ulogic_vector( 31 downto 0);
769  soSHL_Nts_Tcp_SndReq_tvalid : out std_ulogic;
770  soSHL_Nts_Tcp_SndReq_tready : in std_ulogic;
771  ---- Axi4-Stream TCP Send Reply ---------
772  siSHL_Nts_Tcp_SndRep_tdata : in std_ulogic_vector( 55 downto 0);
773  siSHL_Nts_Tcp_SndRep_tvalid : in std_ulogic;
774  siSHL_Nts_Tcp_SndRep_tready : out std_ulogic;
775  --------------------------------------------------------
776  -- SHELL / Nts / Tcp / Rx Data Interfaces (.i.e SHELL-->ROLE)
777  --------------------------------------------------------
778  ---- Axi4-Stream TCP Data -----------------
779  siSHL_Nts_Tcp_Data_tdata : in std_ulogic_vector( 63 downto 0);
780  siSHL_Nts_Tcp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
781  siSHL_Nts_Tcp_Data_tlast : in std_ulogic;
782  siSHL_Nts_Tcp_Data_tvalid : in std_ulogic;
783  siSHL_Nts_Tcp_Data_tready : out std_ulogic;
784  ----- Axi4-Stream TCP Metadata ------------
785  siSHL_Nts_Tcp_Meta_tdata : in std_ulogic_vector( 15 downto 0);
786  siSHL_Nts_Tcp_Meta_tvalid : in std_ulogic;
787  siSHL_Nts_Tcp_Meta_tready : out std_ulogic;
788  ---- Axi4-Stream TCP Data Notification ---
789  siSHL_Nts_Tcp_Notif_tdata : in std_ulogic_vector(7+96 downto 0); -- 8-bits boundary
790  siSHL_Nts_Tcp_Notif_tvalid : in std_ulogic;
791  siSHL_Nts_Tcp_Notif_tready : out std_ulogic;
792  ---- Axi4-Stream TCP Data Request --------
793  soSHL_Nts_Tcp_DReq_tdata : out std_ulogic_vector( 31 downto 0);
794  soSHL_Nts_Tcp_DReq_tvalid : out std_ulogic;
795  soSHL_Nts_Tcp_DReq_tready : in std_ulogic;
796  ------------------------------------------------------
797  -- SHELL / Nts / Tcp / TxP Ctlr Interfaces (.i.e ROLE<-->SHELL)
798  ------------------------------------------------------
799  ---- Axi4-Stream TCP Open Session Request
800  soSHL_Nts_Tcp_OpnReq_tdata : out std_ulogic_vector( 47 downto 0);
801  soSHL_Nts_Tcp_OpnReq_tvalid : out std_ulogic;
802  soSHL_Nts_Tcp_OpnReq_tready : in std_ulogic;
803  ---- Axi4-Stream TCP Open Session Reply
804  siSHL_Nts_Tcp_OpnRep_tdata : in std_ulogic_vector( 23 downto 0);
805  siSHL_Nts_Tcp_OpnRep_tvalid : in std_ulogic;
806  siSHL_Nts_Tcp_OpnRep_tready : out std_ulogic;
807  ---- Axi4-Stream TCP Close Request ------
808  soSHL_Nts_Tcp_ClsReq_tdata : out std_ulogic_vector( 15 downto 0);
809  soSHL_Nts_Tcp_ClsReq_tvalid : out std_ulogic;
810  soSHL_Nts_Tcp_ClsReq_tready : in std_ulogic;
811  ------------------------------------------------------
812  -- SHELL / Nts / Tcp / Rx Ctlr Interfaces (.i.e SHELL-->ROLE)
813  ------------------------------------------------------
814  ---- Axi4-Stream TCP Listen Request ----
815  soSHL_Nts_Tcp_LsnReq_tdata : out std_ulogic_vector( 15 downto 0);
816  soSHL_Nts_Tcp_LsnReq_tvalid : out std_ulogic;
817  soSHL_Nts_Tcp_LsnReq_tready : in std_ulogic;
818  ---- Stream TCP Listen Status ----
819  siSHL_Nts_Tcp_LsnRep_tdata : in std_ulogic_vector( 7 downto 0);
820  siSHL_Nts_Tcp_LsnRep_tvalid : in std_ulogic;
821  siSHL_Nts_Tcp_LsnRep_tready : out std_ulogic;
822  ------------------------------------------------------
823  -- SHELL / Mem / Mp0 Interface
824  ------------------------------------------------------
825  ---- Memory Port #0 / S2MM-AXIS -------------
826  ------ Stream Read Command ---------
827  soSHL_Mem_Mp0_RdCmd_tdata : out std_ulogic_vector( 79 downto 0);
828  soSHL_Mem_Mp0_RdCmd_tvalid : out std_ulogic;
829  soSHL_Mem_Mp0_RdCmd_tready : in std_ulogic;
830  ------ Stream Read Status ----------
831  siSHL_Mem_Mp0_RdSts_tdata : in std_ulogic_vector( 7 downto 0);
832  siSHL_Mem_Mp0_RdSts_tvalid : in std_ulogic;
833  siSHL_Mem_Mp0_RdSts_tready : out std_ulogic;
834  ------ Stream Data Input Channel ---
835  siSHL_Mem_Mp0_Read_tdata : in std_ulogic_vector(511 downto 0);
836  siSHL_Mem_Mp0_Read_tkeep : in std_ulogic_vector( 63 downto 0);
837  siSHL_Mem_Mp0_Read_tlast : in std_ulogic;
838  siSHL_Mem_Mp0_Read_tvalid : in std_ulogic;
839  siSHL_Mem_Mp0_Read_tready : out std_ulogic;
840  ------ Stream Write Command --------
841  soSHL_Mem_Mp0_WrCmd_tdata : out std_ulogic_vector( 79 downto 0);
842  soSHL_Mem_Mp0_WrCmd_tvalid : out std_ulogic;
843  soSHL_Mem_Mp0_WrCmd_tready : in std_ulogic;
844  ------ Stream Write Status ---------
845  siSHL_Mem_Mp0_WrSts_tvalid : in std_ulogic;
846  siSHL_Mem_Mp0_WrSts_tdata : in std_ulogic_vector( 7 downto 0);
847  siSHL_Mem_Mp0_WrSts_tready : out std_ulogic;
848  ------ Stream Data Output Channel --
849  soSHL_Mem_Mp0_Write_tdata : out std_ulogic_vector(511 downto 0);
850  soSHL_Mem_Mp0_Write_tkeep : out std_ulogic_vector( 63 downto 0);
851  soSHL_Mem_Mp0_Write_tlast : out std_ulogic;
852  soSHL_Mem_Mp0_Write_tvalid : out std_ulogic;
853  soSHL_Mem_Mp0_Write_tready : in std_ulogic;
854  ------------------------------------------------------
855  -- SHELL / Mem / Mp1 Interface
856  ------------------------------------------------------
857  moSHL_Mem_Mp1_AWID : out std_ulogic_vector(3 downto 0);
858  moSHL_Mem_Mp1_AWADDR : out std_ulogic_vector(32 downto 0);
859  moSHL_Mem_Mp1_AWLEN : out std_ulogic_vector(7 downto 0);
860  moSHL_Mem_Mp1_AWSIZE : out std_ulogic_vector(2 downto 0);
861  moSHL_Mem_Mp1_AWBURST : out std_ulogic_vector(1 downto 0);
862  moSHL_Mem_Mp1_AWVALID : out std_ulogic;
863  moSHL_Mem_Mp1_AWREADY : in std_ulogic;
864  moSHL_Mem_Mp1_WDATA : out std_ulogic_vector(511 downto 0);
865  moSHL_Mem_Mp1_WSTRB : out std_ulogic_vector(63 downto 0);
866  moSHL_Mem_Mp1_WLAST : out std_ulogic;
867  moSHL_Mem_Mp1_WVALID : out std_ulogic;
868  moSHL_Mem_Mp1_WREADY : in std_ulogic;
869  moSHL_Mem_Mp1_BID : in std_ulogic_vector(3 downto 0);
870  moSHL_Mem_Mp1_BRESP : in std_ulogic_vector(1 downto 0);
871  moSHL_Mem_Mp1_BVALID : in std_ulogic;
872  moSHL_Mem_Mp1_BREADY : out std_ulogic;
873  moSHL_Mem_Mp1_ARID : out std_ulogic_vector(3 downto 0);
874  moSHL_Mem_Mp1_ARADDR : out std_ulogic_vector(32 downto 0);
875  moSHL_Mem_Mp1_ARLEN : out std_ulogic_vector(7 downto 0);
876  moSHL_Mem_Mp1_ARSIZE : out std_ulogic_vector(2 downto 0);
877  moSHL_Mem_Mp1_ARBURST : out std_ulogic_vector(1 downto 0);
878  moSHL_Mem_Mp1_ARVALID : out std_ulogic;
879  moSHL_Mem_Mp1_ARREADY : in std_ulogic;
880  moSHL_Mem_Mp1_RID : in std_ulogic_vector(3 downto 0);
881  moSHL_Mem_Mp1_RDATA : in std_ulogic_vector(511 downto 0);
882  moSHL_Mem_Mp1_RRESP : in std_ulogic_vector(1 downto 0);
883  moSHL_Mem_Mp1_RLAST : in std_ulogic;
884  moSHL_Mem_Mp1_RVALID : in std_ulogic;
885  moSHL_Mem_Mp1_RREADY : out std_ulogic;
886  --------------------------------------------------------
887  -- SHELL / Mmio / AppFlash Interface
888  --------------------------------------------------------
889  ---- [PHY_RESET] -------------------
890  piSHL_Mmio_Ly7Rst : in std_ulogic;
891  ---- [PHY_ENABLE] ------------------
892  piSHL_Mmio_Ly7En : in std_ulogic;
893  ---- [DIAG_CTRL_1] -----------------
894  piSHL_Mmio_Mc1_MemTestCtrl : in std_ulogic_vector( 1 downto 0);
895  ---- [DIAG_STAT_1] -----------------
896  poSHL_Mmio_Mc1_MemTestStat : out std_ulogic_vector( 1 downto 0);
897  ---- [DIAG_CTRL_2] -----------------
898  --[NOT_USED] piSHL_Mmio_UdpEchoCtrl : in std_ulogic_vector( 1 downto 0);
899  --[NOT_USED] piSHL_Mmio_UdpPostDgmEn : in std_ulogic;
900  --[NOT_USED] piSHL_Mmio_UdpCaptDgmEn : in std_ulogic;
901  --[NOT_USED] piSHL_Mmio_TcpEchoCtrl : in std_ulogic_vector( 1 downto 0);
902  --[NOT_USED] piSHL_Mmio_TcpPostSegEn : in std_ulogic;
903  --[NOT_USED] piSHL_Mmio_TcpCaptSegEn : in std_ulogic;
904  ---- [APP_RDROL] -------------------
905  poSHL_Mmio_RdReg : out std_ulogic_vector( 15 downto 0);
906  --- [APP_WRROL] --------------------
907  piSHL_Mmio_WrReg : in std_ulogic_vector( 15 downto 0);
908  --------------------------------------------------------
909  -- TOP : Secondary Clock (Asynchronous)
910  --------------------------------------------------------
911  piTOP_250_00Clk : in std_ulogic -- Freerunning
912  );
913  end component Role_Kale;
914 
915 begin
916 
917  --===========================================================================
918  --== INST: INPUT USER CLOCK BUFFERS
919  --===========================================================================
920  CLKBUF0 : IBUFDS
921  generic map (
922  DQS_BIAS => "FALSE" -- (FALSE, TRUE)
923  )
924  port map (
925  O => sTOP_156_25Clk,
926  I => piCLKT_Usr0Clk_p,
927  IB => piCLKT_Usr0Clk_n
928  );
929 
930  CLKBUF1 : IBUFDS
931  generic map (
932  DQS_BIAS => "FALSE" -- (FALSE, TRUE)
933  )
934  port map (
935  O => sTOP_250_00Clk,
936  I => piCLKT_Usr1Clk_p,
937  IB => piCLKT_Usr1Clk_n
938  );
939 
940  --===========================================================================
941  --== INST: METASTABILITY HARDENED BLOCK FOR THE SYSTEM RESET (Active high)
942  --== [INFO] Note that we instantiate 2 or 3 library primitives rather than
943  --== a VHDL process because it makes it easier to apply the "ASYNC_REG"
944  --== property to those instances.
945  --===========================================================================
946  TOP_META_RST : HARD_SYNC
947  generic map (
948  INIT => '0', -- Initial values, '0', '1'
949  IS_CLK_INVERTED => '0', -- Programmable inversion on CLK input
950  LATENCY => 2 -- 2-3
951  )
952  port map (
953  CLK => sTOP_156_25Clk,
954  DIN => piPSOC_Fcfg_Rst_n,
955  DOUT => sTOP_156_25Rst_n
956  );
957  sTOP_156_25Rst <= not sTOP_156_25Rst_n;
958 
959  --===========================================================================
960  --== INST: BITSTREAM IDENTIFICATION BLOCK with USR_ACCESSE2 PRIMITIVE
961  --== [INFO] This component provides direct FPGA logic access to the 32-bit
962  --== value stored by the FPGA bitstream. We use this register to retrieve
963  --== an accurate timestamp corresponding to the date of the bitstream
964  --== generation (note that we don't track the sminiutes and seconds).
965  --============================================================================
966  TOP_TIMESTAMP : USR_ACCESSE2
967  port map (
968  CFGCLK => open, -- Not used in the static mode
969  DATA => sTOP_Timestamp, -- 32-bit configuration data
970  DATAVALID => open -- Not used in the static mode
971  );
972 
973  --==========================================================================
974  --== INST: SHELL FOR FMKU60
975  --== This version of the SHELL has the following user interfaces:
976  --== - one UDP, one TCP, and two MemoryPort interfaces.
977  --==========================================================================
978  SHELL : Shell_Kale
979  generic map (
980  gSecurityPriviledges => "super",
981  gBitstreamUsage => "flash",
982  gMmioAddrWidth => gEmifAddrWidth,
983  gMmioDataWidth => gEmifDataWidth
984  )
985  port map (
986  ------------------------------------------------------
987  -- TOP / Input Clocks and Resets from topFMKU60
988  ------------------------------------------------------
989  piTOP_156_25Rst => sTOP_156_25Rst,
990  piTOP_156_25Clk => sTOP_156_25Clk,
991  ------------------------------------------------------
992  -- TOP / Bitstream Identification
993  ------------------------------------------------------
994  piTOP_Timestamp => sTOP_Timestamp,
995  ------------------------------------------------------
996  -- CLKT / Clock Tree Interface
997  ------------------------------------------------------
998  piCLKT_Mem0Clk_n => piCLKT_Mem0Clk_n,
999  piCLKT_Mem0Clk_p => piCLKT_Mem0Clk_p,
1000  piCLKT_Mem1Clk_n => piCLKT_Mem1Clk_n,
1001  piCLKT_Mem1Clk_p => piCLKT_Mem1Clk_p,
1002  piCLKT_10GeClk_n => piCLKT_10GeClk_n,
1003  piCLKT_10GeClk_p => piCLKT_10GeClk_p,
1004  ------------------------------------------------------
1005  -- PSOC / External Memory Interface => Emif)
1006  ------------------------------------------------------
1007  piPSOC_Emif_Clk => piPSOC_Emif_Clk,
1008  piPSOC_Emif_Cs_n => piPSOC_Emif_Cs_n,
1009  piPSOC_Emif_We_n => piPSOC_Emif_We_n,
1010  piPSOC_Emif_Oe_n => piPSOC_Emif_Oe_n,
1011  piPSOC_Emif_AdS_n => piPSOC_Emif_AdS_n,
1012  piPSOC_Emif_Addr => piPSOC_Emif_Addr,
1013  pioPSOC_Emif_Data => pioPSOC_Emif_Data,
1014  ------------------------------------------------------
1015  -- LED / Shl / Heart Beat Interface => Yellow LED)
1016  ------------------------------------------------------
1017  poLED_HeartBeat_n => poLED_HeartBeat_n,
1018  ------------------------------------------------------
1019  -- DDR4 / Memory Channel 0 Interface => (Mc0)
1020  ------------------------------------------------------
1021  pioDDR4_Mem_Mc0_DmDbi_n => pioDDR4_Mem_Mc0_DmDbi_n,
1022  pioDDR4_Mem_Mc0_Dq => pioDDR4_Mem_Mc0_Dq,
1023  pioDDR4_Mem_Mc0_Dqs_n => pioDDR4_Mem_Mc0_Dqs_n,
1024  pioDDR4_Mem_Mc0_Dqs_p => pioDDR4_Mem_Mc0_Dqs_p,
1025  poDDR4_Mem_Mc0_Act_n => poDDR4_Mem_Mc0_Act_n,
1026  poDDR4_Mem_Mc0_Adr => poDDR4_Mem_Mc0_Adr,
1027  poDDR4_Mem_Mc0_Ba => poDDR4_Mem_Mc0_Ba,
1028  poDDR4_Mem_Mc0_Bg => poDDR4_Mem_Mc0_Bg,
1029  poDDR4_Mem_Mc0_Cke => poDDR4_Mem_Mc0_Cke,
1030  poDDR4_Mem_Mc0_Odt => poDDR4_Mem_Mc0_Odt,
1031  poDDR4_Mem_Mc0_Cs_n => poDDR4_Mem_Mc0_Cs_n,
1032  poDDR4_Mem_Mc0_Ck_n => poDDR4_Mem_Mc0_Ck_n,
1033  poDDR4_Mem_Mc0_Ck_p => poDDR4_Mem_Mc0_Ck_p,
1034  poDDR4_Mem_Mc0_Reset_n => poDDR4_Mem_Mc0_Reset_n,
1035  ------------------------------------------------------
1036  -- DDR4 / Shl / Memory Channel 1 Interface (Mc1)
1037  ------------------------------------------------------
1038  pioDDR4_Mem_Mc1_DmDbi_n => pioDDR4_Mem_Mc1_DmDbi_n,
1039  pioDDR4_Mem_Mc1_Dq => pioDDR4_Mem_Mc1_Dq,
1040  pioDDR4_Mem_Mc1_Dqs_n => pioDDR4_Mem_Mc1_Dqs_n,
1041  pioDDR4_Mem_Mc1_Dqs_p => pioDDR4_Mem_Mc1_Dqs_p,
1042  poDDR4_Mem_Mc1_Act_n => poDDR4_Mem_Mc1_Act_n,
1043  poDDR4_Mem_Mc1_Adr => poDDR4_Mem_Mc1_Adr,
1044  poDDR4_Mem_Mc1_Ba => poDDR4_Mem_Mc1_Ba,
1045  poDDR4_Mem_Mc1_Bg => poDDR4_Mem_Mc1_Bg,
1046  poDDR4_Mem_Mc1_Cke => poDDR4_Mem_Mc1_Cke,
1047  poDDR4_Mem_Mc1_Odt => poDDR4_Mem_Mc1_Odt,
1048  poDDR4_Mem_Mc1_Cs_n => poDDR4_Mem_Mc1_Cs_n,
1049  poDDR4_Mem_Mc1_Ck_n => poDDR4_Mem_Mc1_Ck_n,
1050  poDDR4_Mem_Mc1_Ck_p => poDDR4_Mem_Mc1_Ck_p,
1051  poDDR4_Mem_Mc1_Reset_n => poDDR4_Mem_Mc1_Reset_n,
1052  ------------------------------------------------------
1053  -- ECON / Edge / Connector Interface (SPD08-200)
1054  ------------------------------------------------------
1055  piECON_Eth_10Ge0_n => piECON_Eth_10Ge0_n,
1056  piECON_Eth_10Ge0_p => piECON_Eth_10Ge0_p,
1057  poECON_Eth_10Ge0_n => poECON_Eth_10Ge0_n,
1058  poECON_Eth_10Ge0_p => poECON_Eth_10Ge0_p,
1059  ------------------------------------------------------
1060  -- ROLE / Reset and Clock Interfaces
1061  ------------------------------------------------------
1062  poROL_156_25Clk => sSHL_156_25Clk,
1063  poROL_156_25Rst => sSHL_156_25Rst,
1064  ------------------------------------------------------
1065  -- ROLE / Nts / Udp / Tx Data Interfaces (.i.e ROLE-->SHELL)
1066  ------------------------------------------------------
1067  ---- Axi4-Stream UDP Data ---------------
1068  siROL_Nts_Udp_Data_tdata => ssROL_SHL_Nts_Udp_Data_tdata,
1069  siROL_Nts_Udp_Data_tkeep => ssROL_SHL_Nts_Udp_Data_tkeep,
1070  siROL_Nts_Udp_Data_tlast => ssROL_SHL_Nts_Udp_Data_tlast,
1071  siROL_Nts_Udp_Data_tvalid => ssROL_SHL_Nts_Udp_Data_tvalid,
1072  siROL_Nts_Udp_Data_tready => ssROL_SHL_Nts_Udp_Data_tready,
1073  ---- Axi4-Stream UDP Metadata -----------
1074  siROL_Nts_Udp_Meta_tdata => ssROL_SHL_Nts_Udp_Meta_tdata ,
1075  siROL_Nts_Udp_Meta_tvalid => ssROL_SHL_Nts_Udp_Meta_tvalid,
1076  siROL_Nts_Udp_Meta_tready => ssROL_SHL_Nts_Udp_Meta_tready,
1077  ---- Axis4Stream UDP Data Length ---------
1078  siROL_Nts_Udp_DLen_tdata => ssROL_SHL_Nts_Udp_DLen_tdata ,
1079  siROL_Nts_Udp_DLen_tvalid => ssROL_SHL_Nts_Udp_DLen_tvalid,
1080  siROL_Nts_Udp_DLen_tready => ssROL_SHL_Nts_Udp_DLen_tready,
1081  ------------------------------------------------------
1082  --ROLE / Nts / Udp / Rx Data Interfaces (.i.e SHELL-->ROLE)
1083  ------------------------------------------------------
1084  ---- Axi4-Stream UDP Data ---------------
1085  soROL_Nts_Udp_Data_tdata => ssSHL_ROL_Nts_Udp_Data_tdata,
1086  soROL_Nts_Udp_Data_tkeep => ssSHL_ROL_Nts_Udp_Data_tkeep,
1087  soROL_Nts_Udp_Data_tlast => ssSHL_ROL_Nts_Udp_Data_tlast,
1088  soROL_Nts_Udp_Data_tvalid => ssSHL_ROL_Nts_Udp_Data_tvalid,
1089  soROL_Nts_Udp_Data_tready => ssSHL_ROL_Nts_Udp_Data_tready,
1090  ---- Axi4-Stream UDP Metadata -----------
1091  soROL_Nts_Udp_Meta_tdata => ssSHL_ROL_Nts_Udp_Meta_tdata ,
1092  soROL_Nts_Udp_Meta_tvalid => ssSHL_ROL_Nts_Udp_Meta_tvalid,
1093  soROL_Nts_Udp_Meta_tready => ssSHL_ROL_Nts_Udp_Meta_tready,
1094  ------------------------------------------------------
1095  -- ROLE / Nts/ Udp / Rx Ctrl Interfaces (.i.e SHELL-->ROLE)
1096  ------------------------------------------------------
1097  ---- Axi4-Stream UDP Listen Request -----
1098  siROL_Nts_Udp_LsnReq_tdata => ssROL_SHL_Nts_Udp_LsnReq_tdata ,
1099  siROL_Nts_Udp_LsnReq_tvalid => ssROL_SHL_Nts_Udp_LsnReq_tvalid,
1100  siROL_Nts_Udp_LsnReq_tready => ssROL_SHL_Nts_Udp_LsnReq_tready,
1101  ---- Axi4-Stream UDP Listen Reply --------
1102  soROL_Nts_Udp_LsnRep_tdata => ssSHL_ROL_Nts_Udp_LsnRep_tdata ,
1103  soROL_Nts_Udp_LsnRep_tvalid => ssSHL_ROL_Nts_Udp_LsnRep_tvalid,
1104  soROL_Nts_Udp_LsnRep_tready => ssSHL_ROL_Nts_Udp_LsnRep_tready,
1105  ---- Axi4-Stream UDP Close Request ------
1106  siROL_Nts_Udp_ClsReq_tdata => ssROL_SHL_Nts_Udp_ClsReq_tdata ,
1107  siROL_Nts_Udp_ClsReq_tvalid => ssROL_SHL_Nts_Udp_ClsReq_tvalid,
1108  siROL_Nts_Udp_ClsReq_tready => ssROL_SHL_Nts_Udp_ClsReq_tready,
1109  ---- Axi4-Stream UDP Close Reply ---------
1110  soROL_Nts_Udp_ClsRep_tdata => ssSHL_ROL_Nts_Udp_ClsRep_tdata ,
1111  soROL_Nts_Udp_ClsRep_tvalid => ssSHL_ROL_Nts_Udp_ClsRep_tvalid,
1112  soROL_Nts_Udp_ClsRep_tready => ssSHL_ROL_Nts_Udp_ClsRep_tready,
1113  ------------------------------------------------------
1114  -- ROLE / Nts / Tcp / Tx Data Interfaces (.i.e ROLE-->SHELL)
1115  ------------------------------------------------------
1116  ---- Axi4-Stream TCP Data ---------------
1117  siROL_Nts_Tcp_Data_tdata => ssROL_SHL_Nts_Tcp_Data_tdata,
1118  siROL_Nts_Tcp_Data_tkeep => ssROL_SHL_Nts_Tcp_Data_tkeep,
1119  siROL_Nts_Tcp_Data_tlast => ssROL_SHL_Nts_Tcp_Data_tlast,
1120  siROL_Nts_Tcp_Data_tvalid => ssROL_SHL_Nts_Tcp_Data_tvalid,
1121  siROL_Nts_Tcp_Data_tready => ssROL_SHL_Nts_Tcp_Data_tready,
1122  ---- Axi4-Stream TCP Send Request -------
1123  siROL_Nts_Tcp_SndReq_tdata => ssROL_SHL_Nts_Tcp_SndReq_tdata,
1124  siROL_Nts_Tcp_SndReq_tvalid => ssROL_SHL_Nts_Tcp_SndReq_tvalid,
1125  siROL_Nts_Tcp_SndReq_tready => ssROL_SHL_Nts_Tcp_SndReq_tready,
1126  ---- Axi4-Stream TCP Send Reply ---------
1127  soROL_Nts_Tcp_SndRep_tdata => ssSHL_ROL_Nts_Tcp_SndRep_tdata,
1128  soROL_Nts_Tcp_SndRep_tvalid => ssSHL_ROL_Nts_Tcp_SndRep_tvalid,
1129  soROL_Nts_Tcp_SndRep_tready => ssSHL_ROL_Nts_Tcp_SndRep_tready,
1130  ------------------------------------------------------
1131  -- ROLE / Nts / Tcp / Rx Data Interfaces (.i.e SHELL-->ROLE)
1132  ------------------------------------------------------
1133  ---- Axi4-Stream TCP Data -----------------
1134  soROL_Nts_Tcp_Data_tdata => ssSHL_ROL_Nts_Tcp_Data_tdata,
1135  soROL_Nts_Tcp_Data_tkeep => ssSHL_ROL_Nts_Tcp_Data_tkeep,
1136  soROL_Nts_Tcp_Data_tlast => ssSHL_ROL_Nts_Tcp_Data_tlast,
1137  soROL_Nts_Tcp_Data_tvalid => ssSHL_ROL_Nts_Tcp_Data_tvalid,
1138  soROL_Nts_Tcp_Data_tready => ssSHL_ROL_Nts_Tcp_Data_tready,
1139  ---- Axi4-Stream TCP Metadata ------------
1140  soROL_Nts_Tcp_Meta_tdata => ssSHL_ROL_Nts_Tcp_Meta_tdata,
1141  soROL_Nts_Tcp_Meta_tvalid => ssSHL_ROL_Nts_Tcp_Meta_tvalid,
1142  soROL_Nts_Tcp_Meta_tready => ssSHL_ROL_Nts_Tcp_Meta_tready,
1143  ---- Axi4-Stream TCP Data Notification ---
1144  soROL_Nts_Tcp_Notif_tdata => ssSHL_ROL_Nts_Tcp_Notif_tdata,
1145  soROL_Nts_Tcp_Notif_tvalid => ssSHL_ROL_Nts_Tcp_Notif_tvalid,
1146  soROL_Nts_Tcp_Notif_tready => ssSHL_ROL_Nts_Tcp_Notif_tready,
1147  ---- Axi4-Stream TCP Data Request --------
1148  siROL_Nts_Tcp_DReq_tdata => ssROL_SHL_Nts_Tcp_DReq_tdata,
1149  siROL_Nts_Tcp_DReq_tvalid => ssROL_SHL_Nts_Tcp_DReq_tvalid,
1150  siROL_Nts_Tcp_DReq_tready => ssROL_SHL_Nts_Tcp_DReq_tready,
1151  ------------------------------------------------------
1152  -- ROLE / Nts / Tcp / TxP Ctlr Interfaces (.i.e ROLE-->SHELL)
1153  ------------------------------------------------------
1154  ---- Axi4-Stream TCP Open Session Request
1155  siROL_Nts_Tcp_OpnReq_tdata => ssROL_SHL_Nts_Tcp_OpnReq_tdata,
1156  siROL_Nts_Tcp_OpnReq_tvalid => ssROL_SHL_Nts_Tcp_OpnReq_tvalid,
1157  siROL_Nts_Tcp_OpnReq_tready => ssROL_SHL_Nts_Tcp_OpnReq_tready,
1158  ---- Axi4-Stream TCP Open Session Reply
1159  soROL_Nts_Tcp_OpnRep_tdata => ssSHL_ROL_Nts_Tcp_OpnRep_tdata,
1160  soROL_Nts_Tcp_OpnRep_tvalid => ssSHL_ROL_Nts_Tcp_OpnRep_tvalid,
1161  soROL_Nts_Tcp_OpnRep_tready => ssSHL_ROL_Nts_Tcp_OpnRep_tready,
1162  ---- Axi4-Stream TCP Close Request ------
1163  siROL_Nts_Tcp_ClsReq_tdata => ssROL_SHL_Nts_Tcp_ClsReq_tdata,
1164  siROL_Nts_Tcp_ClsReq_tvalid => ssROL_SHL_Nts_Tcp_ClsReq_tvalid,
1165  siROL_Nts_Tcp_ClsReq_tready => ssROL_SHL_Nts_Tcp_ClsReq_tready,
1166  ------------------------------------------------------
1167  -- ROLE / Nts / Tcp / Rx Ctlr Interfaces (.i.e SHELL-->ROLE)
1168  ------------------------------------------------------
1169  ---- Axi4-Stream TCP Listen Request ----
1170  siROL_Nts_Tcp_LsnReq_tdata => ssROL_SHL_Nts_Tcp_LsnReq_tdata,
1171  siROL_Nts_Tcp_LsnReq_tvalid => ssROL_SHL_Nts_Tcp_LsnReq_tvalid,
1172  siROL_Nts_Tcp_LsnReq_tready => ssROL_SHL_Nts_Tcp_LsnReq_tready,
1173  ---- Axi4-Stream TCP Listen Rep --------
1174  soROL_Nts_Tcp_LsnRep_tdata => ssSHL_ROL_Nts_Tcp_LsnRep_tdata,
1175  soROL_Nts_Tcp_LsnRep_tvalid => ssSHL_ROL_Nts_Tcp_LsnRep_tvalid,
1176  soROL_Nts_Tcp_LsnRep_tready => ssSHL_ROL_Nts_Tcp_LsnRep_tready,
1177  ------------------------------------------------------
1178  -- ROLE / Mem / Mp0 Interface
1179  ------------------------------------------------------
1180  -- Memory Port #0 / S2MM-AXIS ------------------
1181  ---- Stream Read Command ---------
1182  siROL_Mem_Mp0_RdCmd_tdata => ssROL_SHL_Mem_Mp0_RdCmd_tdata,
1183  siROL_Mem_Mp0_RdCmd_tvalid => ssROL_SHL_Mem_Mp0_RdCmd_tvalid,
1184  siROL_Mem_Mp0_RdCmd_tready => ssROL_SHL_Mem_Mp0_RdCmd_tready,
1185  ---- Stream Read Status ----------
1186  soROL_Mem_Mp0_RdSts_tdata => ssSHL_ROL_Mem_Mp0_RdSts_tdata,
1187  soROL_Mem_Mp0_RdSts_tvalid => ssSHL_ROL_Mem_Mp0_RdSts_tvalid,
1188  soROL_Mem_Mp0_RdSts_tready => ssSHL_ROL_Mem_Mp0_RdSts_tready,
1189  ---- Stream Data Output Channel --
1190  soROL_Mem_Mp0_Read_tdata => ssSHL_ROL_Mem_Mp0_Read_tdata,
1191  soROL_Mem_Mp0_Read_tkeep => ssSHL_ROL_Mem_Mp0_Read_tkeep,
1192  soROL_Mem_Mp0_Read_tlast => ssSHL_ROL_Mem_Mp0_Read_tlast,
1193  soROL_Mem_Mp0_Read_tvalid => ssSHL_ROL_Mem_Mp0_Read_tvalid,
1194  soROL_Mem_Mp0_Read_tready => ssSHL_ROL_Mem_Mp0_Read_tready,
1195  ---- Stream Write Command --------
1196  siROL_Mem_Mp0_WrCmd_tdata => ssROL_SHL_Mem_Mp0_WrCmd_tdata,
1197  siROL_Mem_Mp0_WrCmd_tvalid => ssROL_SHL_Mem_Mp0_WrCmd_tvalid,
1198  siROL_Mem_Mp0_WrCmd_tready => ssROL_SHL_Mem_Mp0_WrCmd_tready,
1199  ---- Stream Write Status ---------
1200  soROL_Mem_Mp0_WrSts_tvalid => ssSHL_ROL_Mem_Mp0_WrSts_tvalid,
1201  soROL_Mem_Mp0_WrSts_tdata => ssSHL_ROL_Mem_Mp0_WrSts_tdata,
1202  soROL_Mem_Mp0_WrSts_tready => ssSHL_ROL_Mem_Mp0_WrSts_tready,
1203  ---- Stream Data Input Channel ---
1204  siROL_Mem_Mp0_Write_tdata => ssROL_SHL_Mem_Mp0_Write_tdata,
1205  siROL_Mem_Mp0_Write_tkeep => ssROL_SHL_Mem_Mp0_Write_tkeep,
1206  siROL_Mem_Mp0_Write_tlast => ssROL_SHL_Mem_Mp0_Write_tlast,
1207  siROL_Mem_Mp0_Write_tvalid => ssROL_SHL_Mem_Mp0_Write_tvalid,
1208  siROL_Mem_Mp0_Write_tready => ssROL_SHL_Mem_Mp0_Write_tready,
1209  ------------------------------------------------------
1210  -- ROLE / Mem / Mp1 Interface
1211  ------------------------------------------------------
1212  miROL_Mem_Mp1_AWID => smROL_SHL_Mem_Mp1_AWID ,
1213  miROL_Mem_Mp1_AWADDR => smROL_SHL_Mem_Mp1_AWADDR ,
1214  miROL_Mem_Mp1_AWLEN => smROL_SHL_Mem_Mp1_AWLEN ,
1215  miROL_Mem_Mp1_AWSIZE => smROL_SHL_Mem_Mp1_AWSIZE ,
1216  miROL_Mem_Mp1_AWBURST => smROL_SHL_Mem_Mp1_AWBURST ,
1217  miROL_Mem_Mp1_AWVALID => smROL_SHL_Mem_Mp1_AWVALID ,
1218  miROL_Mem_Mp1_AWREADY => smROL_SHL_Mem_Mp1_AWREADY ,
1219  miROL_Mem_Mp1_WDATA => smROL_SHL_Mem_Mp1_WDATA ,
1220  miROL_Mem_Mp1_WSTRB => smROL_SHL_Mem_Mp1_WSTRB ,
1221  miROL_Mem_Mp1_WLAST => smROL_SHL_Mem_Mp1_WLAST ,
1222  miROL_Mem_Mp1_WVALID => smROL_SHL_Mem_Mp1_WVALID ,
1223  miROL_Mem_Mp1_WREADY => smROL_SHL_Mem_Mp1_WREADY ,
1224  miROL_Mem_Mp1_BID => smROL_SHL_Mem_Mp1_BID ,
1225  miROL_Mem_Mp1_BRESP => smROL_SHL_Mem_Mp1_BRESP ,
1226  miROL_Mem_Mp1_BVALID => smROL_SHL_Mem_Mp1_BVALID ,
1227  miROL_Mem_Mp1_BREADY => smROL_SHL_Mem_Mp1_BREADY ,
1228  miROL_Mem_Mp1_ARID => smROL_SHL_Mem_Mp1_ARID ,
1229  miROL_Mem_Mp1_ARADDR => smROL_SHL_Mem_Mp1_ARADDR ,
1230  miROL_Mem_Mp1_ARLEN => smROL_SHL_Mem_Mp1_ARLEN ,
1231  miROL_Mem_Mp1_ARSIZE => smROL_SHL_Mem_Mp1_ARSIZE ,
1232  miROL_Mem_Mp1_ARBURST => smROL_SHL_Mem_Mp1_ARBURST ,
1233  miROL_Mem_Mp1_ARVALID => smROL_SHL_Mem_Mp1_ARVALID ,
1234  miROL_Mem_Mp1_ARREADY => smROL_SHL_Mem_Mp1_ARREADY ,
1235  miROL_Mem_Mp1_RID => smROL_SHL_Mem_Mp1_RID ,
1236  miROL_Mem_Mp1_RDATA => smROL_SHL_Mem_Mp1_RDATA ,
1237  miROL_Mem_Mp1_RRESP => smROL_SHL_Mem_Mp1_RRESP ,
1238  miROL_Mem_Mp1_RLAST => smROL_SHL_Mem_Mp1_RLAST ,
1239  miROL_Mem_Mp1_RVALID => smROL_SHL_Mem_Mp1_RVALID ,
1240  miROL_Mem_Mp1_RREADY => smROL_SHL_Mem_Mp1_RREADY ,
1241  ------------------------------------------------------
1242  -- ROLE / Mmio / AppFlash Interface
1243  ------------------------------------------------------
1244  ---- [PHY_RESET] -----------------
1245  poROL_Mmio_Ly7Rst => (sSHL_ROL_Mmio_Ly7Rst),
1246  ---- [PHY_ENABLE] --------------
1247  poROL_Mmio_Ly7En => (sSHL_ROL_Mmio_Ly7En),
1248  ---- [DIAG_CTRL_1] ---------------
1249  poROL_Mmio_Mc1_MemTestCtrl => sSHL_ROL_Mmio_Mc1_MemTestCtrl,
1250  ---- [DIAG_STAT_1] ---------------
1251  piROL_Mmio_Mc1_MemTestStat => sROL_SHL_Mmio_Mc1_MemTestStat,
1252  ---- [DIAG_CTRL_2] ---------------
1253  poROL_Mmio_UdpEchoCtrl => sSHL_ROL_Mmio_UdpEchoCtrl,
1254  poROL_Mmio_UdpPostDgmEn => sSHL_ROL_Mmio_UdpPostDgmEn,
1255  poROL_Mmio_UdpCaptDgmEn => sSHL_ROL_Mmio_UdpCaptDgmEn,
1256  poROL_Mmio_TcpEchoCtrl => sSHL_ROL_Mmio_TcpEchoCtrl,
1257  poROL_Mmio_TcpPostSegEn => sSHL_ROL_Mmio_TcpPostSegEn,
1258  poROL_Mmio_TcpCaptSegEn => sSHL_ROL_Mmio_TcpCaptSegEn,
1259  ---- [APP_RDROL] -----------------
1260  piROL_Mmio_RdReg => sROL_SHL_Mmio_RdReg,
1261  ---- [APP_WRROL] -----------------
1262  poROL_Mmio_WrReg => sSHL_ROL_Mmio_WrReg
1263  ); -- End-of: Shell_Kale instantiation
1264 
1265  --==========================================================================
1266  -- INST: ROLE FOR FMKU60
1267  --==========================================================================
1268  ROLE : Role_Kale
1269  port map (
1270  ------------------------------------------------------
1271  -- SHELL / Global Input Clock and Reset Interface
1272  ------------------------------------------------------
1273  piSHL_156_25Clk => sSHL_156_25Clk,
1274  piSHL_156_25Rst => sSHL_156_25Rst,
1275  ------------------------------------------------------
1276  -- SHELL / Nts / Udp / Tx Data Interfaces (.i.e SHELL-->ROLE)
1277  ------------------------------------------------------
1278  ---- Axi4-Stream UDP Data ----------------
1279  siSHL_Nts_Udp_Data_tdata => ssSHL_ROL_Nts_Udp_Data_tdata ,
1280  siSHL_Nts_Udp_Data_tkeep => ssSHL_ROL_Nts_Udp_Data_tkeep ,
1281  siSHL_Nts_Udp_Data_tlast => ssSHL_ROL_Nts_Udp_Data_tlast ,
1282  siSHL_Nts_Udp_Data_tvalid => ssSHL_ROL_Nts_Udp_Data_tvalid,
1283  siSHL_Nts_Udp_Data_tready => ssSHL_ROL_Nts_Udp_Data_tready,
1284  ---- Axi4-Stream UDP Metadata ------------
1285  siSHL_Nts_Udp_Meta_tdata => ssSHL_ROL_Nts_Udp_Meta_tdata ,
1286  siSHL_Nts_Udp_Meta_tvalid => ssSHL_ROL_Nts_Udp_Meta_tvalid,
1287  siSHL_Nts_Udp_Meta_tready => ssSHL_ROL_Nts_Udp_Meta_tready,
1288  -----------------------------------------------------
1289  -- SHELL / Nts / Udp / Rx Data Interfaces (.i.e ROLE-->SHELL)
1290  ------------------------------------------------------
1291  ---- Axi4-Stream UDP Data ---------------
1292  soSHL_Nts_Udp_Data_tdata => ssROL_SHL_Nts_Udp_Data_tdata ,
1293  soSHL_Nts_Udp_Data_tkeep => ssROL_SHL_Nts_Udp_Data_tkeep ,
1294  soSHL_Nts_Udp_Data_tlast => ssROL_SHL_Nts_Udp_Data_tlast ,
1295  soSHL_Nts_Udp_Data_tvalid => ssROL_SHL_Nts_Udp_Data_tvalid,
1296  soSHL_Nts_Udp_Data_tready => ssROL_SHL_Nts_Udp_Data_tready,
1297  ---- Axi4-Stream UDP Meta ---------------
1298  soSHL_Nts_Udp_Meta_tdata => ssROL_SHL_Nts_Udp_Meta_tdata ,
1299  soSHL_Nts_Udp_Meta_tvalid => ssROL_SHL_Nts_Udp_Meta_tvalid,
1300  soSHL_Nts_Udp_Meta_tready => ssROL_SHL_Nts_Udp_Meta_tready,
1301  ---- Axi4-Stream UDP Data Length ---------
1302  soSHL_Nts_Udp_DLen_tdata => ssROL_SHL_Nts_Udp_DLen_tdata ,
1303  soSHL_Nts_Udp_DLen_tvalid => ssROL_SHL_Nts_Udp_DLen_tvalid,
1304  soSHL_Nts_Udp_DLen_tready => ssROL_SHL_Nts_Udp_DLen_tready,
1305  ------------------------------------------------------
1306  -- SHELL / Nts/ Udp / Rx Ctrl Interfaces (.i.e ROLE-->SHELL)
1307  ------------------------------------------------------
1308  ---- Axi4-Stream UDP Listen Request -----
1309  soSHL_Nts_Udp_LsnReq_tdata => ssROL_SHL_Nts_Udp_LsnReq_tdata ,
1310  soSHL_Nts_Udp_LsnReq_tvalid => ssROL_SHL_Nts_Udp_LsnReq_tvalid,
1311  soSHL_Nts_Udp_LsnReq_tready => ssROL_SHL_Nts_Udp_LsnReq_tready,
1312  ---- Axi4-Stream UDP Listen Reply --------
1313  siSHL_Nts_Udp_LsnRep_tdata => ssSHL_ROL_Nts_Udp_LsnRep_tdata ,
1314  siSHL_Nts_Udp_LsnRep_tvalid => ssSHL_ROL_Nts_Udp_LsnRep_tvalid,
1315  siSHL_Nts_Udp_LsnRep_tready => ssSHL_ROL_Nts_Udp_LsnRep_tready,
1316  ---- Axi4-Stream UDP Close Request ------
1317  soSHL_Nts_Udp_ClsReq_tdata => ssROL_SHL_Nts_Udp_ClsReq_tdata ,
1318  soSHL_Nts_Udp_ClsReq_tvalid => ssROL_SHL_Nts_Udp_ClsReq_tvalid,
1319  soSHL_Nts_Udp_ClsReq_tready => ssROL_SHL_Nts_Udp_ClsReq_tready,
1320  ---- Axi4-Stream UDP Close Reply ---------
1321  siSHL_Nts_Udp_ClsRep_tdata => ssSHL_ROL_Nts_Udp_ClsRep_tdata ,
1322  siSHL_Nts_Udp_ClsRep_tvalid => ssSHL_ROL_Nts_Udp_ClsRep_tvalid,
1323  siSHL_Nts_Udp_ClsRep_tready => ssSHL_ROL_Nts_Udp_ClsRep_tready,
1324  ------------------------------------------------------
1325  -- SHELL / Nts / Tcp / Tx Data Interfaces (.i.e ROLE-->SHELL)
1326  ------------------------------------------------------
1327  ---- Axi4-Stream TCP Data ---------------
1328  soSHL_Nts_Tcp_Data_tdata => ssROL_SHL_Nts_Tcp_Data_tdata ,
1329  soSHL_Nts_Tcp_Data_tkeep => ssROL_SHL_Nts_Tcp_Data_tkeep ,
1330  soSHL_Nts_Tcp_Data_tlast => ssROL_SHL_Nts_Tcp_Data_tlast ,
1331  soSHL_Nts_Tcp_Data_tvalid => ssROL_SHL_Nts_Tcp_Data_tvalid,
1332  soSHL_Nts_Tcp_Data_tready => ssROL_SHL_Nts_Tcp_Data_tready,
1333  ---- Axi4-Stream TCP Send Request --------
1334  soSHL_Nts_Tcp_SndReq_tdata => ssROL_SHL_Nts_Tcp_SndReq_tdata ,
1335  soSHL_Nts_Tcp_SndReq_tvalid => ssROL_SHL_Nts_Tcp_SndReq_tvalid,
1336  soSHL_Nts_Tcp_SndReq_tready => ssROL_SHL_Nts_Tcp_SndReq_tready,
1337  ---- Axi4-Stream TCP Send Reply ---------
1338  siSHL_Nts_Tcp_SndRep_tdata => ssSHL_ROL_Nts_Tcp_SndRep_tdata ,
1339  siSHL_Nts_Tcp_SndRep_tvalid => ssSHL_ROL_Nts_Tcp_SndRep_tvalid,
1340  siSHL_Nts_Tcp_SndRep_tready => ssSHL_ROL_Nts_Tcp_SndRep_tready,
1341  --------------------------------------------------------
1342  -- SHELL / Nts / Tcp / Rx Data Interfaces (.i.e SHELL-->ROLE)
1343  --------------------------------------------------------
1344  ---- Axi4-Stream TCP Data -----------------
1345  siSHL_Nts_Tcp_Data_tdata => ssSHL_ROL_Nts_Tcp_Data_tdata,
1346  siSHL_Nts_Tcp_Data_tkeep => ssSHL_ROL_Nts_Tcp_Data_tkeep,
1347  siSHL_Nts_Tcp_Data_tlast => ssSHL_ROL_Nts_Tcp_Data_tlast,
1348  siSHL_Nts_Tcp_Data_tvalid => ssSHL_ROL_Nts_Tcp_Data_tvalid,
1349  siSHL_Nts_Tcp_Data_tready => ssSHL_ROL_Nts_Tcp_Data_tready,
1350  ---- Axi4-Stream TCP Metadata ------------
1351  siSHL_Nts_Tcp_Meta_tdata => ssSHL_ROL_Nts_Tcp_Meta_tdata,
1352  siSHL_Nts_Tcp_Meta_tvalid => ssSHL_ROL_Nts_Tcp_Meta_tvalid,
1353  siSHL_Nts_Tcp_Meta_tready => ssSHL_ROL_Nts_Tcp_Meta_tready,
1354  ---- Axi4-Stream TCP Data Notification ---
1355  siSHL_Nts_Tcp_Notif_tdata => ssSHL_ROL_Nts_Tcp_Notif_tdata,
1356  siSHL_Nts_Tcp_Notif_tvalid => ssSHL_ROL_Nts_Tcp_Notif_tvalid,
1357  siSHL_Nts_Tcp_Notif_tready => ssSHL_ROL_Nts_Tcp_Notif_tready,
1358  ---- Axi4-Stream TCP Data Request --------
1359  soSHL_Nts_Tcp_DReq_tdata => ssROL_SHL_Nts_Tcp_DReq_tdata,
1360  soSHL_Nts_Tcp_DReq_tvalid => ssROL_SHL_Nts_Tcp_DReq_tvalid,
1361  soSHL_Nts_Tcp_DReq_tready => ssROL_SHL_Nts_Tcp_DReq_tready,
1362  ------------------------------------------------------
1363  -- SHELL / Nts / Tcp / TxP Ctlr Interfaces (.i.e ROLE-->SHELL)
1364  ------------------------------------------------------
1365  ---- Axi4-Stream TCP Open Session Request
1366  ---- Stream TCP Open Session Request
1367  soSHL_Nts_Tcp_OpnReq_tdata => ssROL_SHL_Nts_Tcp_OpnReq_tdata,
1368  soSHL_Nts_Tcp_OpnReq_tvalid => ssROL_SHL_Nts_Tcp_OpnReq_tvalid,
1369  soSHL_Nts_Tcp_OpnReq_tready => ssROL_SHL_Nts_Tcp_OpnReq_tready,
1370  ---- Axi4-Stream TCP Open Session Reply
1371  siSHL_Nts_Tcp_OpnRep_tdata => ssSHL_ROL_Nts_Tcp_OpnRep_tdata,
1372  siSHL_Nts_Tcp_OpnRep_tvalid => ssSHL_ROL_Nts_Tcp_OpnRep_tvalid,
1373  siSHL_Nts_Tcp_OpnRep_tready => ssSHL_ROL_Nts_Tcp_OpnRep_tready,
1374  ---- Axi4-Stream TCP Close Request ------
1375  soSHL_Nts_Tcp_ClsReq_tdata => ssROL_SHL_Nts_Tcp_ClsReq_tdata,
1376  soSHL_Nts_Tcp_ClsReq_tvalid => ssROL_SHL_Nts_Tcp_ClsReq_tvalid,
1377  soSHL_Nts_Tcp_ClsReq_tready => ssROL_SHL_Nts_Tcp_ClsReq_tready,
1378  ------------------------------------------------------
1379  -- SHELL / Nts / Tcp / Rx Ctlr Interfaces (.i.e SHELL-->ROLE)
1380  ------------------------------------------------------
1381  ---- Axi4-Stream TCP Listen Request ----
1382  soSHL_Nts_Tcp_LsnReq_tdata => ssROL_SHL_Nts_Tcp_LsnReq_tdata,
1383  soSHL_Nts_Tcp_LsnReq_tvalid => ssROL_SHL_Nts_Tcp_LsnReq_tvalid,
1384  soSHL_Nts_Tcp_LsnReq_tready => ssROL_SHL_Nts_Tcp_LsnReq_tready,
1385  ----- Axi4-Stream TCP Listen Rep --------
1386  siSHL_Nts_Tcp_LsnRep_tdata => ssSHL_ROL_Nts_Tcp_LsnRep_tdata,
1387  siSHL_Nts_Tcp_LsnRep_tvalid => ssSHL_ROL_Nts_Tcp_LsnRep_tvalid,
1388  siSHL_Nts_Tcp_LsnRep_tready => ssSHL_ROL_Nts_Tcp_LsnRep_tready,
1389  ------------------------------------------------------
1390  -- SHELL / Mem / Mp0 Interface
1391  ------------------------------------------------------
1392  -- Memory Port #0 / S2MM-AXIS ------------------
1393  ---- Stream Read Command ---------
1394  soSHL_Mem_Mp0_RdCmd_tdata => ssROL_SHL_Mem_Mp0_RdCmd_tdata,
1395  soSHL_Mem_Mp0_RdCmd_tvalid => ssROL_SHL_Mem_Mp0_RdCmd_tvalid,
1396  soSHL_Mem_Mp0_RdCmd_tready => ssROL_SHL_Mem_Mp0_RdCmd_tready,
1397  ---- Stream Read Status ----------
1398  siSHL_Mem_Mp0_RdSts_tdata => ssSHL_ROL_Mem_Mp0_RdSts_tdata,
1399  siSHL_Mem_Mp0_RdSts_tvalid => ssSHL_ROL_Mem_Mp0_RdSts_tvalid,
1400  siSHL_Mem_Mp0_RdSts_tready => ssSHL_ROL_Mem_Mp0_RdSts_tready,
1401  ---- Stream Data Input Channel ---
1402  siSHL_Mem_Mp0_Read_tdata => ssSHL_ROL_Mem_Mp0_Read_tdata,
1403  siSHL_Mem_Mp0_Read_tkeep => ssSHL_ROL_Mem_Mp0_Read_tkeep,
1404  siSHL_Mem_Mp0_Read_tlast => ssSHL_ROL_Mem_Mp0_Read_tlast,
1405  siSHL_Mem_Mp0_Read_tvalid => ssSHL_ROL_Mem_Mp0_Read_tvalid,
1406  siSHL_Mem_Mp0_Read_tready => ssSHL_ROL_Mem_Mp0_Read_tready,
1407  ---- Stream Write Command --------
1408  soSHL_Mem_Mp0_WrCmd_tdata => ssROL_SHL_Mem_Mp0_WrCmd_tdata,
1409  soSHL_Mem_Mp0_WrCmd_tvalid => ssROL_SHL_Mem_Mp0_WrCmd_tvalid,
1410  soSHL_Mem_Mp0_WrCmd_tready => ssROL_SHL_Mem_Mp0_WrCmd_tready,
1411  ---- Stream Write Status ---------
1412  siSHL_Mem_Mp0_WrSts_tvalid => ssSHL_ROL_Mem_Mp0_WrSts_tvalid,
1413  siSHL_Mem_Mp0_WrSts_tdata => ssSHL_ROL_Mem_Mp0_WrSts_tdata,
1414  siSHL_Mem_Mp0_WrSts_tready => ssSHL_ROL_Mem_Mp0_WrSts_tready,
1415  ---- Stream Data Output Channel --
1416  soSHL_Mem_Mp0_Write_tdata => ssROL_SHL_Mem_Mp0_Write_tdata,
1417  soSHL_Mem_Mp0_Write_tkeep => ssROL_SHL_Mem_Mp0_Write_tkeep,
1418  soSHL_Mem_Mp0_Write_tlast => ssROL_SHL_Mem_Mp0_Write_tlast,
1419  soSHL_Mem_Mp0_Write_tvalid => ssROL_SHL_Mem_Mp0_Write_tvalid,
1420  soSHL_Mem_Mp0_Write_tready => ssROL_SHL_Mem_Mp0_Write_tready,
1421  ------------------------------------------------------
1422  -- SHELL / Role / Mem / Mp1 Interface
1423  ------------------------------------------------------
1424  moSHL_Mem_Mp1_AWID => smROL_SHL_Mem_Mp1_AWID ,
1425  moSHL_Mem_Mp1_AWADDR => smROL_SHL_Mem_Mp1_AWADDR ,
1426  moSHL_Mem_Mp1_AWLEN => smROL_SHL_Mem_Mp1_AWLEN ,
1427  moSHL_Mem_Mp1_AWSIZE => smROL_SHL_Mem_Mp1_AWSIZE ,
1428  moSHL_Mem_Mp1_AWBURST => smROL_SHL_Mem_Mp1_AWBURST ,
1429  moSHL_Mem_Mp1_AWVALID => smROL_SHL_Mem_Mp1_AWVALID ,
1430  moSHL_Mem_Mp1_AWREADY => smROL_SHL_Mem_Mp1_AWREADY ,
1431  moSHL_Mem_Mp1_WDATA => smROL_SHL_Mem_Mp1_WDATA ,
1432  moSHL_Mem_Mp1_WSTRB => smROL_SHL_Mem_Mp1_WSTRB ,
1433  moSHL_Mem_Mp1_WLAST => smROL_SHL_Mem_Mp1_WLAST ,
1434  moSHL_Mem_Mp1_WVALID => smROL_SHL_Mem_Mp1_WVALID ,
1435  moSHL_Mem_Mp1_WREADY => smROL_SHL_Mem_Mp1_WREADY ,
1436  moSHL_Mem_Mp1_BID => smROL_SHL_Mem_Mp1_BID ,
1437  moSHL_Mem_Mp1_BRESP => smROL_SHL_Mem_Mp1_BRESP ,
1438  moSHL_Mem_Mp1_BVALID => smROL_SHL_Mem_Mp1_BVALID ,
1439  moSHL_Mem_Mp1_BREADY => smROL_SHL_Mem_Mp1_BREADY ,
1440  moSHL_Mem_Mp1_ARID => smROL_SHL_Mem_Mp1_ARID ,
1441  moSHL_Mem_Mp1_ARADDR => smROL_SHL_Mem_Mp1_ARADDR ,
1442  moSHL_Mem_Mp1_ARLEN => smROL_SHL_Mem_Mp1_ARLEN ,
1443  moSHL_Mem_Mp1_ARSIZE => smROL_SHL_Mem_Mp1_ARSIZE ,
1444  moSHL_Mem_Mp1_ARBURST => smROL_SHL_Mem_Mp1_ARBURST ,
1445  moSHL_Mem_Mp1_ARVALID => smROL_SHL_Mem_Mp1_ARVALID ,
1446  moSHL_Mem_Mp1_ARREADY => smROL_SHL_Mem_Mp1_ARREADY ,
1447  moSHL_Mem_Mp1_RID => smROL_SHL_Mem_Mp1_RID ,
1448  moSHL_Mem_Mp1_RDATA => smROL_SHL_Mem_Mp1_RDATA ,
1449  moSHL_Mem_Mp1_RRESP => smROL_SHL_Mem_Mp1_RRESP ,
1450  moSHL_Mem_Mp1_RLAST => smROL_SHL_Mem_Mp1_RLAST ,
1451  moSHL_Mem_Mp1_RVALID => smROL_SHL_Mem_Mp1_RVALID ,
1452  moSHL_Mem_Mp1_RREADY => smROL_SHL_Mem_Mp1_RREADY ,
1453  ------------------------------------------------------
1454  -- SHELL / Mmio / AppFlash Interface
1455  ------------------------------------------------------
1456  ---- [PHY_RESET] -----------------
1457  piSHL_Mmio_Ly7Rst => sSHL_ROL_Mmio_Ly7Rst,
1458  ---- [PHY_ENABLE] ----------------
1459  piSHL_Mmio_Ly7En => sSHL_ROL_Mmio_Ly7En,
1460  ---- [DIAG_CTRL_1] ---------------
1461  piSHL_Mmio_Mc1_MemTestCtrl => sSHL_ROL_Mmio_Mc1_MemTestCtrl,
1462  ---- [DIAG_STAT_1] ---------------
1463  poSHL_Mmio_Mc1_MemTestStat => sROL_SHL_Mmio_Mc1_MemTestStat,
1464  ---- [DIAG_CTRL_2] ---------------
1465  --[NOT_USED] piSHL_Mmio_UdpEchoCtrl => sSHL_ROL_Mmio_UdpEchoCtrl,
1466  --[NOT_USED] piSHL_Mmio_UdpPostDgmEn => sSHL_ROL_Mmio_UdpPostDgmEn,
1467  --[NOT_USED] piSHL_Mmio_UdpCaptDgmEn => sSHL_ROL_Mmio_UdpCaptDgmEn,
1468  --[NOT_USED] piSHL_Mmio_TcpEchoCtrl => sSHL_ROL_Mmio_TcpEchoCtrl,
1469  --[NOT_USED] piSHL_Mmio_TcpPostSegEn => sSHL_ROL_Mmio_TcpPostSegEn,
1470  --[NOT_USED] piSHL_Mmio_TcpCaptSegEn => sSHL_ROL_Mmio_TcpCaptSegEn,
1471  ---- [APP_RDROL] -----------------
1472  poSHL_Mmio_RdReg => sROL_SHL_Mmio_RdReg,
1473  --- [APP_WRROL] ------------------
1474  piSHL_Mmio_WrReg => sSHL_ROL_Mmio_WrReg,
1475  ------------------------------------------------------
1476  ---- TOP : Secondary Clock (Asynchronous)
1477  ------------------------------------------------------
1478  piTOP_250_00Clk => sTOP_250_00Clk -- Freerunning
1479  ); -- End-of: Role instantiation
1480 
1481 end structural;
1482 
Role_Kale
Definition: Role.vhdl:74
Role_Kale.soSHL_Mem_Mp0_RdCmd_tvalid
out soSHL_Mem_Mp0_RdCmd_tvalidstd_ulogic
Definition: Role.vhdl:179
Role_Kale.soSHL_Nts_Udp_DLen_tready
in soSHL_Nts_Udp_DLen_treadystd_ulogic
Definition: Role.vhdl:94
Role_Kale.siSHL_Nts_Tcp_Data_tkeep
in siSHL_Nts_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:124
Role_Kale.siSHL_Nts_Tcp_Notif_tvalid
in siSHL_Nts_Tcp_Notif_tvalidstd_ulogic
Definition: Role.vhdl:136
Role_Kale.siSHL_Nts_Tcp_SndRep_tdata
in siSHL_Nts_Tcp_SndRep_tdatastd_ulogic_vector(55 downto 0)
Definition: Role.vhdl:128
Role_Kale.siSHL_Nts_Tcp_LsnRep_tdata
in siSHL_Nts_Tcp_LsnRep_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:175
Role_Kale.siSHL_Mem_Mp0_Read_tlast
in siSHL_Mem_Mp0_Read_tlaststd_ulogic
Definition: Role.vhdl:188
Role_Kale.soSHL_Nts_Tcp_Data_tvalid
out soSHL_Nts_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:107
Role_Kale.moSHL_Mem_Mp1_RREADY
out moSHL_Mem_Mp1_RREADYstd_ulogic
Definition: Role.vhdl:246
Role_Kale.moSHL_Mem_Mp1_WREADY
in moSHL_Mem_Mp1_WREADYstd_ulogic
Definition: Role.vhdl:226
Role_Kale.siSHL_Nts_Tcp_OpnRep_tdata
in siSHL_Nts_Tcp_OpnRep_tdatastd_ulogic_vector(23 downto 0)
Definition: Role.vhdl:152
Role_Kale.siSHL_Mem_Mp0_WrSts_tvalid
in siSHL_Mem_Mp0_WrSts_tvalidstd_ulogic
Definition: Role.vhdl:197
Role_Kale.poSHL_Mmio_RdReg
out poSHL_Mmio_RdRegstd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:258
Role_Kale.piSHL_156_25Rst
in piSHL_156_25Rststd_ulogic
Definition: Role.vhdl:81
Role_Kale.siSHL_Nts_Udp_Data_tlast
in siSHL_Nts_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:89
Role_Kale.siSHL_Mem_Mp0_Read_tkeep
in siSHL_Mem_Mp0_Read_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:187
Role_Kale.soSHL_Nts_Tcp_SndReq_tvalid
out soSHL_Nts_Tcp_SndReq_tvalidstd_ulogic
Definition: Role.vhdl:125
Role_Kale.moSHL_Mem_Mp1_AWBURST
out moSHL_Mem_Mp1_AWBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:218
Role_Kale.soSHL_Nts_Tcp_DReq_tvalid
out soSHL_Nts_Tcp_DReq_tvalidstd_ulogic
Definition: Role.vhdl:140
Role_Kale.moSHL_Mem_Mp1_RID
in moSHL_Mem_Mp1_RIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:241
Role_Kale.soSHL_Nts_Tcp_OpnReq_tready
in soSHL_Nts_Tcp_OpnReq_treadystd_ulogic
Definition: Role.vhdl:150
Role_Kale.siSHL_Mem_Mp0_RdSts_tvalid
in siSHL_Mem_Mp0_RdSts_tvalidstd_ulogic
Definition: Role.vhdl:183
Role_Kale.soSHL_Mem_Mp0_WrCmd_tvalid
out soSHL_Mem_Mp0_WrCmd_tvalidstd_ulogic
Definition: Role.vhdl:193
Role_Kale.piSHL_Mmio_Ly7En
in piSHL_Mmio_Ly7Enstd_ulogic
Definition: Role.vhdl:245
Role_Kale.soSHL_Nts_Udp_LsnReq_tdata
out soSHL_Nts_Udp_LsnReq_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:99
Role_Kale.soSHL_Nts_Tcp_Data_tlast
out soSHL_Nts_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:106
Role_Kale.moSHL_Mem_Mp1_WVALID
out moSHL_Mem_Mp1_WVALIDstd_ulogic
Definition: Role.vhdl:225
Role_Kale.siSHL_Mem_Mp0_Read_tready
out siSHL_Mem_Mp0_Read_treadystd_ulogic
Definition: Role.vhdl:190
Role_Kale.soSHL_Nts_Udp_DLen_tvalid
out soSHL_Nts_Udp_DLen_tvalidstd_ulogic
Definition: Role.vhdl:93
Role_Kale.soSHL_Nts_Tcp_ClsReq_tdata
out soSHL_Nts_Tcp_ClsReq_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:156
Role_Kale.soSHL_Nts_Udp_Meta_tdata
out soSHL_Nts_Udp_Meta_tdatastd_ulogic_vector(95 downto 0)
Definition: Role.vhdl:88
Role_Kale.moSHL_Mem_Mp1_BREADY
out moSHL_Mem_Mp1_BREADYstd_ulogic
Definition: Role.vhdl:231
Role_Kale.siSHL_Nts_Udp_Data_tready
out siSHL_Nts_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:91
Role_Kale.siSHL_Nts_Udp_ClsRep_tvalid
in siSHL_Nts_Udp_ClsRep_tvalidstd_ulogic
Definition: Role.vhdl:112
Role_Kale.siSHL_Nts_Udp_ClsRep_tdata
in siSHL_Nts_Udp_ClsRep_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:111
Role_Kale.siSHL_Mem_Mp0_WrSts_tdata
in siSHL_Mem_Mp0_WrSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:196
Role_Kale.soSHL_Nts_Tcp_DReq_tready
in soSHL_Nts_Tcp_DReq_treadystd_ulogic
Definition: Role.vhdl:141
Role_Kale.piSHL_156_25Clk
in piSHL_156_25Clkstd_ulogic
Definition: Role.vhdl:80
Role_Kale.soSHL_Nts_Tcp_LsnReq_tvalid
out soSHL_Nts_Tcp_LsnReq_tvalidstd_ulogic
Definition: Role.vhdl:166
Role_Kale.siSHL_Nts_Tcp_Meta_tready
out siSHL_Nts_Tcp_Meta_treadystd_ulogic
Definition: Role.vhdl:133
Role_Kale.siSHL_Nts_Udp_Meta_tdata
in siSHL_Nts_Udp_Meta_tdatastd_ulogic_vector(95 downto 0)
Definition: Role.vhdl:71
Role_Kale.moSHL_Mem_Mp1_AWREADY
in moSHL_Mem_Mp1_AWREADYstd_ulogic
Definition: Role.vhdl:220
Role_Kale.moSHL_Mem_Mp1_RRESP
in moSHL_Mem_Mp1_RRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:243
Role_Kale.soSHL_Nts_Udp_Data_tvalid
out soSHL_Nts_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:96
Role_Kale.siSHL_Nts_Tcp_Data_tready
out siSHL_Nts_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:127
Role_Kale.siSHL_Nts_Udp_Data_tdata
in siSHL_Nts_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:87
Role_Kale.poSHL_Mmio_Mc1_MemTestStat
out poSHL_Mmio_Mc1_MemTestStatstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:249
Role_Kale.soSHL_Nts_Tcp_Data_tready
in soSHL_Nts_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:108
Role_Kale.soSHL_Mem_Mp0_Write_tready
in soSHL_Mem_Mp0_Write_treadystd_ulogic
Definition: Role.vhdl:204
Role_Kale.moSHL_Mem_Mp1_BID
in moSHL_Mem_Mp1_BIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:228
Role_Kale.soSHL_Nts_Udp_ClsReq_tready
in soSHL_Nts_Udp_ClsReq_treadystd_ulogic
Definition: Role.vhdl:109
Role_Kale.siSHL_Nts_Tcp_Notif_tready
out siSHL_Nts_Tcp_Notif_treadystd_ulogic
Definition: Role.vhdl:137
Role_Kale.siSHL_Nts_Tcp_OpnRep_tvalid
in siSHL_Nts_Tcp_OpnRep_tvalidstd_ulogic
Definition: Role.vhdl:153
Role_Kale.soSHL_Mem_Mp0_WrCmd_tdata
out soSHL_Mem_Mp0_WrCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:192
Role_Kale.siSHL_Nts_Tcp_OpnRep_tready
out siSHL_Nts_Tcp_OpnRep_treadystd_ulogic
Definition: Role.vhdl:154
Role_Kale.siSHL_Nts_Tcp_Data_tlast
in siSHL_Nts_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:125
Role_Kale.siSHL_Nts_Udp_Meta_tvalid
in siSHL_Nts_Udp_Meta_tvalidstd_ulogic
Definition: Role.vhdl:72
Role_Kale.soSHL_Nts_Udp_Data_tready
in soSHL_Nts_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:97
Role_Kale.moSHL_Mem_Mp1_BRESP
in moSHL_Mem_Mp1_BRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:229
Role_Kale.soSHL_Mem_Mp0_Write_tdata
out soSHL_Mem_Mp0_Write_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:200
Role_Kale.siSHL_Mem_Mp0_RdSts_tdata
in siSHL_Mem_Mp0_RdSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:182
Role_Kale.soSHL_Nts_Tcp_LsnReq_tdata
out soSHL_Nts_Tcp_LsnReq_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:165
Role_Kale.moSHL_Mem_Mp1_AWSIZE
out moSHL_Mem_Mp1_AWSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:217
Role_Kale.soSHL_Mem_Mp0_RdCmd_tready
in soSHL_Mem_Mp0_RdCmd_treadystd_ulogic
Definition: Role.vhdl:180
Role_Kale.piSHL_Mmio_Mc1_MemTestCtrl
in piSHL_Mmio_Mc1_MemTestCtrlstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:247
Role_Kale.soSHL_Nts_Udp_Data_tlast
out soSHL_Nts_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:95
Role_Kale.siSHL_Nts_Udp_LsnRep_tready
out siSHL_Nts_Udp_LsnRep_treadystd_ulogic
Definition: Role.vhdl:105
Role_Kale.soSHL_Nts_Udp_LsnReq_tready
in soSHL_Nts_Udp_LsnReq_treadystd_ulogic
Definition: Role.vhdl:101
Role_Kale.soSHL_Nts_Udp_DLen_tdata
out soSHL_Nts_Udp_DLen_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:92
Role_Kale.soSHL_Nts_Tcp_OpnReq_tvalid
out soSHL_Nts_Tcp_OpnReq_tvalidstd_ulogic
Definition: Role.vhdl:149
Role_Kale.soSHL_Nts_Tcp_OpnReq_tdata
out soSHL_Nts_Tcp_OpnReq_tdatastd_ulogic_vector(47 downto 0)
Definition: Role.vhdl:148
Role_Kale.moSHL_Mem_Mp1_RDATA
in moSHL_Mem_Mp1_RDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:242
Role_Kale.moSHL_Mem_Mp1_RVALID
in moSHL_Mem_Mp1_RVALIDstd_ulogic
Definition: Role.vhdl:245
Role_Kale.moSHL_Mem_Mp1_WSTRB
out moSHL_Mem_Mp1_WSTRBstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:223
Role_Kale.soSHL_Nts_Tcp_ClsReq_tvalid
out soSHL_Nts_Tcp_ClsReq_tvalidstd_ulogic
Definition: Role.vhdl:157
Role_Kale.moSHL_Mem_Mp1_AWVALID
out moSHL_Mem_Mp1_AWVALIDstd_ulogic
Definition: Role.vhdl:219
Role_Kale.moSHL_Mem_Mp1_AWID
out moSHL_Mem_Mp1_AWIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:214
Role_Kale.soSHL_Mem_Mp0_Write_tvalid
out soSHL_Mem_Mp0_Write_tvalidstd_ulogic
Definition: Role.vhdl:203
Role_Kale.siSHL_Nts_Udp_ClsRep_tready
out siSHL_Nts_Udp_ClsRep_treadystd_ulogic
Definition: Role.vhdl:113
Role_Kale.siSHL_Nts_Tcp_SndRep_tready
out siSHL_Nts_Tcp_SndRep_treadystd_ulogic
Definition: Role.vhdl:130
Role_Kale.siSHL_Nts_Udp_Data_tkeep
in siSHL_Nts_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:88
Role_Kale.soSHL_Nts_Tcp_LsnReq_tready
in soSHL_Nts_Tcp_LsnReq_treadystd_ulogic
Definition: Role.vhdl:167
Role_Kale.soSHL_Nts_Tcp_SndReq_tready
in soSHL_Nts_Tcp_SndReq_treadystd_ulogic
Definition: Role.vhdl:126
Role_Kale.siSHL_Nts_Udp_LsnRep_tdata
in siSHL_Nts_Udp_LsnRep_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:103
Role_Kale.moSHL_Mem_Mp1_ARADDR
out moSHL_Mem_Mp1_ARADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:234
Role_Kale.soSHL_Mem_Mp0_WrCmd_tready
in soSHL_Mem_Mp0_WrCmd_treadystd_ulogic
Definition: Role.vhdl:194
Role_Kale.soSHL_Mem_Mp0_Write_tlast
out soSHL_Mem_Mp0_Write_tlaststd_ulogic
Definition: Role.vhdl:202
Role_Kale.siSHL_Nts_Tcp_Notif_tdata
in siSHL_Nts_Tcp_Notif_tdatastd_ulogic_vector(7+96 downto 0)
Definition: Role.vhdl:135
Role_Kale.soSHL_Nts_Tcp_Data_tdata
out soSHL_Nts_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:104
Role_Kale.soSHL_Nts_Udp_Meta_tvalid
out soSHL_Nts_Udp_Meta_tvalidstd_ulogic
Definition: Role.vhdl:89
Role_Kale.moSHL_Mem_Mp1_ARLEN
out moSHL_Mem_Mp1_ARLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:235
Role_Kale.siSHL_Nts_Udp_Meta_tready
out siSHL_Nts_Udp_Meta_treadystd_ulogic
Definition: Role.vhdl:73
Role_Kale.soSHL_Nts_Tcp_Data_tkeep
out soSHL_Nts_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:105
Role_Kale.soSHL_Nts_Udp_Data_tdata
out soSHL_Nts_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:93
Role_Kale.moSHL_Mem_Mp1_ARREADY
in moSHL_Mem_Mp1_ARREADYstd_ulogic
Definition: Role.vhdl:239
Role_Kale.siSHL_Nts_Tcp_Meta_tdata
in siSHL_Nts_Tcp_Meta_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:129
Role_Kale.soSHL_Nts_Udp_LsnReq_tvalid
out soSHL_Nts_Udp_LsnReq_tvalidstd_ulogic
Definition: Role.vhdl:100
Role_Kale.soSHL_Mem_Mp0_RdCmd_tdata
out soSHL_Mem_Mp0_RdCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:178
Role_Kale.siSHL_Nts_Tcp_Data_tdata
in siSHL_Nts_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:123
Role_Kale.moSHL_Mem_Mp1_AWLEN
out moSHL_Mem_Mp1_AWLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:216
Role_Kale.moSHL_Mem_Mp1_ARSIZE
out moSHL_Mem_Mp1_ARSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:236
Role_Kale.soSHL_Nts_Tcp_SndReq_tdata
out soSHL_Nts_Tcp_SndReq_tdatastd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:124
Role_Kale.soSHL_Nts_Udp_Meta_tready
in soSHL_Nts_Udp_Meta_treadystd_ulogic
Definition: Role.vhdl:90
Role_Kale.moSHL_Mem_Mp1_WLAST
out moSHL_Mem_Mp1_WLASTstd_ulogic
Definition: Role.vhdl:224
Role_Kale.siSHL_Nts_Udp_LsnRep_tvalid
in siSHL_Nts_Udp_LsnRep_tvalidstd_ulogic
Definition: Role.vhdl:104
Role_Kale.soSHL_Nts_Tcp_DReq_tdata
out soSHL_Nts_Tcp_DReq_tdatastd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:139
Role_Kale.moSHL_Mem_Mp1_WDATA
out moSHL_Mem_Mp1_WDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:222
Role_Kale.soSHL_Nts_Udp_Data_tkeep
out soSHL_Nts_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:94
Role_Kale.siSHL_Nts_Tcp_SndRep_tvalid
in siSHL_Nts_Tcp_SndRep_tvalidstd_ulogic
Definition: Role.vhdl:129
Role_Kale.soSHL_Nts_Udp_ClsReq_tvalid
out soSHL_Nts_Udp_ClsReq_tvalidstd_ulogic
Definition: Role.vhdl:108
Role_Kale.soSHL_Nts_Udp_ClsReq_tdata
out soSHL_Nts_Udp_ClsReq_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:107
Role_Kale.siSHL_Mem_Mp0_Read_tvalid
in siSHL_Mem_Mp0_Read_tvalidstd_ulogic
Definition: Role.vhdl:189
Role_Kale.soSHL_Mem_Mp0_Write_tkeep
out soSHL_Mem_Mp0_Write_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:201
Role_Kale.siSHL_Nts_Udp_Data_tvalid
in siSHL_Nts_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:90
Role_Kale.siSHL_Nts_Tcp_LsnRep_tready
out siSHL_Nts_Tcp_LsnRep_treadystd_ulogic
Definition: Role.vhdl:177
Role_Kale.piTOP_250_00Clk
in piTOP_250_00Clkstd_ulogic
Definition: Role.vhdl:265
Role_Kale.moSHL_Mem_Mp1_RLAST
in moSHL_Mem_Mp1_RLASTstd_ulogic
Definition: Role.vhdl:244
Role_Kale.moSHL_Mem_Mp1_ARBURST
out moSHL_Mem_Mp1_ARBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:237
Role_Kale.siSHL_Nts_Tcp_Meta_tvalid
in siSHL_Nts_Tcp_Meta_tvalidstd_ulogic
Definition: Role.vhdl:132
Role_Kale.piSHL_Mmio_WrReg
in piSHL_Mmio_WrRegstd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:260
Role_Kale.moSHL_Mem_Mp1_BVALID
in moSHL_Mem_Mp1_BVALIDstd_ulogic
Definition: Role.vhdl:230
Role_Kale.siSHL_Nts_Tcp_LsnRep_tvalid
in siSHL_Nts_Tcp_LsnRep_tvalidstd_ulogic
Definition: Role.vhdl:176
Role_Kale.soSHL_Nts_Tcp_ClsReq_tready
in soSHL_Nts_Tcp_ClsReq_treadystd_ulogic
Definition: Role.vhdl:158
Role_Kale.moSHL_Mem_Mp1_ARID
out moSHL_Mem_Mp1_ARIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:233
Role_Kale.siSHL_Mem_Mp0_WrSts_tready
out siSHL_Mem_Mp0_WrSts_treadystd_ulogic
Definition: Role.vhdl:198
Role_Kale.siSHL_Mem_Mp0_RdSts_tready
out siSHL_Mem_Mp0_RdSts_treadystd_ulogic
Definition: Role.vhdl:184
Role_Kale.moSHL_Mem_Mp1_ARVALID
out moSHL_Mem_Mp1_ARVALIDstd_ulogic
Definition: Role.vhdl:238
Role_Kale.siSHL_Mem_Mp0_Read_tdata
in siSHL_Mem_Mp0_Read_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:186
Role_Kale.moSHL_Mem_Mp1_AWADDR
out moSHL_Mem_Mp1_AWADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:215
Role_Kale.piSHL_Mmio_Ly7Rst
in piSHL_Mmio_Ly7Rststd_ulogic
Definition: Role.vhdl:243
Role_Kale.siSHL_Nts_Tcp_Data_tvalid
in siSHL_Nts_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:126
topFMKU60.poDDR4_Mem_Mc0_Reset_n
out poDDR4_Mem_Mc0_Reset_nstd_ulogic
Definition: top.vhdl:149
topFMKU60.pioPSOC_Emif_Data
inout pioPSOC_Emif_Datastd_ulogic_vector( gEmifDataWidth- 1 downto 0)
Definition: top.vhdl:126
topFMKU60.poDDR4_Mem_Mc0_Odt
out poDDR4_Mem_Mc0_Odtstd_ulogic
Definition: top.vhdl:145
topFMKU60.poDDR4_Mem_Mc0_Act_n
out poDDR4_Mem_Mc0_Act_nstd_ulogic
Definition: top.vhdl:140
topFMKU60.piPSOC_Emif_Addr
in piPSOC_Emif_Addrstd_ulogic_vector( gEmifAddrWidth- 1 downto 0)
Definition: top.vhdl:125
topFMKU60.piPSOC_Emif_Clk
in piPSOC_Emif_Clkstd_ulogic
Definition: top.vhdl:120
topFMKU60.pioDDR4_Mem_Mc0_Dqs_n
inout pioDDR4_Mem_Mc0_Dqs_nstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:139
topFMKU60.piPSOC_Emif_Cs_n
in piPSOC_Emif_Cs_nstd_ulogic
Definition: top.vhdl:121
topFMKU60.gBitstreamUsage
gBitstreamUsagestring := "flash"
Definition: top.vhdl:78
topFMKU60.poDDR4_Mem_Mc1_Ck_n
out poDDR4_Mem_Mc1_Ck_nstd_ulogic
Definition: top.vhdl:166
topFMKU60.pioDDR4_Mem_Mc0_DmDbi_n
inout pioDDR4_Mem_Mc0_DmDbi_nstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:136
topFMKU60.gEmifDataWidth
gEmifDataWidthinteger :=8
Definition: top.vhdl:87
topFMKU60.piCLKT_Usr1Clk_n
in piCLKT_Usr1Clk_nstd_ulogic
Definition: top.vhdl:114
topFMKU60.poDDR4_Mem_Mc0_Ck_n
out poDDR4_Mem_Mc0_Ck_nstd_ulogic
Definition: top.vhdl:148
topFMKU60.piCLKT_10GeClk_p
in piCLKT_10GeClk_pstd_ulogic
Definition: top.vhdl:107
topFMKU60.poDDR4_Mem_Mc0_Ck_p
out poDDR4_Mem_Mc0_Ck_pstd_ulogic
Definition: top.vhdl:147
topFMKU60.piPSOC_Emif_AdS_n
in piPSOC_Emif_AdS_nstd_ulogic
Definition: top.vhdl:124
topFMKU60.piPSOC_Emif_We_n
in piPSOC_Emif_We_nstd_ulogic
Definition: top.vhdl:122
topFMKU60.poDDR4_Mem_Mc0_Adr
out poDDR4_Mem_Mc0_Adrstd_ulogic_vector(16 downto 0)
Definition: top.vhdl:141
topFMKU60.poLED_HeartBeat_n
out poLED_HeartBeat_nstd_ulogic
Definition: top.vhdl:131
topFMKU60.piPSOC_Emif_Oe_n
in piPSOC_Emif_Oe_nstd_ulogic
Definition: top.vhdl:123
topFMKU60.gTopDateMonth
gTopDateMonthstDate :=8d"00"
Definition: top.vhdl:82
topFMKU60.pioDDR4_Mem_Mc1_Dqs_n
inout pioDDR4_Mem_Mc1_Dqs_nstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:157
topFMKU60.piCLKT_Mem0Clk_n
in piCLKT_Mem0Clk_nstd_ulogic
Definition: top.vhdl:98
topFMKU60.pioDDR4_Mem_Mc1_Dq
inout pioDDR4_Mem_Mc1_Dqstd_ulogic_vector(71 downto 0)
Definition: top.vhdl:155
topFMKU60.pioDDR4_Mem_Mc1_DmDbi_n
inout pioDDR4_Mem_Mc1_DmDbi_nstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:154
topFMKU60.piCLKT_Usr0Clk_n
in piCLKT_Usr0Clk_nstd_ulogic
Definition: top.vhdl:112
topFMKU60.pioDDR4_Mem_Mc0_Dq
inout pioDDR4_Mem_Mc0_Dqstd_ulogic_vector(71 downto 0)
Definition: top.vhdl:137
topFMKU60.poDDR4_Mem_Mc1_Cke
out poDDR4_Mem_Mc1_Ckestd_ulogic
Definition: top.vhdl:162
topFMKU60.piCLKT_Mem1Clk_p
in piCLKT_Mem1Clk_pstd_ulogic
Definition: top.vhdl:101
topFMKU60.pioDDR4_Mem_Mc0_Dqs_p
inout pioDDR4_Mem_Mc0_Dqs_pstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:138
topFMKU60.poDDR4_Mem_Mc1_Adr
out poDDR4_Mem_Mc1_Adrstd_ulogic_vector(16 downto 0)
Definition: top.vhdl:159
topFMKU60.gTopDateDay
gTopDateDaystDate :=8d"00"
Definition: top.vhdl:83
topFMKU60.gSecurityPriviledges
gSecurityPriviledgesstring := "super"
Definition: top.vhdl:79
topFMKU60.poDDR4_Mem_Mc1_Ck_p
out poDDR4_Mem_Mc1_Ck_pstd_ulogic
Definition: top.vhdl:165
topFMKU60.gEmifAddrWidth
gEmifAddrWidthinteger :=8
Definition: top.vhdl:85
topFMKU60.piCLKT_Usr1Clk_p
in piCLKT_Usr1Clk_pstd_ulogic
Definition: top.vhdl:115
topFMKU60.poDDR4_Mem_Mc1_Cs_n
out poDDR4_Mem_Mc1_Cs_nstd_ulogic
Definition: top.vhdl:164
topFMKU60.poDDR4_Mem_Mc0_Bg
out poDDR4_Mem_Mc0_Bgstd_ulogic_vector(1 downto 0)
Definition: top.vhdl:143
topFMKU60.piECON_Eth_10Ge0_p
in piECON_Eth_10Ge0_pstd_ulogic
Definition: top.vhdl:173
topFMKU60.poDDR4_Mem_Mc0_Cs_n
out poDDR4_Mem_Mc0_Cs_nstd_ulogic
Definition: top.vhdl:146
topFMKU60.piCLKT_Usr0Clk_p
in piCLKT_Usr0Clk_pstd_ulogic
Definition: top.vhdl:113
topFMKU60.poECON_Eth_10Ge0_n
out poECON_Eth_10Ge0_nstd_ulogic
Definition: top.vhdl:174
topFMKU60.piECON_Eth_10Ge0_n
in piECON_Eth_10Ge0_nstd_ulogic
Definition: top.vhdl:172
topFMKU60.piPSOC_Fcfg_Rst_n
in piPSOC_Fcfg_Rst_nstd_ulogic
Definition: top.vhdl:93
topFMKU60.gTopDateYear
gTopDateYearstDate :=8d"00"
Definition: top.vhdl:81
topFMKU60.piCLKT_Mem0Clk_p
in piCLKT_Mem0Clk_pstd_ulogic
Definition: top.vhdl:99
topFMKU60.poECON_Eth_10Ge0_p
out poECON_Eth_10Ge0_pstd_ulogic
Definition: top.vhdl:177
topFMKU60.poDDR4_Mem_Mc1_Act_n
out poDDR4_Mem_Mc1_Act_nstd_ulogic
Definition: top.vhdl:158
topFMKU60.pioDDR4_Mem_Mc1_Dqs_p
inout pioDDR4_Mem_Mc1_Dqs_pstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:156
topFMKU60.poDDR4_Mem_Mc0_Ba
out poDDR4_Mem_Mc0_Bastd_ulogic_vector(1 downto 0)
Definition: top.vhdl:142
topFMKU60.poDDR4_Mem_Mc1_Ba
out poDDR4_Mem_Mc1_Bastd_ulogic_vector(1 downto 0)
Definition: top.vhdl:160
topFMKU60.poDDR4_Mem_Mc1_Bg
out poDDR4_Mem_Mc1_Bgstd_ulogic_vector(1 downto 0)
Definition: top.vhdl:161
topFMKU60.poDDR4_Mem_Mc1_Odt
out poDDR4_Mem_Mc1_Odtstd_ulogic
Definition: top.vhdl:163
topFMKU60.poDDR4_Mem_Mc1_Reset_n
out poDDR4_Mem_Mc1_Reset_nstd_ulogic
Definition: top.vhdl:167
topFMKU60.piCLKT_10GeClk_n
in piCLKT_10GeClk_nstd_ulogic
Definition: top.vhdl:106
topFMKU60.poDDR4_Mem_Mc0_Cke
out poDDR4_Mem_Mc0_Ckestd_ulogic
Definition: top.vhdl:144
topFMKU60.piCLKT_Mem1Clk_n
in piCLKT_Mem1Clk_nstd_ulogic
Definition: top.vhdl:100