cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
Generics | Libraries | Ports | Use Clauses
topFMKU60 Entity Reference

Libraries

IEEE 
UNISIM 
XIL_DEFAULTLIB 

Use Clauses

std_logic_1164 
numeric_std 
vcomponents 
topFMKU_pkg  Package <topFMKU_pkg>

Generics

gBitstreamUsage  string := " flash "
gSecurityPriviledges  string := " super "
gTopDateYear  stDate := 8d " 00 "
gTopDateMonth  stDate := 8d " 00 "
gTopDateDay  stDate := 8d " 00 "
gEmifAddrWidth  integer := 8
gEmifDataWidth  integer := 8
gVivadoVersion  integer := 2019

Ports

piPSOC_Fcfg_Rst_n   in   std_ulogic
piCLKT_Mem0Clk_n   in   std_ulogic
piCLKT_Mem0Clk_p   in   std_ulogic
piCLKT_Mem1Clk_n   in   std_ulogic
piCLKT_Mem1Clk_p   in   std_ulogic
piCLKT_10GeClk_n   in   std_ulogic
piCLKT_10GeClk_p   in   std_ulogic
piCLKT_Usr0Clk_n   in   std_ulogic
piCLKT_Usr0Clk_p   in   std_ulogic
piCLKT_Usr1Clk_n   in   std_ulogic
piCLKT_Usr1Clk_p   in   std_ulogic
piPSOC_Emif_Clk   in   std_ulogic
piPSOC_Emif_Cs_n   in   std_ulogic
piPSOC_Emif_We_n   in   std_ulogic
piPSOC_Emif_Oe_n   in   std_ulogic
piPSOC_Emif_AdS_n   in   std_ulogic
piPSOC_Emif_Addr   in   std_ulogic_vector ( gEmifAddrWidth - 1 downto 0 )
pioPSOC_Emif_Data   inout   std_ulogic_vector ( gEmifDataWidth - 1 downto 0 )
poLED_HeartBeat_n   out   std_ulogic
pioDDR4_Mem_Mc0_DmDbi_n   inout   std_ulogic_vector ( 8 downto 0 )
pioDDR4_Mem_Mc0_Dq   inout   std_ulogic_vector ( 71 downto 0 )
pioDDR4_Mem_Mc0_Dqs_p   inout   std_ulogic_vector ( 8 downto 0 )
pioDDR4_Mem_Mc0_Dqs_n   inout   std_ulogic_vector ( 8 downto 0 )
poDDR4_Mem_Mc0_Act_n   out   std_ulogic
poDDR4_Mem_Mc0_Adr   out   std_ulogic_vector ( 16 downto 0 )
poDDR4_Mem_Mc0_Ba   out   std_ulogic_vector ( 1 downto 0 )
poDDR4_Mem_Mc0_Bg   out   std_ulogic_vector ( 1 downto 0 )
poDDR4_Mem_Mc0_Cke   out   std_ulogic
poDDR4_Mem_Mc0_Odt   out   std_ulogic
poDDR4_Mem_Mc0_Cs_n   out   std_ulogic
poDDR4_Mem_Mc0_Ck_p   out   std_ulogic
poDDR4_Mem_Mc0_Ck_n   out   std_ulogic
poDDR4_Mem_Mc0_Reset_n   out   std_ulogic
pioDDR4_Mem_Mc1_DmDbi_n   inout   std_ulogic_vector ( 8 downto 0 )
pioDDR4_Mem_Mc1_Dq   inout   std_ulogic_vector ( 71 downto 0 )
pioDDR4_Mem_Mc1_Dqs_p   inout   std_ulogic_vector ( 8 downto 0 )
pioDDR4_Mem_Mc1_Dqs_n   inout   std_ulogic_vector ( 8 downto 0 )
poDDR4_Mem_Mc1_Act_n   out   std_ulogic
poDDR4_Mem_Mc1_Adr   out   std_ulogic_vector ( 16 downto 0 )
poDDR4_Mem_Mc1_Ba   out   std_ulogic_vector ( 1 downto 0 )
poDDR4_Mem_Mc1_Bg   out   std_ulogic_vector ( 1 downto 0 )
poDDR4_Mem_Mc1_Cke   out   std_ulogic
poDDR4_Mem_Mc1_Odt   out   std_ulogic
poDDR4_Mem_Mc1_Cs_n   out   std_ulogic
poDDR4_Mem_Mc1_Ck_p   out   std_ulogic
poDDR4_Mem_Mc1_Ck_n   out   std_ulogic
poDDR4_Mem_Mc1_Reset_n   out   std_ulogic
piECON_Eth_10Ge0_n   in   std_ulogic
piECON_Eth_10Ge0_p   in   std_ulogic
poECON_Eth_10Ge0_n   out   std_ulogic
poECON_Eth_10Ge0_p   out   std_ulogic

Detailed Description

Definition at line 75 of file top.vhdl.

Member Data Documentation

◆ gBitstreamUsage

gBitstreamUsage string := " flash "
Generic

Definition at line 78 of file top.vhdl.

◆ gEmifAddrWidth

gEmifAddrWidth integer := 8
Generic

Definition at line 85 of file top.vhdl.

◆ gEmifDataWidth

gEmifDataWidth integer := 8
Generic

Definition at line 87 of file top.vhdl.

◆ gSecurityPriviledges

gSecurityPriviledges string := " super "
Generic

Definition at line 79 of file top.vhdl.

◆ gTopDateDay

gTopDateDay stDate := 8d " 00 "
Generic

Definition at line 83 of file top.vhdl.

◆ gTopDateMonth

gTopDateMonth stDate := 8d " 00 "
Generic

Definition at line 82 of file top.vhdl.

◆ gTopDateYear

gTopDateYear stDate := 8d " 00 "
Generic

Definition at line 81 of file top.vhdl.

◆ gVivadoVersion

gVivadoVersion integer := 2019
Generic

Definition at line 83 of file top.vhdl.

◆ IEEE

IEEE
Library

Definition at line 57 of file top.vhdl.

◆ numeric_std

numeric_std
use clause

Definition at line 59 of file top.vhdl.

◆ piCLKT_10GeClk_n

piCLKT_10GeClk_n in std_ulogic
Port

Definition at line 106 of file top.vhdl.

◆ piCLKT_10GeClk_p

piCLKT_10GeClk_p in std_ulogic
Port

Definition at line 107 of file top.vhdl.

◆ piCLKT_Mem0Clk_n

piCLKT_Mem0Clk_n in std_ulogic
Port

Definition at line 98 of file top.vhdl.

◆ piCLKT_Mem0Clk_p

piCLKT_Mem0Clk_p in std_ulogic
Port

Definition at line 99 of file top.vhdl.

◆ piCLKT_Mem1Clk_n

piCLKT_Mem1Clk_n in std_ulogic
Port

Definition at line 100 of file top.vhdl.

◆ piCLKT_Mem1Clk_p

piCLKT_Mem1Clk_p in std_ulogic
Port

Definition at line 101 of file top.vhdl.

◆ piCLKT_Usr0Clk_n

piCLKT_Usr0Clk_n in std_ulogic
Port

Definition at line 112 of file top.vhdl.

◆ piCLKT_Usr0Clk_p

piCLKT_Usr0Clk_p in std_ulogic
Port

Definition at line 113 of file top.vhdl.

◆ piCLKT_Usr1Clk_n

piCLKT_Usr1Clk_n in std_ulogic
Port

Definition at line 114 of file top.vhdl.

◆ piCLKT_Usr1Clk_p

piCLKT_Usr1Clk_p in std_ulogic
Port

Definition at line 115 of file top.vhdl.

◆ piECON_Eth_10Ge0_n

piECON_Eth_10Ge0_n in std_ulogic
Port

Definition at line 172 of file top.vhdl.

◆ piECON_Eth_10Ge0_p

piECON_Eth_10Ge0_p in std_ulogic
Port

Definition at line 173 of file top.vhdl.

◆ pioDDR4_Mem_Mc0_DmDbi_n

pioDDR4_Mem_Mc0_DmDbi_n inout std_ulogic_vector ( 8 downto 0 )
Port

Definition at line 136 of file top.vhdl.

◆ pioDDR4_Mem_Mc0_Dq

pioDDR4_Mem_Mc0_Dq inout std_ulogic_vector ( 71 downto 0 )
Port

Definition at line 137 of file top.vhdl.

◆ pioDDR4_Mem_Mc0_Dqs_n

pioDDR4_Mem_Mc0_Dqs_n inout std_ulogic_vector ( 8 downto 0 )
Port

Definition at line 139 of file top.vhdl.

◆ pioDDR4_Mem_Mc0_Dqs_p

pioDDR4_Mem_Mc0_Dqs_p inout std_ulogic_vector ( 8 downto 0 )
Port

Definition at line 138 of file top.vhdl.

◆ pioDDR4_Mem_Mc1_DmDbi_n

pioDDR4_Mem_Mc1_DmDbi_n inout std_ulogic_vector ( 8 downto 0 )
Port

Definition at line 154 of file top.vhdl.

◆ pioDDR4_Mem_Mc1_Dq

pioDDR4_Mem_Mc1_Dq inout std_ulogic_vector ( 71 downto 0 )
Port

Definition at line 155 of file top.vhdl.

◆ pioDDR4_Mem_Mc1_Dqs_n

pioDDR4_Mem_Mc1_Dqs_n inout std_ulogic_vector ( 8 downto 0 )
Port

Definition at line 157 of file top.vhdl.

◆ pioDDR4_Mem_Mc1_Dqs_p

pioDDR4_Mem_Mc1_Dqs_p inout std_ulogic_vector ( 8 downto 0 )
Port

Definition at line 156 of file top.vhdl.

◆ pioPSOC_Emif_Data

pioPSOC_Emif_Data inout std_ulogic_vector ( gEmifDataWidth - 1 downto 0 )
Port

Definition at line 126 of file top.vhdl.

◆ piPSOC_Emif_Addr

piPSOC_Emif_Addr in std_ulogic_vector ( gEmifAddrWidth - 1 downto 0 )
Port

Definition at line 125 of file top.vhdl.

◆ piPSOC_Emif_AdS_n

piPSOC_Emif_AdS_n in std_ulogic
Port

Definition at line 124 of file top.vhdl.

◆ piPSOC_Emif_Clk

piPSOC_Emif_Clk in std_ulogic
Port

Definition at line 120 of file top.vhdl.

◆ piPSOC_Emif_Cs_n

piPSOC_Emif_Cs_n in std_ulogic
Port

Definition at line 121 of file top.vhdl.

◆ piPSOC_Emif_Oe_n

piPSOC_Emif_Oe_n in std_ulogic
Port

Definition at line 123 of file top.vhdl.

◆ piPSOC_Emif_We_n

piPSOC_Emif_We_n in std_ulogic
Port

Definition at line 122 of file top.vhdl.

◆ piPSOC_Fcfg_Rst_n

piPSOC_Fcfg_Rst_n in std_ulogic
Port

Definition at line 93 of file top.vhdl.

◆ poDDR4_Mem_Mc0_Act_n

poDDR4_Mem_Mc0_Act_n out std_ulogic
Port

Definition at line 140 of file top.vhdl.

◆ poDDR4_Mem_Mc0_Adr

poDDR4_Mem_Mc0_Adr out std_ulogic_vector ( 16 downto 0 )
Port

Definition at line 141 of file top.vhdl.

◆ poDDR4_Mem_Mc0_Ba

poDDR4_Mem_Mc0_Ba out std_ulogic_vector ( 1 downto 0 )
Port

Definition at line 142 of file top.vhdl.

◆ poDDR4_Mem_Mc0_Bg

poDDR4_Mem_Mc0_Bg out std_ulogic_vector ( 1 downto 0 )
Port

Definition at line 143 of file top.vhdl.

◆ poDDR4_Mem_Mc0_Ck_n

poDDR4_Mem_Mc0_Ck_n out std_ulogic
Port

Definition at line 148 of file top.vhdl.

◆ poDDR4_Mem_Mc0_Ck_p

poDDR4_Mem_Mc0_Ck_p out std_ulogic
Port

Definition at line 147 of file top.vhdl.

◆ poDDR4_Mem_Mc0_Cke

poDDR4_Mem_Mc0_Cke out std_ulogic
Port

Definition at line 144 of file top.vhdl.

◆ poDDR4_Mem_Mc0_Cs_n

poDDR4_Mem_Mc0_Cs_n out std_ulogic
Port

Definition at line 146 of file top.vhdl.

◆ poDDR4_Mem_Mc0_Odt

poDDR4_Mem_Mc0_Odt out std_ulogic
Port

Definition at line 145 of file top.vhdl.

◆ poDDR4_Mem_Mc0_Reset_n

poDDR4_Mem_Mc0_Reset_n out std_ulogic
Port

Definition at line 149 of file top.vhdl.

◆ poDDR4_Mem_Mc1_Act_n

poDDR4_Mem_Mc1_Act_n out std_ulogic
Port

Definition at line 158 of file top.vhdl.

◆ poDDR4_Mem_Mc1_Adr

poDDR4_Mem_Mc1_Adr out std_ulogic_vector ( 16 downto 0 )
Port

Definition at line 159 of file top.vhdl.

◆ poDDR4_Mem_Mc1_Ba

poDDR4_Mem_Mc1_Ba out std_ulogic_vector ( 1 downto 0 )
Port

Definition at line 160 of file top.vhdl.

◆ poDDR4_Mem_Mc1_Bg

poDDR4_Mem_Mc1_Bg out std_ulogic_vector ( 1 downto 0 )
Port

Definition at line 161 of file top.vhdl.

◆ poDDR4_Mem_Mc1_Ck_n

poDDR4_Mem_Mc1_Ck_n out std_ulogic
Port

Definition at line 166 of file top.vhdl.

◆ poDDR4_Mem_Mc1_Ck_p

poDDR4_Mem_Mc1_Ck_p out std_ulogic
Port

Definition at line 165 of file top.vhdl.

◆ poDDR4_Mem_Mc1_Cke

poDDR4_Mem_Mc1_Cke out std_ulogic
Port

Definition at line 162 of file top.vhdl.

◆ poDDR4_Mem_Mc1_Cs_n

poDDR4_Mem_Mc1_Cs_n out std_ulogic
Port

Definition at line 164 of file top.vhdl.

◆ poDDR4_Mem_Mc1_Odt

poDDR4_Mem_Mc1_Odt out std_ulogic
Port

Definition at line 163 of file top.vhdl.

◆ poDDR4_Mem_Mc1_Reset_n

poDDR4_Mem_Mc1_Reset_n out std_ulogic
Port

Definition at line 167 of file top.vhdl.

◆ poECON_Eth_10Ge0_n

poECON_Eth_10Ge0_n out std_ulogic
Port

Definition at line 174 of file top.vhdl.

◆ poECON_Eth_10Ge0_p

poECON_Eth_10Ge0_p out std_ulogic
Port

Definition at line 177 of file top.vhdl.

◆ poLED_HeartBeat_n

poLED_HeartBeat_n out std_ulogic
Port

Definition at line 131 of file top.vhdl.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 58 of file top.vhdl.

◆ topFMKU_pkg

topFMKU_pkg
use clause

Definition at line 68 of file top.vhdl.

◆ UNISIM

UNISIM
Library

Definition at line 61 of file top.vhdl.

◆ vcomponents

vcomponents
use clause

Definition at line 62 of file top.vhdl.

◆ XIL_DEFAULTLIB

XIL_DEFAULTLIB
Library

Definition at line 67 of file top.vhdl.

The documentation for this class was generated from the following file: