cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
Role.vhdl
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1 /*
2  * Copyright 2016 -- 2021 IBM Corporation
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 -- *****************************************************************************
18 -- *
19 -- * Title : Role for the bring-up of the FMKU2595 when equipped with a XCKU060.
20 -- *
21 -- * File : Role.vhdl
22 -- *
23 -- * Tools : Vivado v2016.4, v2017.4, v2019.2 (64-bit)
24 -- *
25 -- * Description : In cloudFPGA, the user application is referred to as a 'role'
26 -- * and is integrated along with a 'shell' that abstracts the HW components
27 -- * of the FPGA module.
28 -- * The current role implements a set of TCP, UDP and DDR4 tests for the
29 -- * bring-up of the FPGA module FMKU60. This role is typically paired with
30 -- * the shell 'Kale' by the cloudFPGA project 'cFp_HelloKale'.
31 -- *
32 -- *****************************************************************************
33 
34 --******************************************************************************
35 --** CONTEXT CLAUSE ** FMKU60 ROLE(BringUp)
36 --******************************************************************************
37 library IEEE;
38 use IEEE.std_logic_1164.all;
39 use IEEE.numeric_std.all;
40 
41 library UNISIM;
42 use UNISIM.vcomponents.all;
43 
44 library XIL_DEFAULTLIB;
45 use XIL_DEFAULTLIB.all;
46 
47 
48 --******************************************************************************
49 --** ENTITY ** ROLE_KALE
50 --******************************************************************************
51 entity Role_Kale is
52  generic (
53  gVivadoVersion : integer := 2019
54  );
55  port (
56  --------------------------------------------------------
57  -- SHELL / Clock, Reset and Enable Interface
58  --------------------------------------------------------
59  piSHL_156_25Clk : in std_ulogic;
60  piSHL_156_25Rst : in std_ulogic;
61  ------------------------------------------------------
62  -- SHELL / Nts / Udp / Tx Data Interfaces (.i.e SHELL-->ROLE)
63  ------------------------------------------------------
64  ---- Axi4-Stream UDP Data ----------------
65  siSHL_Nts_Udp_Data_tdata : in std_ulogic_vector( 63 downto 0);
66  siSHL_Nts_Udp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
67  siSHL_Nts_Udp_Data_tlast : in std_ulogic;
68  siSHL_Nts_Udp_Data_tvalid : in std_ulogic;
69  siSHL_Nts_Udp_Data_tready : out std_ulogic;
70  ---- Axi4-Stream UDP Metadata ------------
71  siSHL_Nts_Udp_Meta_tdata : in std_ulogic_vector( 95 downto 0);
72  siSHL_Nts_Udp_Meta_tvalid : in std_ulogic;
73  siSHL_Nts_Udp_Meta_tready : out std_ulogic;
74  ---- Axi4-Stream UDP Data Len ------------
75  siSHL_Nts_Udp_DLen_tdata : in std_ulogic_vector( 15 downto 0);
76  siSHL_Nts_Udp_DLen_tvalid : in std_ulogic;
77  siSHL_Nts_Udp_DLen_tready : out std_ulogic;
78  ------------------------------------------------------
79  -- SHELL / Nts / Udp / Rx Data Interfaces (.i.e ROLE-->SHELL)
80  ------------------------------------------------------
81  ---- Axi4-Stream UDP Data ---------------
82  soSHL_Nts_Udp_Data_tdata : out std_ulogic_vector( 63 downto 0);
83  soSHL_Nts_Udp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
84  soSHL_Nts_Udp_Data_tlast : out std_ulogic;
85  soSHL_Nts_Udp_Data_tvalid : out std_ulogic;
86  soSHL_Nts_Udp_Data_tready : in std_ulogic;
87  ---- Axi4-Stream UDP Meta ---------------
88  soSHL_Nts_Udp_Meta_tdata : out std_ulogic_vector( 95 downto 0);
89  soSHL_Nts_Udp_Meta_tvalid : out std_ulogic;
90  soSHL_Nts_Udp_Meta_tready : in std_ulogic;
91  ---- Axi4-Stream UDP Data Length ---------
92  soSHL_Nts_Udp_DLen_tdata : out std_ulogic_vector( 15 downto 0);
93  soSHL_Nts_Udp_DLen_tvalid : out std_ulogic;
94  soSHL_Nts_Udp_DLen_tready : in std_ulogic;
95  ------------------------------------------------------
96  -- SHELL / Nts/ Udp / Rx Ctrl Interfaces (.i.e ROLE<-->SHELL)
97  ------------------------------------------------------
98  ---- Axi4-Stream UDP Listen Request -----
99  soSHL_Nts_Udp_LsnReq_tdata : out std_ulogic_vector( 15 downto 0);
100  soSHL_Nts_Udp_LsnReq_tvalid : out std_ulogic;
101  soSHL_Nts_Udp_LsnReq_tready : in std_ulogic;
102  ---- Axi4-Stream UDP Listen Reply --------
103  siSHL_Nts_Udp_LsnRep_tdata : in std_ulogic_vector( 7 downto 0);
104  siSHL_Nts_Udp_LsnRep_tvalid : in std_ulogic;
105  siSHL_Nts_Udp_LsnRep_tready : out std_ulogic;
106  ---- Axi4-Stream UDP Close Request ------
107  soSHL_Nts_Udp_ClsReq_tdata : out std_ulogic_vector( 15 downto 0);
108  soSHL_Nts_Udp_ClsReq_tvalid : out std_ulogic;
109  soSHL_Nts_Udp_ClsReq_tready : in std_ulogic;
110  ---- Axi4-Stream UDP Close Reply --------
111  siSHL_Nts_Udp_ClsRep_tdata : in std_ulogic_vector( 7 downto 0);
112  siSHL_Nts_Udp_ClsRep_tvalid : in std_ulogic;
113  siSHL_Nts_Udp_ClsRep_tready : out std_ulogic;
114  ------------------------------------------------------
115  -- SHELL / Nts / Tcp / Tx Data Interfaces (.i.e ROLE-->SHELL)
116  ------------------------------------------------------
117  ---- Axi4-Stream TCP Data ---------------
118  soSHL_Nts_Tcp_Data_tdata : out std_ulogic_vector( 63 downto 0);
119  soSHL_Nts_Tcp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
120  soSHL_Nts_Tcp_Data_tlast : out std_ulogic;
121  soSHL_Nts_Tcp_Data_tvalid : out std_ulogic;
122  soSHL_Nts_Tcp_Data_tready : in std_ulogic;
123  ---- Axi4-Stream TCP Send Request -------
124  soSHL_Nts_Tcp_SndReq_tdata : out std_ulogic_vector( 31 downto 0);
125  soSHL_Nts_Tcp_SndReq_tvalid : out std_ulogic;
126  soSHL_Nts_Tcp_SndReq_tready : in std_ulogic;
127  ---- Axi4-Stream TCP Send Reply ---------
128  siSHL_Nts_Tcp_SndRep_tdata : in std_ulogic_vector( 55 downto 0);
129  siSHL_Nts_Tcp_SndRep_tvalid : in std_ulogic;
130  siSHL_Nts_Tcp_SndRep_tready : out std_ulogic;
131  --------------------------------------------------------
132  -- SHELL / Nts / Tcp / Rx Data Interfaces (.i.e SHELL-->ROLE)
133  --------------------------------------------------------
134  ---- Axi4-Stream TCP Data -----------------
135  siSHL_Nts_Tcp_Data_tdata : in std_ulogic_vector( 63 downto 0);
136  siSHL_Nts_Tcp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
137  siSHL_Nts_Tcp_Data_tlast : in std_ulogic;
138  siSHL_Nts_Tcp_Data_tvalid : in std_ulogic;
139  siSHL_Nts_Tcp_Data_tready : out std_ulogic;
140  ---- Axi4-Stream TCP Metadata ------------
141  siSHL_Nts_Tcp_Meta_tdata : in std_ulogic_vector( 15 downto 0);
142  siSHL_Nts_Tcp_Meta_tvalid : in std_ulogic;
143  siSHL_Nts_Tcp_Meta_tready : out std_ulogic;
144  ---- Axi4-Stream TCP Data Notification ---
145  siSHL_Nts_Tcp_Notif_tdata : in std_ulogic_vector(7+96 downto 0);
146  siSHL_Nts_Tcp_Notif_tvalid : in std_ulogic;
147  siSHL_Nts_Tcp_Notif_tready : out std_ulogic;
148  ---- Axi4-Stream TCP Data Request --------
149  soSHL_Nts_Tcp_DReq_tdata : out std_ulogic_vector( 31 downto 0);
150  soSHL_Nts_Tcp_DReq_tvalid : out std_ulogic;
151  soSHL_Nts_Tcp_DReq_tready : in std_ulogic;
152  ------------------------------------------------------
153  -- SHELL / Nts / Tcp / TxP Ctlr Interfaces (.i.e ROLE<-->SHELL)
154  ------------------------------------------------------
155  ---- Axi4-Stream TCP Open Session Request
156  soSHL_Nts_Tcp_OpnReq_tdata : out std_ulogic_vector( 47 downto 0);
157  soSHL_Nts_Tcp_OpnReq_tvalid : out std_ulogic;
158  soSHL_Nts_Tcp_OpnReq_tready : in std_ulogic;
159  ---- Axi4-Stream TCP Open Session Reply
160  siSHL_Nts_Tcp_OpnRep_tdata : in std_ulogic_vector( 23 downto 0);
161  siSHL_Nts_Tcp_OpnRep_tvalid : in std_ulogic;
162  siSHL_Nts_Tcp_OpnRep_tready : out std_ulogic;
163  ---- Axi4-Stream TCP Close Request ------
164  soSHL_Nts_Tcp_ClsReq_tdata : out std_ulogic_vector( 15 downto 0);
165  soSHL_Nts_Tcp_ClsReq_tvalid : out std_ulogic;
166  soSHL_Nts_Tcp_ClsReq_tready : in std_ulogic;
167  ------------------------------------------------------
168  -- SHELL / Nts / Tcp / Rx Ctlr Interfaces (.i.e SHELL-->ROLE)
169  ------------------------------------------------------
170  ---- Axi4-Stream TCP Listen Request ----
171  soSHL_Nts_Tcp_LsnReq_tdata : out std_ulogic_vector( 15 downto 0);
172  soSHL_Nts_Tcp_LsnReq_tvalid : out std_ulogic;
173  soSHL_Nts_Tcp_LsnReq_tready : in std_ulogic;
174  ---- Axi4-Stream TCP Listen Rep --------
175  siSHL_Nts_Tcp_LsnRep_tdata : in std_ulogic_vector( 7 downto 0);
176  siSHL_Nts_Tcp_LsnRep_tvalid : in std_ulogic;
177  siSHL_Nts_Tcp_LsnRep_tready : out std_ulogic;
178  --------------------------------------------------------
179  -- SHELL / Mem / Mp0 Interface
180  --------------------------------------------------------
181  ---- Memory Port #0 / S2MM-AXIS ----------------
182  ------ Stream Read Command ---------
183  soSHL_Mem_Mp0_RdCmd_tdata : out std_ulogic_vector( 79 downto 0);
184  soSHL_Mem_Mp0_RdCmd_tvalid : out std_ulogic;
185  soSHL_Mem_Mp0_RdCmd_tready : in std_ulogic;
186  ------ Stream Read Status ----------
187  siSHL_Mem_Mp0_RdSts_tdata : in std_ulogic_vector( 7 downto 0);
188  siSHL_Mem_Mp0_RdSts_tvalid : in std_ulogic;
189  siSHL_Mem_Mp0_RdSts_tready : out std_ulogic;
190  ------ Stream Read Data ------------
191  siSHL_Mem_Mp0_Read_tdata : in std_ulogic_vector(511 downto 0);
192  siSHL_Mem_Mp0_Read_tkeep : in std_ulogic_vector( 63 downto 0);
193  siSHL_Mem_Mp0_Read_tlast : in std_ulogic;
194  siSHL_Mem_Mp0_Read_tvalid : in std_ulogic;
195  siSHL_Mem_Mp0_Read_tready : out std_ulogic;
196  ------ Stream Write Command --------
197  soSHL_Mem_Mp0_WrCmd_tdata : out std_ulogic_vector( 79 downto 0);
198  soSHL_Mem_Mp0_WrCmd_tvalid : out std_ulogic;
199  soSHL_Mem_Mp0_WrCmd_tready : in std_ulogic;
200  ------ Stream Write Status ---------
201  siSHL_Mem_Mp0_WrSts_tdata : in std_ulogic_vector( 7 downto 0);
202  siSHL_Mem_Mp0_WrSts_tvalid : in std_ulogic;
203  siSHL_Mem_Mp0_WrSts_tready : out std_ulogic;
204  ------ Stream Write Data -----------
205  soSHL_Mem_Mp0_Write_tdata : out std_ulogic_vector(511 downto 0);
206  soSHL_Mem_Mp0_Write_tkeep : out std_ulogic_vector( 63 downto 0);
207  soSHL_Mem_Mp0_Write_tlast : out std_ulogic;
208  soSHL_Mem_Mp0_Write_tvalid : out std_ulogic;
209  soSHL_Mem_Mp0_Write_tready : in std_ulogic;
210  --------------------------------------------------------
211  -- SHELL / Mem / Mp1 Interface
212  --------------------------------------------------------
213  ---- Write Address Channel ---------
214  moSHL_Mem_Mp1_AWID : out std_ulogic_vector( 7 downto 0);
215  moSHL_Mem_Mp1_AWADDR : out std_ulogic_vector( 32 downto 0);
216  moSHL_Mem_Mp1_AWLEN : out std_ulogic_vector( 7 downto 0);
217  moSHL_Mem_Mp1_AWSIZE : out std_ulogic_vector( 2 downto 0);
218  moSHL_Mem_Mp1_AWBURST : out std_ulogic_vector( 1 downto 0);
219  moSHL_Mem_Mp1_AWVALID : out std_ulogic;
220  moSHL_Mem_Mp1_AWREADY : in std_ulogic;
221  ---- Write Data Channel ------------
222  moSHL_Mem_Mp1_WDATA : out std_ulogic_vector(511 downto 0);
223  moSHL_Mem_Mp1_WSTRB : out std_ulogic_vector( 63 downto 0);
224  moSHL_Mem_Mp1_WLAST : out std_ulogic;
225  moSHL_Mem_Mp1_WVALID : out std_ulogic;
226  moSHL_Mem_Mp1_WREADY : in std_ulogic;
227  ---- Write Response Channel --------
228  moSHL_Mem_Mp1_BID : in std_ulogic_vector( 7 downto 0);
229  moSHL_Mem_Mp1_BRESP : in std_ulogic_vector( 1 downto 0);
230  moSHL_Mem_Mp1_BVALID : in std_ulogic;
231  moSHL_Mem_Mp1_BREADY : out std_ulogic;
232  ---- Read Address Channel ----------
233  moSHL_Mem_Mp1_ARID : out std_ulogic_vector( 7 downto 0);
234  moSHL_Mem_Mp1_ARADDR : out std_ulogic_vector( 32 downto 0);
235  moSHL_Mem_Mp1_ARLEN : out std_ulogic_vector( 7 downto 0);
236  moSHL_Mem_Mp1_ARSIZE : out std_ulogic_vector( 2 downto 0);
237  moSHL_Mem_Mp1_ARBURST : out std_ulogic_vector( 1 downto 0);
238  moSHL_Mem_Mp1_ARVALID : out std_ulogic;
239  moSHL_Mem_Mp1_ARREADY : in std_ulogic;
240  ---- Read Data Channel -------------
241  moSHL_Mem_Mp1_RID : in std_ulogic_vector( 7 downto 0);
242  moSHL_Mem_Mp1_RDATA : in std_ulogic_vector(511 downto 0);
243  moSHL_Mem_Mp1_RRESP : in std_ulogic_vector( 1 downto 0);
244  moSHL_Mem_Mp1_RLAST : in std_ulogic;
245  moSHL_Mem_Mp1_RVALID : in std_ulogic;
246  moSHL_Mem_Mp1_RREADY : out std_ulogic;
247 
248  --------------------------------------------------------
249  -- SHELL / Mmio / AppFlash Interface
250  --------------------------------------------------------
251  ---- [PHY_RESET] -------------------
252  piSHL_Mmio_Ly7Rst : in std_ulogic;
253  ---- [PHY_ENABLE] ------------------
254  piSHL_Mmio_Ly7En : in std_ulogic;
255  ---- [DIAG_CTRL_1] -----------------
256  piSHL_Mmio_Mc1_MemTestCtrl : in std_ulogic_vector( 1 downto 0);
257  ---- [DIAG_STAT_1] -----------------
258  poSHL_Mmio_Mc1_MemTestStat : out std_ulogic_vector( 1 downto 0);
259  ---- [DIAG_CTRL_2] -----------------
260  --[NOT_USED] piSHL_Mmio_UdpEchoCtrl : in std_ulogic_vector( 1 downto 0);
261  --[NOT_USED] piSHL_Mmio_UdpPostDgmEn : in std_ulogic;
262  --[NOT_USED] piSHL_Mmio_UdpCaptDgmEn : in std_ulogic;
263  --[NOT_USED] piSHL_Mmio_TcpEchoCtrl : in std_ulogic_vector( 1 downto 0);
264  --[NOT_USED] piSHL_Mmio_TcpPostSegEn : in std_ulogic;
265  --[NOT_USED] piSHL_Mmio_TcpCaptSegEn : in std_ulogic;
266  ---- [APP_RDROL] -------------------
267  poSHL_Mmio_RdReg : out std_ulogic_vector( 15 downto 0);
268  --- [APP_WRROL] --------------------
269  piSHL_Mmio_WrReg : in std_ulogic_vector( 15 downto 0);
270  --------------------------------------------------------
271  -- TOP : Secondary Clock (Asynchronous)
272  --------------------------------------------------------
273  piTOP_250_00Clk : in std_ulogic -- Freerunning
274  );
275 end Role_Kale;
276 
277 
278 -- *****************************************************************************
279 -- ** ARCHITECTURE ** BRING_UP of ROLE_KALE
280 -- *****************************************************************************
281 
282 architecture BringUp of Role_Kale is
283 
284  --============================================================================
285  -- SIGNAL DECLARATIONS
286  --============================================================================
287  -- Delayed reset signal and counter
288  signal s156_25Rst_delayed : std_ulogic;
289  signal sRstDelayCounter : std_ulogic_vector(5 downto 0);
290 
291  --------------------------------------------------------
292  -- SIGNAL DECLARATIONS : TSIF --> TARS --> TAF
293  --------------------------------------------------------
294  signal ssTSIF_TARS_Data_tdata : std_ulogic_vector( 63 downto 0);
295  signal ssTSIF_TARS_Data_tkeep : std_ulogic_vector( 7 downto 0);
296  signal ssTSIF_TARS_Data_tlast : std_ulogic;
297  signal ssTSIF_TARS_Data_tvalid : std_ulogic;
298  signal ssTSIF_TARS_Data_tready : std_ulogic;
299  --
300  signal ssTSIF_TARS_SessId_tdata : std_ulogic_vector( 15 downto 0);
301  signal ssTSIF_TARS_SessId_tvalid : std_ulogic;
302  signal ssTSIF_TARS_SessId_tready : std_ulogic;
303  --
304  signal ssTSIF_TARS_DatLen_tdata : std_ulogic_vector( 15 downto 0);
305  signal ssTSIF_TARS_DatLen_tvalid : std_ulogic;
306  signal ssTSIF_TARS_DatLen_tready : std_ulogic;
307  -- -------------------------------------------
308  signal ssTARS_TAF_Data_tdata : std_ulogic_vector( 63 downto 0);
309  signal ssTARS_TAF_Data_tkeep : std_ulogic_vector( 7 downto 0);
310  signal ssTARS_TAF_Data_tlast : std_ulogic;
311  signal ssTARS_TAF_Data_tvalid : std_ulogic;
312  signal ssTARS_TAF_Data_tready : std_ulogic;
313  --
314  signal ssTARS_TAF_SessId_tdata : std_ulogic_vector( 15 downto 0);
315  signal ssTARS_TAF_SessId_tvalid : std_ulogic;
316  signal ssTARS_TAF_SessId_tready : std_ulogic;
317  --
318  signal ssTARS_TAF_DatLen_tdata : std_ulogic_vector( 15 downto 0);
319  signal ssTARS_TAF_DatLen_tvalid : std_ulogic;
320  signal ssTARS_TAF_DatLen_tready : std_ulogic;
321 
322  --------------------------------------------------------
323  -- SIGNAL DECLARATIONS : TSIF --> ARS --> DEBUG
324  --------------------------------------------------------
325  signal ssTSIF_ARS_SinkCnt_tdata : std_ulogic_vector( 31 downto 0);
326  signal ssTSIF_ARS_SinkCnt_tvalid : std_ulogic;
327  signal ssTSIF_ARS_SinkCnt_tready : std_ulogic;
328 
329  --------------------------------------------------------
330  -- SIGNAL DECLARATIONS : TAF --> TARS --> TSIF
331  --------------------------------------------------------
332  signal ssTAF_TARS_Data_tdata : std_ulogic_vector( 63 downto 0);
333  signal ssTAF_TARS_Data_tkeep : std_ulogic_vector( 7 downto 0);
334  signal ssTAF_TARS_Data_tlast : std_ulogic;
335  signal ssTAF_TARS_Data_tvalid : std_ulogic;
336  signal ssTAF_TARS_Data_tready : std_ulogic;
337  --
338  signal ssTAF_TARS_SessId_tdata : std_ulogic_vector( 15 downto 0);
339  signal ssTAF_TARS_SessId_tvalid : std_ulogic;
340  signal ssTAF_TARS_SessId_tready : std_ulogic;
341  --
342  signal ssTAF_TARS_DatLen_tdata : std_ulogic_vector( 15 downto 0);
343  signal ssTAF_TARS_DatLen_tvalid : std_ulogic;
344  signal ssTAF_TARS_DatLen_tready : std_ulogic;
345  -- -------------------------------------------
346  signal ssTARS_TSIF_Data_tdata : std_ulogic_vector( 63 downto 0);
347  signal ssTARS_TSIF_Data_tkeep : std_ulogic_vector( 7 downto 0);
348  signal ssTARS_TSIF_Data_tlast : std_ulogic;
349  signal ssTARS_TSIF_Data_tvalid : std_ulogic;
350  signal ssTARS_TSIF_Data_tready : std_ulogic;
351  --
352  signal ssTARS_TSIF_SessId_tdata : std_ulogic_vector( 15 downto 0);
353  signal ssTARS_TSIF_SessId_tvalid : std_ulogic;
354  signal ssTARS_TSIF_SessId_tready : std_ulogic;
355  --
356  signal ssTARS_TSIF_DatLen_tdata : std_ulogic_vector( 15 downto 0);
357  signal ssTARS_TSIF_DatLen_tvalid : std_ulogic;
358  signal ssTARS_TSIF_DatLen_tready : std_ulogic;
359 
360  --------------------------------------------------------
361  -- SIGNAL DECLARATIONS : USIF --> UARS --> UAF
362  --------------------------------------------------------
363  signal ssUSIF_UARS_Data_tdata : std_ulogic_vector( 63 downto 0);
364  signal ssUSIF_UARS_Data_tkeep : std_ulogic_vector( 7 downto 0);
365  signal ssUSIF_UARS_Data_tlast : std_ulogic;
366  signal ssUSIF_UARS_Data_tvalid : std_ulogic;
367  signal ssUSIF_UARS_Data_tready : std_ulogic;
368  --
369  signal ssUSIF_UARS_Meta_tdata : std_ulogic_vector( 95 downto 0);
370  signal ssUSIF_UARS_Meta_tvalid : std_ulogic;
371  signal ssUSIF_UARS_Meta_tready : std_ulogic;
372  --
373  signal ssUSIF_UARS_DLen_tdata : std_ulogic_vector( 15 downto 0);
374  signal ssUSIF_UARS_DLen_tvalid : std_ulogic;
375  signal ssUSIF_UARS_DLen_tready : std_ulogic;
376  -- -------------------------------------------
377  signal ssUARS_UAF_Data_tdata : std_ulogic_vector( 63 downto 0);
378  signal ssUARS_UAF_Data_tkeep : std_ulogic_vector( 7 downto 0);
379  signal ssUARS_UAF_Data_tlast : std_ulogic;
380  signal ssUARS_UAF_Data_tvalid : std_ulogic;
381  signal ssUARS_UAF_Data_tready : std_ulogic;
382  --
383  signal ssUARS_UAF_Meta_tdata : std_ulogic_vector( 95 downto 0);
384  signal ssUARS_UAF_Meta_tvalid : std_ulogic;
385  signal ssUARS_UAF_Meta_tready : std_ulogic;
386  --
387  signal ssUARS_UAF_DLen_tdata : std_ulogic_vector( 15 downto 0);
388  signal ssUARS_UAF_DLen_tvalid : std_ulogic;
389  signal ssUARS_UAF_DLen_tready : std_ulogic;
390  --------------------------------------------------------
391  -- SIGNAL DECLARATIONS : UAF --> UARS --> USIF
392  --------------------------------------------------------
393  signal ssUAF_UARS_Data_tdata : std_ulogic_vector( 63 downto 0);
394  signal ssUAF_UARS_Data_tkeep : std_ulogic_vector( 7 downto 0);
395  signal ssUAF_UARS_Data_tlast : std_ulogic;
396  signal ssUAF_UARS_Data_tvalid : std_ulogic;
397  signal ssUAF_UARS_Data_tready : std_ulogic;
398  --
399  signal ssUAF_UARS_Meta_tdata : std_ulogic_vector( 95 downto 0);
400  signal ssUAF_UARS_Meta_tvalid : std_ulogic;
401  signal ssUAF_UARS_Meta_tready : std_ulogic;
402  --
403  signal ssUAF_UARS_DLen_tdata : std_ulogic_vector( 15 downto 0);
404  signal ssUAF_UARS_DLen_tvalid : std_ulogic;
405  signal ssUAF_UARS_DLen_tready : std_ulogic;
406  -- -------------------------------------------
407  signal ssUARS_USIF_Data_tdata : std_ulogic_vector( 63 downto 0);
408  signal ssUARS_USIF_Data_tkeep : std_ulogic_vector( 7 downto 0);
409  signal ssUARS_USIF_Data_tlast : std_ulogic;
410  signal ssUARS_USIF_Data_tvalid : std_ulogic;
411  signal ssUARS_USIF_Data_tready : std_ulogic;
412  --
413  signal ssUARS_USIF_Meta_tdata : std_ulogic_vector( 95 downto 0);
414  signal ssUARS_USIF_Meta_tvalid : std_ulogic;
415  signal ssUARS_USIF_Meta_tready : std_ulogic;
416  --
417  signal ssUARS_USIF_DLen_tdata : std_ulogic_vector( 15 downto 0);
418  signal ssUARS_USIF_DLen_tvalid : std_ulogic;
419  signal ssUARS_USIF_DLen_tready : std_ulogic;
420 
421  --------------------------------------------------------
422  -- SIGNAL DECLARATIONS : USIF <--> UAF (Axis-based)
423  --------------------------------------------------------
424  -- USIF-> UAF / UDP Rx Data Interfaces
425  signal ssUSIF_UAF_Data_tdata : std_logic_vector(63 downto 0);
426  signal ssUSIF_UAF_Data_tkeep : std_logic_vector( 7 downto 0);
427  signal ssUSIF_UAF_Data_tlast : std_logic;
428  signal ssUSIF_UAF_Data_tvalid : std_logic;
429  signal ssUSIF_UAF_Data_tready : std_logic;
430  --
431  signal ssUSIF_UAF_Meta_tdata : std_logic_vector(95 downto 0);
432  signal ssUSIF_UAF_Meta_tvalid : std_logic;
433  signal ssUSIF_UAF_Meta_tready : std_logic;
434  --
435  signal ssUSIF_UAF_DLen_tdata : std_logic_vector(15 downto 0);
436  signal ssUSIF_UAF_DLen_tvalid : std_logic;
437  signal ssUSIF_UAF_DLen_tready : std_logic;
438 
439  -- UAF->USIF / UDP Tx Data Interfaces
440  signal ssUAF_USIF_Data_tdata : std_logic_vector(63 downto 0);
441  signal ssUAF_USIF_Data_tkeep : std_logic_vector( 7 downto 0);
442  signal ssUAF_USIF_Data_tlast : std_logic;
443  signal ssUAF_USIF_Data_tvalid : std_logic;
444  signal ssUAF_USIF_Data_tready : std_logic;
445  --
446  signal ssUAF_USIF_Meta_tdata : std_logic_vector(95 downto 0);
447  signal ssUAF_USIF_Meta_tvalid : std_logic;
448  signal ssUAF_USIF_Meta_tready : std_logic;
449  --
450  signal ssUAF_USIF_DLen_tdata : std_logic_vector(15 downto 0);
451  signal ssUAF_USIF_DLen_tvalid : std_logic;
452  signal ssUAF_USIF_DLen_tready : std_logic;
453 
454  --------------------------------------------------------
455  -- SIGNAL DECLARATIONS : USIF <--> FIFO <--> UAF
456  --------------------------------------------------------
457  -- USIF -> FIFO_Write / UDP Rx Data Interfaces
458  signal ssUSIF_FIFO_Udp_Data_data : std_logic_vector(72 downto 0);
459  signal ssUSIF_FIFO_Udp_Data_write : std_logic;
460  signal ssUSIF_FIFO_Udp_Data_full : std_logic;
461  --
462  signal ssUSIF_FIFO_Udp_Meta_data : std_logic_vector(95 downto 0);
463  signal ssUSIF_FIFO_Udp_Meta_write : std_logic;
464  signal ssUSIF_FIFO_Udp_Meta_full : std_logic;
465  -- FIFO_Read -> UAF / UDP Rx Data Interfaces
466  signal ssFIFO_UAF_Udp_Data_data : std_logic_vector(72 downto 0);
467  signal ssFIFO_UAF_Udp_Data_read : std_logic;
468  signal ssFIFO_UAF_Udp_Data_empty : std_logic;
469  --
470  signal ssFIFO_UAF_Udp_Meta_data : std_logic_vector(95 downto 0);
471  signal ssFIFO_UAF_Udp_Meta_read : std_logic;
472  signal ssFIFO_UAF_Udp_Meta_empty : std_logic;
473 
474  -- UAF -> FIFO_write / UDP Tx Data Interfaces
475  signal ssUAF_FIFO_Udp_Data_data : std_logic_vector(72 downto 0);
476  signal ssUAF_FIFO_Udp_Data_write : std_logic;
477  signal ssUAF_FIFO_Udp_Data_full : std_logic;
478  --
479  signal ssUAF_FIFO_Udp_Meta_data : std_logic_vector(95 downto 0);
480  signal ssUAF_FIFO_Udp_Meta_write : std_logic;
481  signal ssUAF_FIFO_Udp_Meta_full : std_logic;
482  --
483  signal ssUAF_FIFO_Udp_DLen_data : std_logic_vector(15 downto 0);
484  signal ssUAF_FIFO_Udp_DLen_write : std_logic;
485  signal ssUAF_FIFO_Udp_DLen_full : std_logic;
486  -- FIFO_Read -> USIF / UDP Tx Data Interfaces
487  signal ssFIFO_USIF_Udp_Data_data : std_logic_vector(72 downto 0);
488  signal ssFIFO_USIF_Udp_Data_read : std_logic;
489  signal ssFIFO_USIF_Udp_Data_empty : std_logic;
490  --
491  signal ssFIFO_USIF_Udp_Meta_data : std_logic_vector(95 downto 0);
492  signal ssFIFO_USIF_Udp_Meta_read : std_logic;
493  signal ssFIFO_USIF_Udp_Meta_empty : std_logic;
494  --
495  signal ssFIFO_USIF_Udp_DLen_data : std_logic_vector(15 downto 0);
496  signal ssFIFO_USIF_Udp_DLen_read : std_logic;
497  signal ssFIFO_USIF_Udp_DLen_empty : std_logic;
498 
499  signal sSHL_Mem_Mp0_Write_tlast : std_ulogic_vector(0 downto 0);
500 
501  --------------------------------------------------------
502  -- DEBUG SIGNALS
503  --------------------------------------------------------
504  attribute mark_debug : string;
505  --
506  signal sTSIF_DBG_SinkCnt : std_logic_vector(31 downto 0);
507  attribute mark_debug of sTSIF_DBG_SinkCnt: signal is "true"; -- Set to "true' if you need/want to trace these signals
508  --
509  signal sTSIF_DBG_InpBufSpace : std_logic_vector(15 downto 0);
510  attribute mark_debug of sTSIF_DBG_InpBufSpace : signal is "true"; -- Set to "true' if you need/want to trace these signals
511 
512  --============================================================================
513  -- VARIABLE DECLARATIONS
514  --============================================================================
515 
516  --===========================================================================
517  --== COMPONENT DECLARATIONS
518  --===========================================================================
519  component UdpApplicationFlash_Deprecated is
520  port (
521  ------------------------------------------------------
522  -- From SHELL / Clock, Reset
523  ------------------------------------------------------
524  aclk : in std_logic;
525  aresetn : in std_logic;
526  --------------------------------------------------------
527  -- From SHELL / Mmio Interfaces
528  --------------------------------------------------------
529  piSHL_Mmio_En_V : in std_logic_vector( 0 downto 0);
530  --[NOT_USED] piSHL_Mmio_EchoCtrl_V : in std_logic_vector( 1 downto 0);
531  --[NOT_USED] piSHL_MmioPostDgmEn_V : in std_logic;
532  --[NOT_USED] piSHL_MmioCaptDgmEn_V : in std_logic;
533  --------------------------------------------------------
534  -- From USIF / UDP Rx Data Interfaces
535  --------------------------------------------------------
536  siUSIF_Data_tdata : in std_logic_vector( 63 downto 0);
537  siUSIF_Data_tkeep : in std_logic_vector( 7 downto 0);
538  siUSIF_Data_tlast : in std_logic;
539  siUSIF_Data_tvalid : in std_logic;
540  siUSIF_Data_tready : out std_logic;
541  --
542  siUSIF_Meta_tdata : in std_logic_vector(95 downto 0);
543  siUSIF_Meta_tvalid : in std_logic;
544  siUSIF_Meta_tready : out std_logic;
545  --
546  siUSIF_DLen_tdata : in std_logic_vector(15 downto 0);
547  siUSIF_DLen_tvalid : in std_logic;
548  siUSIF_DLen_tready : out std_logic;
549  --------------------------------------------------------
550  -- To USIF / UDP Tx Data Interfaces
551  --------------------------------------------------------
552  soUSIF_Data_tdata : out std_logic_vector( 63 downto 0);
553  soUSIF_Data_tkeep : out std_logic_vector( 7 downto 0);
554  soUSIF_Data_tlast : out std_logic;
555  soUSIF_Data_tvalid : out std_logic;
556  soUSIF_Data_tready : in std_logic;
557  --
558  soUSIF_Meta_tdata : out std_logic_vector(95 downto 0);
559  soUSIF_Meta_tvalid : out std_logic;
560  soUSIF_Meta_tready : in std_logic;
561  --
562  soUSIF_DLen_tdata : out std_logic_vector(15 downto 0);
563  soUSIF_DLen_tvalid : out std_logic;
564  soUSIF_DLen_tready : in std_logic
565  );
566  end component UdpApplicationFlash_Deprecated;
567 
568  component UdpApplicationFlash_ApFifo is
569  port (
570  ------------------------------------------------------
571  -- From SHELL / Clock and Reset
572  ------------------------------------------------------
573  ap_clk : in std_logic;
574  ap_rst : in std_logic;
575  --------------------------------------------------------
576  -- From SHELL / Mmio Interfaces
577  --------------------------------------------------------
578  piSHL_Mmio_En_V : in std_logic_vector( 0 downto 0);
579  --[NOT_USED] piSHL_Mmio_EchoCtrl_V : in std_logic_vector( 1 downto 0);
580  --[NOT_USED] piSHL_Mmio_PostDgmEn_V : in std_logic;
581  --[NOT_USED] piSHL_Mmio_CaptDgmEn_V : in std_logic;
582  --------------------------------------------------------
583  -- From USIF / UDP Rx Data Interfaces
584  --------------------------------------------------------
585  siUSIF_Data_V_dout : in std_logic_vector( 72 downto 0); -- 64+8+1
586  siUSIF_Data_V_empty_n : in std_logic;
587  siUSIF_Data_V_read : out std_logic;
588  --
589  siUSIF_Meta_V_dout : in std_logic_vector(95 DOWNTO 0);
590  siUSIF_Meta_V_empty_n : in std_logic;
591  siUSIF_Meta_V_read : out std_logic;
592  --
593  siUSIF_DLen_V_V_dout : in std_logic_vector(15 DOWNTO 0);
594  siUSIF_DLen_V_V_empty_n : in std_logic;
595  siUSIF_DLen_V_V_read : out std_logic;
596  --------------------------------------------------------
597  -- To USIF / UDP Tx Data Interfaces
598  --------------------------------------------------------
599  soUSIF_Data_V_din : out std_logic_vector( 72 downto 0);
600  soUSIF_Data_V_write : out std_logic;
601  soUSIF_Data_V_full_n : in std_logic;
602  --
603  soUSIF_Meta_V_din : out std_logic_vector(95 DOWNTO 0);
604  soUSIF_Meta_V_write : out std_logic;
605  soUSIF_Meta_V_full_n : in std_logic;
606  --
607  soUSIF_DLen_V_V_din : out std_logic_vector( 15 downto 0);
608  soUSIF_DLen_V_V_write : out std_logic;
609  soUSIF_DLen_V_V_full_n : in std_logic
610  );
611  end component UdpApplicationFlash_ApFifo;
612 
613  component UdpApplicationFlash is
614  port (
615  ------------------------------------------------------
616  -- From SHELL / Clock and Reset
617  ------------------------------------------------------
618  ap_clk : in std_logic;
619  ap_rst_n : in std_logic;
620  --------------------------------------------------------
621  -- From SHELL / Mmio Interfaces
622  --------------------------------------------------------
623  piSHL_Mmio_En_V : in std_logic_vector( 0 downto 0);
624  --[NOT_USED] piSHL_Mmio_EchoCtrl_V : in std_logic_vector( 1 downto 0);
625  --[NOT_USED] piSHL_Mmio_PostDgmEn_V : in std_logic;
626  --[NOT_USED] piSHL_Mmio_CaptDgmEn_V : in std_logic;
627  --------------------------------------------------------
628  -- From USIF / UDP Rx Data Interfaces
629  --------------------------------------------------------
630  siUSIF_Data_tdata : in std_logic_vector( 63 downto 0);
631  siUSIF_Data_tkeep : in std_logic_vector( 7 downto 0);
632  siUSIF_Data_tlast : in std_logic;
633  siUSIF_Data_tvalid : in std_logic;
634  siUSIF_Data_tready : out std_logic;
635  --
636  siUSIF_Meta_V_tdata : in std_logic_vector(95 downto 0);
637  siUSIF_Meta_V_tvalid : in std_logic;
638  siUSIF_Meta_V_tready : out std_logic;
639  --
640  siUSIF_DLen_V_V_tdata : in std_logic_vector(15 downto 0);
641  siUSIF_DLen_V_V_tvalid : in std_logic;
642  siUSIF_DLen_V_V_tready : out std_logic;
643  --------------------------------------------------------
644  -- To USIF / UDP Tx Data Interfaces
645  --------------------------------------------------------
646  soUSIF_Data_tdata : out std_logic_vector( 63 downto 0);
647  soUSIF_Data_tkeep : out std_logic_vector( 7 downto 0);
648  soUSIF_Data_tlast : out std_logic;
649  soUSIF_Data_tvalid : out std_logic;
650  soUSIF_Data_tready : in std_logic;
651  --
652  soUSIF_Meta_V_tdata : out std_logic_vector(95 downto 0);
653  soUSIF_Meta_V_tvalid : out std_logic;
654  soUSIF_Meta_V_tready : in std_logic;
655  --
656  soUSIF_DLen_V_V_tdata : out std_logic_vector(15 downto 0);
657  soUSIF_DLen_V_V_tvalid : out std_logic;
658  soUSIF_DLen_V_V_tready : in std_logic
659  );
660  end component UdpApplicationFlash;
661 
662  component UdpShellInterface_Deprecated is
663  port (
664  ------------------------------------------------------
665  -- From SHELL / Clock and Reset
666  ------------------------------------------------------
667  aclk : in std_logic;
668  aresetn : in std_logic;
669  --------------------------------------------------------
670  -- SHELL / Mmio Interface
671  --------------------------------------------------------
672  piSHL_Mmio_En_V : in std_logic_vector( 0 downto 0);
673  --------------------------------------------------------
674  -- SHELL / UDP Control Port Interfaces
675  --------------------------------------------------------
676  soSHL_LsnReq_tdata : out std_logic_vector(15 downto 0);
677  soSHL_LsnReq_tvalid : out std_logic;
678  soSHL_LsnReq_TREADY : in std_logic;
679  --
680  siSHL_LsnRep_tdata : in std_logic_vector( 7 downto 0);
681  siSHL_LsnRep_tvalid : in std_logic;
682  siSHL_LsnRep_tready : out std_logic;
683  --
684  soSHL_ClsReq_tdata : out std_logic_vector(15 downto 0);
685  soSHL_ClsReq_tvalid : out std_logic;
686  soSHL_ClsReq_TREADY : in std_logic;
687  --
688  siSHL_ClsRep_tdata : in std_logic_vector( 7 downto 0);
689  siSHL_ClsRep_tvalid : in std_logic;
690  siSHL_ClsRep_tready : out std_logic;
691  --------------------------------------------------------
692  -- SHELL / Rx Data Interfaces
693  --------------------------------------------------------
694  siSHL_Data_tdata : in std_logic_vector(63 downto 0);
695  siSHL_Data_tkeep : in std_logic_vector( 7 downto 0);
696  siSHL_Data_tlast : in std_logic;
697  siSHL_Data_tvalid : in std_logic;
698  siSHL_Data_tready : out std_logic;
699  --
700  siSHL_Meta_tdata : in std_logic_vector(95 downto 0);
701  siSHL_Meta_tvalid : in std_logic;
702  siSHL_Meta_tready : out std_logic;
703  --
704  siSHL_DLen_tdata : in std_logic_vector(15 downto 0);
705  siSHL_DLen_tvalid : in std_logic;
706  siSHL_DLen_tready : out std_logic;
707  --------------------------------------------------------
708  -- SHELL / UDP Tx Data Interfaces
709  --------------------------------------------------------
710  soSHL_Data_tdata : out std_logic_vector(63 downto 0);
711  soSHL_Data_tkeep : out std_logic_vector( 7 downto 0);
712  soSHL_Data_tlast : out std_logic;
713  soSHL_Data_tvalid : out std_logic;
714  soSHL_Data_tready : in std_logic;
715  --
716  soSHL_Meta_tdata : out std_logic_vector(95 downto 0);
717  soSHL_Meta_tvalid : out std_logic;
718  soSHL_Meta_tready : in std_logic;
719  --
720  soSHL_DLen_tdata : out std_logic_vector(15 downto 0);
721  soSHL_DLen_tvalid : out std_logic;
722  soSHL_DLen_tready : in std_logic;
723  --------------------------------------------------------
724  -- UAF / UDP Tx Data Interfaces
725  --------------------------------------------------------
726  siUAF_Data_tdata : in std_logic_vector(63 downto 0);
727  siUAF_Data_tkeep : in std_logic_vector( 7 downto 0);
728  siUAF_Data_tlast : in std_logic;
729  siUAF_Data_tvalid : in std_logic;
730  siUAF_Data_tready : out std_logic;
731  --
732  siUAF_Meta_tdata : in std_logic_vector(95 downto 0);
733  siUAF_Meta_tvalid : in std_logic;
734  siUAF_Meta_tready : out std_logic;
735  --
736  siUAF_DLen_tdata : in std_logic_vector(15 downto 0);
737  siUAF_DLen_tvalid : in std_logic;
738  siUAF_DLen_tready : out std_logic;
739  --------------------------------------------------------
740  -- UAF / Rx Data Interfaces
741  --------------------------------------------------------
742  soUAF_Data_tdata : out std_logic_vector(63 downto 0);
743  soUAF_Data_tkeep : out std_logic_vector( 7 downto 0);
744  soUAF_Data_tlast : out std_logic;
745  soUAF_Data_tvalid : out std_logic;
746  soUAF_Data_tready : in std_logic;
747  --
748  soUAF_Meta_tdata : out std_logic_vector(95 downto 0);
749  soUAF_Meta_tvalid : out std_logic;
750  soUAF_Meta_tready : in std_logic;
751  --
752  soUAF_DLen_tdata : out std_logic_vector(15 downto 0);
753  soUAF_DLen_tvalid : out std_logic;
754  soUAF_DLen_tready : in std_logic
755  );
756  end component UdpShellInterface_Deprecated;
757 
758  component UdpShellInterface_ApFifo is
759  port (
760  ------------------------------------------------------
761  -- From SHELL / Clock and Reset
762  ------------------------------------------------------
763  ap_clk : in std_logic;
764  ap_rst_n : in std_logic;
765  --------------------------------------------------------
766  -- SHELL / Mmio Interface
767  --------------------------------------------------------
768  piSHL_Mmio_En_V : in std_logic;
769  --------------------------------------------------------
770  -- SHELL / UDP Control Port Interfaces
771  --------------------------------------------------------
772  soSHL_LsnReq_V_V_tdata : out std_logic_vector(15 downto 0);
773  soSHL_LsnReq_V_V_tvalid : out std_logic;
774  soSHL_LsnReq_V_V_tready : in std_logic;
775  --
776  siSHL_LsnRep_V_tdata : in std_logic_vector( 7 downto 0);
777  siSHL_LsnRep_V_tvalid : in std_logic;
778  siSHL_LsnRep_V_tready : out std_logic;
779  --
780  soSHL_ClsReq_V_V_tdata : out std_logic_vector(15 downto 0);
781  soSHL_ClsReq_V_V_tvalid : out std_logic;
782  soSHL_ClsReq_V_V_tready : in std_logic;
783  --
784  siSHL_ClsRep_V_tdata : in std_logic_vector( 7 downto 0);
785  siSHL_ClsRep_V_tvalid : in std_logic;
786  siSHL_ClsRep_V_tready : out std_logic;
787  --------------------------------------------------------
788  -- SHELL / Rx Data Interfaces
789  --------------------------------------------------------
790  siSHL_Data_tdata : in std_logic_vector(63 downto 0);
791  siSHL_Data_tkeep : in std_logic_vector( 7 downto 0);
792  siSHL_Data_tlast : in std_logic;
793  siSHL_Data_tvalid : in std_logic;
794  siSHL_Data_tready : out std_logic;
795  --
796  siSHL_Meta_V_tdata : in std_logic_vector(95 downto 0);
797  siSHL_Meta_V_tvalid : in std_logic;
798  siSHL_Meta_V_tready : out std_logic;
799  --
800  siSHL_DLen_V_V_tdata : in std_logic_vector(15 downto 0);
801  siSHL_DLen_V_V_tvalid : in std_logic;
802  siSHL_DLen_V_V_tready : out std_logic;
803  --------------------------------------------------------
804  -- SHELL / UDP Tx Data Interfaces
805  --------------------------------------------------------
806  soSHL_Data_tdata : out std_logic_vector(63 downto 0);
807  soSHL_Data_tkeep : out std_logic_vector( 7 downto 0);
808  soSHL_Data_tlast : out std_logic;
809  soSHL_Data_tvalid : out std_logic;
810  soSHL_Data_tready : in std_logic;
811  --
812  soSHL_Meta_V_tdata : out std_logic_vector(95 downto 0);
813  soSHL_Meta_V_tvalid : out std_logic;
814  soSHL_Meta_V_tready : in std_logic;
815  --
816  soSHL_DLen_V_V_tdata : out std_logic_vector(15 downto 0);
817  soSHL_DLen_V_V_tvalid : out std_logic;
818  soSHL_DLen_V_V_tready : in std_logic;
819  --------------------------------------------------------
820  -- UAF / UDP Tx Data Interfaces
821  --------------------------------------------------------
822  siUAF_Data_V_dout : in std_logic_vector(72 downto 0);
823  siUAF_Data_V_empty_n : in std_logic;
824  siUAF_Data_V_read : out std_logic;
825  --
826  siUAF_Meta_V_dout : in std_logic_vector(95 downto 0);
827  siUAF_Meta_V_empty_n : in std_logic;
828  siUAF_Meta_V_read : out std_logic;
829  --
830  siUAF_DLen_V_V_dout : in std_logic_vector(15 downto 0);
831  siUAF_DLen_V_V_empty_n : in std_logic;
832  siUAF_DLen_V_V_read : out std_logic;
833  --------------------------------------------------------
834  -- UAF / Rx Data Interfaces
835  --------------------------------------------------------
836  soUAF_Data_V_din : out std_logic_vector(72 downto 0);
837  soUAF_Data_V_write : out std_logic;
838  soUAF_Data_V_full_n : in std_logic;
839  --
840  soUAF_Meta_V_din : out std_logic_vector(95 downto 0);
841  soUAF_Meta_V_write : out std_logic;
842  soUAF_Meta_V_full_n : in std_logic;
843  --
844  soUAF_DLen_V_din : out std_logic_vector(15 downto 0);
845  soUAF_DLen_V_write : out std_logic;
846  soUAF_DLen_V_full_n : in std_logic
847  );
848 
849  end component UdpShellInterface_ApFifo;
850 
851  component UdpShellInterface is
852  port (
853  ------------------------------------------------------
854  -- From SHELL / Clock and Reset
855  ------------------------------------------------------
856  ap_clk : in std_logic;
857  ap_rst_n : in std_logic;
858  --------------------------------------------------------
859  -- SHELL / Mmio Interface
860  --------------------------------------------------------
861  piSHL_Mmio_En_V : in std_logic;
862  --------------------------------------------------------
863  -- SHELL / UDP Control Port Interfaces
864  --------------------------------------------------------
865  soSHL_LsnReq_V_V_tdata : out std_logic_vector(15 downto 0);
866  soSHL_LsnReq_V_V_tvalid : out std_logic;
867  soSHL_LsnReq_V_V_tready : in std_logic;
868  --
869  siSHL_LsnRep_V_tdata : in std_logic_vector( 7 downto 0);
870  siSHL_LsnRep_V_tvalid : in std_logic;
871  siSHL_LsnRep_V_tready : out std_logic;
872  --
873  soSHL_ClsReq_V_V_tdata : out std_logic_vector(15 downto 0);
874  soSHL_ClsReq_V_V_tvalid : out std_logic;
875  soSHL_ClsReq_V_V_tready : in std_logic;
876  --
877  siSHL_ClsRep_V_tdata : in std_logic_vector( 7 downto 0);
878  siSHL_ClsRep_V_tvalid : in std_logic;
879  siSHL_ClsRep_V_tready : out std_logic;
880  --------------------------------------------------------
881  -- SHELL / Rx Data Interfaces
882  --------------------------------------------------------
883  siSHL_Data_tdata : in std_logic_vector(63 downto 0);
884  siSHL_Data_tkeep : in std_logic_vector( 7 downto 0);
885  siSHL_Data_tlast : in std_logic;
886  siSHL_Data_tvalid : in std_logic;
887  siSHL_Data_tready : out std_logic;
888  --
889  siSHL_Meta_V_tdata : in std_logic_vector(95 downto 0);
890  siSHL_Meta_V_tvalid : in std_logic;
891  siSHL_Meta_V_tready : out std_logic;
892  --
893  siSHL_DLen_V_V_tdata : in std_logic_vector(15 downto 0);
894  siSHL_DLen_V_V_tvalid : in std_logic;
895  siSHL_DLen_V_V_tready : out std_logic;
896  --------------------------------------------------------
897  -- SHELL / UDP Tx Data Interfaces
898  --------------------------------------------------------
899  soSHL_Data_tdata : out std_logic_vector(63 downto 0);
900  soSHL_Data_tkeep : out std_logic_vector( 7 downto 0);
901  soSHL_Data_tlast : out std_logic;
902  soSHL_Data_tvalid : out std_logic;
903  soSHL_Data_tready : in std_logic;
904  --
905  soSHL_Meta_V_tdata : out std_logic_vector(95 downto 0);
906  soSHL_Meta_V_tvalid : out std_logic;
907  soSHL_Meta_V_tready : in std_logic;
908  --
909  soSHL_DLen_V_V_tdata : out std_logic_vector(15 downto 0);
910  soSHL_DLen_V_V_tvalid : out std_logic;
911  soSHL_DLen_V_V_tready : in std_logic;
912  --------------------------------------------------------
913  -- UAF / UDP Tx Data Interfaces
914  --------------------------------------------------------
915  siUAF_Data_tdata : in std_logic_vector(63 downto 0);
916  siUAF_Data_tkeep : in std_logic_vector( 7 downto 0);
917  siUAF_Data_tlast : in std_logic;
918  siUAF_Data_tvalid : in std_logic;
919  siUAF_Data_tready : out std_logic;
920  --
921  siUAF_Meta_V_tdata : in std_logic_vector(95 downto 0);
922  siUAF_Meta_V_tvalid : in std_logic;
923  siUAF_Meta_V_tready : out std_logic;
924  --
925  siUAF_DLen_V_V_tdata : in std_logic_vector(15 downto 0);
926  siUAF_DLen_V_V_tvalid : in std_logic;
927  siUAF_DLen_V_V_tready : out std_logic;
928  --------------------------------------------------------
929  -- UAF / Rx Data Interfaces
930  --------------------------------------------------------
931  soUAF_Data_tdata : out std_logic_vector(63 downto 0);
932  soUAF_Data_tkeep : out std_logic_vector( 7 downto 0);
933  soUAF_Data_tlast : out std_logic;
934  soUAF_Data_tvalid : out std_logic;
935  soUAF_Data_tready : in std_logic;
936  --
937  soUAF_Meta_V_tdata : out std_logic_vector(95 downto 0);
938  soUAF_Meta_V_tvalid : out std_logic;
939  soUAF_Meta_V_tready : in std_logic;
940  --
941  soUAF_DLen_V_V_tdata : out std_logic_vector(15 downto 0);
942  soUAF_DLen_V_V_tvalid : out std_logic;
943  soUAF_DLen_V_V_tready : in std_logic
944  );
945  end component UdpShellInterface;
946 
947  component TcpApplicationFlash_Deprecated is
948  port (
949  ------------------------------------------------------
950  -- From SHELL / Clock and Reset
951  ------------------------------------------------------
952  aclk : in std_logic;
953  aresetn : in std_logic;
954  ------------------------------------------------------
955  -- From SHELL / Mmio Interfaces
956  ------------------------------------------------------
957  --[NOT_USED] piSHL_MmioEchoCtrl_V : in std_logic_vector( 1 downto 0);
958  --[NOT_USED] piSHL_MmioPostSegEn_V : in std_logic;
959  --[NOT_USED] piSHL_MmioCaptSegEn_V : in std_logic;
960  --------------------------------------------------------
961  -- From SHELL / Tcp Data Interfaces
962  --------------------------------------------------------
963  siTSIF_Data_tdata : in std_logic_vector( 63 downto 0);
964  siTSIF_Data_tkeep : in std_logic_vector( 7 downto 0);
965  siTSIF_Data_tlast : in std_logic;
966  siTSIF_Data_tvalid : in std_logic;
967  siTSIF_Data_tready : out std_logic;
968  --
969  siTSIF_SessId_tdata : in std_logic_vector( 15 downto 0);
970  siTSIF_SessId_tvalid : in std_logic;
971  siTSIF_SessId_tready : out std_logic;
972  --
973  siTSIF_DatLen_tdata : in std_logic_vector( 15 downto 0);
974  siTSIF_DatLen_tvalid : in std_logic;
975  siTSIF_DatLen_tready : out std_logic;
976  --------------------------------------------------------
977  -- To SHELL / Tcp Data Interfaces
978  --------------------------------------------------------
979  soTSIF_Data_tdata : out std_logic_vector( 63 downto 0);
980  soTSIF_Data_tkeep : out std_logic_vector( 7 downto 0);
981  soTSIF_Data_tlast : out std_logic;
982  soTSIF_Data_tvalid : out std_logic;
983  soTSIF_Data_tready : in std_logic;
984  --
985  soTSIF_SessId_tdata : out std_logic_vector( 15 downto 0);
986  soTSIF_SessId_tvalid : out std_logic;
987  soTSIF_SessId_tready : in std_logic;
988  --
989  soTSIF_DatLen_tdata : out std_logic_vector( 15 downto 0);
990  soTSIF_DatLen_tvalid : out std_logic;
991  soTSIF_DatLen_tready : in std_logic
992  );
993  end component TcpApplicationFlash_Deprecated;
994 
995  component TcpApplicationFlash is
996  port (
997  ------------------------------------------------------
998  -- From SHELL / Clock and Reset
999  ------------------------------------------------------
1000  ap_clk : in std_logic;
1001  ap_rst_n : in std_logic;
1002  --------------------------------------------------------
1003  -- From SHELL / Mmio Interfaces
1004  --------------------------------------------------------
1005  --[NOT_USED] piSHL_MmioEchoCtrl_V : in std_logic_vector( 1 downto 0);
1006  --[NOT_USED] piSHL_MmioPostSegEn_V : in std_logic;
1007  --[NOT_USED] piSHL_MmioCaptSegEn : in std_logic;
1008  --------------------------------------------------------
1009  -- From SHELL / Tcp Data Interfaces
1010  --------------------------------------------------------
1011  siTSIF_Data_tdata : in std_logic_vector( 63 downto 0);
1012  siTSIF_Data_tkeep : in std_logic_vector( 7 downto 0);
1013  siTSIF_Data_tlast : in std_logic;
1014  siTSIF_Data_tvalid : in std_logic;
1015  siTSIF_Data_tready : out std_logic;
1016  --
1017  siTSIF_SessId_V_V_tdata : in std_logic_vector( 15 downto 0);
1018  siTSIF_SessId_V_V_tvalid : in std_logic;
1019  siTSIF_SessId_V_V_tready : out std_logic;
1020  --
1021  siTSIF_DatLen_V_V_tdata : in std_logic_vector( 15 downto 0);
1022  siTSIF_DatLen_V_V_tvalid : in std_logic;
1023  siTSIF_DatLen_V_V_tready : out std_logic;
1024  --------------------------------------------------------
1025  -- To SHELL / Tcp Data Interfaces
1026  --------------------------------------------------------
1027  soTSIF_Data_tdata : out std_logic_vector( 63 downto 0);
1028  soTSIF_Data_tkeep : out std_logic_vector( 7 downto 0);
1029  soTSIF_Data_tlast : out std_logic;
1030  soTSIF_Data_tvalid : out std_logic;
1031  soTSIF_Data_tready : in std_logic;
1032  --
1033  soTSIF_SessId_V_V_tdata : out std_logic_vector( 15 downto 0);
1034  soTSIF_SessId_V_V_tvalid : out std_logic;
1035  soTSIF_SessId_V_V_tready : in std_logic;
1036  --
1037  soTSIF_DatLen_V_V_tdata : out std_logic_vector( 15 downto 0);
1038  soTSIF_DatLen_V_V_tvalid : out std_logic;
1039  soTSIF_DatLen_V_V_tready : in std_logic
1040  );
1041  end component TcpApplicationFlash;
1042 
1043  component TcpShellInterface_Deprecated is
1044  port (
1045  ------------------------------------------------------
1046  -- SHELL / Clock and Reset
1047  ------------------------------------------------------
1048  aclk : in std_ulogic;
1049  aresetn : in std_ulogic;
1050  --------------------------------------------------------
1051  -- SHELL / Mmio Interfaces
1052  --------------------------------------------------------
1053  piSHL_Mmio_En_V : in std_ulogic;
1054  ------------------------------------------------------
1055  -- TAF / TxP Data Flow Interfaces
1056  ------------------------------------------------------
1057  -- FPGA Transmit Path (APP-->SHELL) ----------
1058  ---- TCP Data Stream
1059  siTAF_Data_tdata : in std_ulogic_vector( 63 downto 0);
1060  siTAF_Data_tkeep : in std_ulogic_vector( 7 downto 0);
1061  siTAF_Data_tlast : in std_ulogic;
1062  siTAF_Data_tvalid : in std_ulogic;
1063  siTAF_Data_tready : out std_ulogic;
1064  ---- TCP Session-Id
1065  siTAF_SessId_tdata : in std_ulogic_vector( 15 downto 0);
1066  siTAF_SessId_tvalid : in std_ulogic;
1067  siTAF_SessId_tready : out std_ulogic;
1068  ---- TCP Data-Length
1069  siTAF_DatLen_tdata : in std_ulogic_vector( 15 downto 0);
1070  siTAF_DatLen_tvalid : in std_ulogic;
1071  siTAF_DatLen_tready : out std_ulogic;
1072  ------------------------------------------------------
1073  -- TAF /RxP Data Flow Interfaces
1074  ------------------------------------------------------
1075  -- FPGA Transmit Path (SHELL-->APP) --------
1076  ---- TCP Data Stream
1077  soTAF_Data_tdata : out std_ulogic_vector( 63 downto 0);
1078  soTAF_Data_tkeep : out std_ulogic_vector( 7 downto 0);
1079  soTAF_Data_tlast : out std_ulogic;
1080  soTAF_Data_tvalid : out std_ulogic;
1081  soTAF_Data_tready : in std_ulogic;
1082  ---- TCP Session-Id
1083  soTAF_SessId_tdata : out std_ulogic_vector( 15 downto 0);
1084  soTAF_SessId_tvalid : out std_ulogic;
1085  soTAF_SessId_tready : in std_ulogic;
1086  ---- TCP Data-Length
1087  soTAF_DatLen_tdata : out std_ulogic_vector( 15 downto 0);
1088  soTAF_DatLen_tvalid : out std_ulogic;
1089  soTAF_DatLen_tready : in std_ulogic;
1090  ------------------------------------------------------
1091  -- SHELL / RxP Data Flow Interfaces
1092  ------------------------------------------------------
1093  ---- TCP Data Notification Stream
1094  siSHL_Notif_tdata : in std_ulogic_vector(7+96 downto 0); -- 8-bits boundary
1095  siSHL_Notif_tvalid : in std_ulogic;
1096  siSHL_Notif_tready : out std_ulogic;
1097  ---- TCP Data Request Stream
1098  soSHL_DReq_tdata : out std_ulogic_vector( 31 downto 0);
1099  soSHL_DReq_tvalid : out std_ulogic;
1100  soSHL_DReq_tready : in std_ulogic;
1101  ---- TCP Data Stream
1102  siSHL_Data_tdata : in std_ulogic_vector( 63 downto 0);
1103  siSHL_Data_tkeep : in std_ulogic_vector( 7 downto 0);
1104  siSHL_Data_tlast : in std_ulogic;
1105  siSHL_Data_tvalid : in std_ulogic;
1106  siSHL_Data_tready : out std_ulogic;
1107  ---- TCP Metadata Stream
1108  siSHL_Meta_tdata : in std_ulogic_vector( 15 downto 0);
1109  siSHL_Meta_tvalid : in std_ulogic;
1110  siSHL_Meta_tready : out std_ulogic;
1111  ------------------------------------------------------
1112  -- SHELL / RxP Ctlr Flow Interfaces
1113  ------------------------------------------------------
1114  -- FPGA Receive Path (SHELL-->APP) -------
1115  ---- TCP Listen Request Stream
1116  soSHL_LsnReq_tdata : out std_ulogic_vector( 15 downto 0);
1117  soSHL_LsnReq_tvalid : out std_ulogic;
1118  soSHL_LsnReq_tready : in std_ulogic;
1119  ---- TCP Listen Status Stream
1120  siSHL_LsnRep_tdata : in std_ulogic_vector( 7 downto 0);
1121  siSHL_LsnRep_tvalid : in std_ulogic;
1122  siSHL_LsnRep_tready : out std_ulogic;
1123  ------------------------------------------------------
1124  -- SHELL / TxP Data Flow Interfaces
1125  ------------------------------------------------------
1126  ---- TCP Data Stream
1127  soSHL_Data_tdata : out std_ulogic_vector( 63 downto 0);
1128  soSHL_Data_tkeep : out std_ulogic_vector( 7 downto 0);
1129  soSHL_Data_tlast : out std_ulogic;
1130  soSHL_Data_tvalid : out std_ulogic;
1131  soSHL_Data_tready : in std_ulogic;
1132  ---- TCP Send Request Stream
1133  soSHL_SndReq_tdata : out std_ulogic_vector( 31 downto 0);
1134  soSHL_SndReq_tvalid : out std_ulogic;
1135  soSHL_SndReq_tready : in std_ulogic;
1136  ---- TCP Send Reply Stream
1137  siSHL_SndRep_tdata : in std_ulogic_vector( 55 downto 0);
1138  siSHL_SndRep_tvalid : in std_ulogic;
1139  siSHL_SndRep_tready : out std_ulogic;
1140  ------------------------------------------------------
1141  -- SHELL / TxP Ctlr Flow Interfaces
1142  ------------------------------------------------------
1143  -- FPGA Transmit Path (APP-->SHELL) ------
1144  ---- TCP Open Session Request Stream
1145  soSHL_OpnReq_tdata : out std_ulogic_vector( 47 downto 0);
1146  soSHL_OpnReq_tvalid : out std_ulogic;
1147  soSHL_OpnReq_tready : in std_ulogic;
1148  ---- TCP Open Session Status Stream
1149  siSHL_OpnRep_tdata : in std_ulogic_vector( 23 downto 0);
1150  siSHL_OpnRep_tvalid : in std_ulogic;
1151  siSHL_OpnRep_tready : out std_ulogic;
1152  ---- TCP Close Request Stream
1153  soSHL_ClsReq_tdata : out std_ulogic_vector( 15 downto 0);
1154  soSHL_ClsReq_tvalid : out std_ulogic;
1155  soSHL_ClsReq_tready : in std_ulogic
1156  );
1157  end component TcpShellInterface_Deprecated;
1158 
1159  component TcpShellInterface is
1160  port (
1161  ------------------------------------------------------
1162  -- From SHELL / Clock and Reset
1163  ------------------------------------------------------
1164  ap_clk : in std_ulogic;
1165  ap_rst_n : in std_ulogic;
1166  --------------------------------------------------------
1167  -- From SHELL / Mmio Interfaces
1168  --------------------------------------------------------
1169  piSHL_Mmio_En_V : in std_ulogic;
1170  ------------------------------------------------------
1171  -- TAF / TxP Data Flow Interfaces
1172  ------------------------------------------------------
1173  -- FPGA Transmit Path (APP-->SHELL) ---------
1174  ---- TCP Data Stream
1175  siTAF_Data_tdata : in std_ulogic_vector( 63 downto 0);
1176  siTAF_Data_tkeep : in std_ulogic_vector( 7 downto 0);
1177  siTAF_Data_tlast : in std_ulogic;
1178  siTAF_Data_tvalid : in std_ulogic;
1179  siTAF_Data_tready : out std_ulogic;
1180  ---- TCP Session-Id
1181  siTAF_SessId_V_V_tdata : in std_ulogic_vector( 15 downto 0);
1182  siTAF_SessId_V_V_tvalid : in std_ulogic;
1183  siTAF_SessId_V_V_tready : out std_ulogic;
1184  ---- TCP Data-Length
1185  siTAF_DatLen_V_V_tdata : in std_ulogic_vector( 15 downto 0);
1186  siTAF_DatLen_V_V_tvalid : in std_ulogic;
1187  siTAF_DatLen_V_V_tready : out std_ulogic;
1188  ------------------------------------------------------
1189  -- TAF / RxP Data Flow Interfaces
1190  ------------------------------------------------------
1191  -- FPGA Transmit Path (SHELL-->APP) --------
1192  ---- TCP Data Stream
1193  soTAF_Data_tdata : out std_ulogic_vector( 63 downto 0);
1194  soTAF_Data_tkeep : out std_ulogic_vector( 7 downto 0);
1195  soTAF_Data_tlast : out std_ulogic;
1196  soTAF_Data_tvalid : out std_ulogic;
1197  soTAF_Data_tready : in std_ulogic;
1198  ---- TCP Session-Id
1199  soTAF_SessId_V_V_tdata : out std_ulogic_vector( 15 downto 0);
1200  soTAF_SessId_V_V_tvalid : out std_ulogic;
1201  soTAF_SessId_V_V_tready : in std_ulogic;
1202  ---- TCP Data-Length
1203  soTAF_DatLen_V_V_tdata : out std_ulogic_vector( 15 downto 0);
1204  soTAF_DatLen_V_V_tvalid : out std_ulogic;
1205  soTAF_DatLen_V_V_tready : in std_ulogic;
1206  ------------------------------------------------------
1207  -- SHELL / RxP Data Flow Interfaces
1208  ------------------------------------------------------
1209  ---- TCP Data Notification Stream
1210  siSHL_Notif_V_tdata : in std_ulogic_vector(103 downto 0);
1211  siSHL_Notif_V_tvalid : in std_ulogic;
1212  siSHL_Notif_V_tready : out std_ulogic;
1213  ---- TCP Data Request Stream
1214  soSHL_DReq_V_tdata : out std_ulogic_vector( 31 downto 0);
1215  soSHL_DReq_V_tvalid : out std_ulogic;
1216  soSHL_DReq_V_tready : in std_ulogic;
1217  ---- TCP Data Stream
1218  siSHL_Data_tdata : in std_ulogic_vector( 63 downto 0);
1219  siSHL_Data_tkeep : in std_ulogic_vector( 7 downto 0);
1220  siSHL_Data_tlast : in std_ulogic;
1221  siSHL_Data_tvalid : in std_ulogic;
1222  siSHL_Data_tready : out std_ulogic;
1223  ---- TCP Metadata Stream
1224  siSHL_Meta_V_V_tdata : in std_ulogic_vector( 15 downto 0);
1225  siSHL_Meta_V_V_tvalid : in std_ulogic;
1226  siSHL_Meta_V_V_tready : out std_ulogic;
1227  ------------------------------------------------------
1228  -- SHELL / RxP Ctlr Flow Interfaces
1229  ------------------------------------------------------
1230  -- FPGA Receive Path (SHELL-->APP) -------
1231  ---- TCP Listen Request Stream
1232  soSHL_LsnReq_V_V_tdata : out std_ulogic_vector( 15 downto 0);
1233  soSHL_LsnReq_V_V_tvalid : out std_ulogic;
1234  soSHL_LsnReq_V_V_tready : in std_ulogic;
1235  ---- TCP Listen Status Stream
1236  siSHL_LsnRep_V_tdata : in std_ulogic_vector( 7 downto 0);
1237  siSHL_LsnRep_V_tvalid : in std_ulogic;
1238  siSHL_LsnRep_V_tready : out std_ulogic;
1239  ------------------------------------------------------
1240  -- SHELL / TxP Data Flow Interfaces
1241  ------------------------------------------------------
1242  ---- TCP Data Stream
1243  soSHL_Data_tdata : out std_ulogic_vector( 63 downto 0);
1244  soSHL_Data_tkeep : out std_ulogic_vector( 7 downto 0);
1245  soSHL_Data_tlast : out std_ulogic;
1246  soSHL_Data_tvalid : out std_ulogic;
1247  soSHL_Data_tready : in std_ulogic;
1248  ---- TCP Send Request Stream
1249  soSHL_SndReq_V_tdata : out std_ulogic_vector( 31 downto 0);
1250  soSHL_SndReq_V_tvalid : out std_ulogic;
1251  soSHL_SndReq_V_tready : in std_ulogic;
1252  ---- TCP Send Reply Stream
1253  siSHL_SndRep_V_tdata : in std_ulogic_vector( 55 downto 0);
1254  siSHL_SndRep_V_tvalid : in std_ulogic;
1255  siSHL_SndRep_V_tready : out std_ulogic;
1256  ------------------------------------------------------
1257  -- SHELL / TxP Ctlr Flow Interfaces
1258  ------------------------------------------------------
1259  -- FPGA Transmit Path (APP-->SHELL) ------
1260  ---- TCP Open Session Request Stream
1261  soSHL_OpnReq_V_tdata : out std_ulogic_vector( 47 downto 0);
1262  soSHL_OpnReq_V_tvalid : out std_ulogic;
1263  soSHL_OpnReq_V_tready : in std_ulogic;
1264  ---- TCP Open Session Status Stream
1265  siSHL_OpnRep_V_tdata : in std_ulogic_vector( 23 downto 0);
1266  siSHL_OpnRep_V_tvalid : in std_ulogic;
1267  siSHL_OpnRep_V_tready : out std_ulogic;
1268  ---- TCP Close Request Stream
1269  soSHL_ClsReq_V_V_tdata : out std_ulogic_vector( 15 downto 0);
1270  soSHL_ClsReq_V_V_tvalid : out std_ulogic;
1271  soSHL_ClsReq_V_V_tready : in std_ulogic;
1272  ------------------------------------------------------
1273  -- DEBUG Interfaces
1274  ------------------------------------------------------
1275  ---- Sink Counter Stream
1276  soDBG_SinkCnt_V_V_tdata : out std_ulogic_vector( 31 downto 0);
1277  soDBG_SinkCnt_V_V_tvalid: out std_ulogic;
1278  soDBG_SinkCnt_V_V_tready: in std_ulogic;
1279  ---- Input Buffer Space
1280  soDBG_InpBufSpace_V_V_tdata : out std_ulogic_vector( 15 downto 0);
1281  soDBG_InpBufSpace_V_V_tvalid: out std_ulogic;
1282  soDBG_InpBufSpace_V_V_tready: in std_ulogic
1283  );
1284  end component TcpShellInterface;
1285 
1286  component MemTestFlash is
1287  port (
1288  ------------------------------------------------------
1289  -- From SHELL / Clock and Reset
1290  ------------------------------------------------------
1291  ap_clk : in std_logic;
1292  ap_rst_n : in std_logic;
1293  ------------------------------------------------------
1294  -- BLock-Level I/O Protocol
1295  ------------------------------------------------------
1296  ap_start : in std_logic;
1297  ap_done : out std_logic;
1298  ap_idle : out std_logic;
1299  ap_ready : out std_logic;
1300  ------------------------------------------------------
1301  -- From ROLE / Delayed Reset
1302  ------------------------------------------------------
1303  piSysReset_V : in std_logic_vector( 0 downto 0);
1304  piSysReset_V_ap_vld : in std_logic;
1305  --------------------------------------------------------
1306  -- From SHELL / Mmio Interfaces
1307  --------------------------------------------------------
1308  piMMIO_diag_ctrl_V : in std_logic_vector( 1 downto 0);
1309  piMMIO_diag_ctrl_V_ap_vld : in std_logic;
1310  poMMIO_diag_stat_V : out std_logic_vector( 1 downto 0);
1311  poMMIO_diag_stat_V_ap_vld : out std_logic;
1312  poDebug_V : out std_logic_vector( 15 downto 0);
1313  poDebug_V_ap_vld : out std_logic;
1314  ------------------------------------------------------
1315  -- ROLE / Mem / Mp0 Interface
1316  ------------------------------------------------------
1317  ---- Axi4-Stream Read Command -----
1318  soMemRdCmdP0_TDATA : out std_logic_vector( 79 downto 0);
1319  soMemRdCmdP0_TVALID : out std_logic;
1320  soMemRdCmdP0_TREADY : in std_logic;
1321  ---- Axi4-Stream Read Status ------
1322  siMemRdStsP0_TDATA : in std_logic_vector( 7 downto 0);
1323  siMemRdStsP0_TVALID : in std_logic;
1324  siMemRdStsP0_TREADY : out std_logic;
1325  ---- Axi4-Stream Data Output Channel
1326  siMemReadP0_TDATA : in std_logic_vector(511 downto 0);
1327  siMemReadP0_TKEEP : in std_logic_vector( 63 downto 0);
1328  siMemReadP0_TLAST : in std_logic_vector( 0 downto 0);
1329  siMemReadP0_TVALID : in std_logic;
1330  siMemReadP0_TREADY : out std_logic;
1331  ---- Axi4-Stream Write Command ----
1332  soMemWrCmdP0_TDATA : out std_logic_vector( 79 downto 0);
1333  soMemWrCmdP0_TVALID : out std_logic;
1334  soMemWrCmdP0_TREADY : in std_logic;
1335  ---- Axi4-Stream Write Status -----
1336  siMemWrStsP0_TDATA : in std_logic_vector( 7 downto 0);
1337  siMemWrStsP0_TVALID : in std_logic;
1338  siMemWrStsP0_TREADY : out std_logic;
1339  ---- Axi4-Stream Write Command ----
1340  soMemWriteP0_TDATA : out std_logic_vector(511 downto 0);
1341  soMemWriteP0_TKEEP : out std_logic_vector( 63 downto 0);
1342  soMemWriteP0_TLAST : out std_logic_vector( 0 downto 0);
1343  soMemWriteP0_TVALID : out std_logic;
1344  soMemWriteP0_TREADY : in std_logic
1345  );
1346  end component MemTestFlash;
1347 
1348  component AxisRegisterSlice_64_8_1
1349  port (
1350  aclk : in std_logic;
1351  aresetn : in std_logic;
1352  s_axis_tdata : in std_logic_vector(63 downto 0);
1353  s_axis_tkeep : in std_logic_vector( 7 downto 0);
1354  s_axis_tlast : in std_logic;
1355  s_axis_tvalid : in std_logic;
1356  s_axis_tready : out std_logic;
1357  m_axis_tdata : out std_logic_vector(63 downto 0);
1358  m_axis_tkeep : out std_logic_vector( 7 downto 0);
1359  m_axis_tlast : out std_logic;
1360  m_axis_tvalid : out std_logic;
1361  m_axis_tready : in std_logic
1362  );
1363  end component AxisRegisterSlice_64_8_1;
1364 
1365  component AxisRegisterSlice_32
1366  port (
1367  aclk : in std_logic;
1368  aresetn : in std_logic;
1369  s_axis_tdata : in std_logic_vector(31 downto 0);
1370  s_axis_tvalid : in std_logic;
1371  s_axis_tready : out std_logic;
1372  m_axis_tdata : out std_logic_vector(31 downto 0);
1373  m_axis_tvalid : out std_logic;
1374  m_axis_tready : in std_logic
1375  );
1376  end component AxisRegisterSlice_32;
1377 
1378  component AxisRegisterSlice_16
1379  port (
1380  aclk : in std_logic;
1381  aresetn : in std_logic;
1382  s_axis_tvalid : in std_logic;
1383  s_axis_tready : out std_logic;
1384  s_axis_tdata : in std_logic_vector(15 downto 0);
1385  m_axis_tvalid : out std_logic;
1386  m_axis_tready : in std_logic;
1387  m_axis_tdata : out std_logic_vector(15 downto 0)
1388  );
1389  end component AxisRegisterSlice_16;
1390 
1391  component AxisRegisterSlice_96
1392  port (
1393  aclk : in std_logic;
1394  aresetn : in std_logic;
1395  s_axis_tvalid : in std_logic;
1396  s_axis_tready : out std_logic;
1397  s_axis_tdata : in std_logic_vector(95 downto 0);
1398  m_axis_tvalid : out std_logic;
1399  m_axis_tready : in std_logic;
1400  m_axis_tdata : out std_logic_vector(95 downto 0)
1401  );
1402  end component AxisRegisterSlice_96;
1403 
1404  component Fifo_16x16 is
1405  port (
1406  clk : in std_logic;
1407  srst : in std_logic;
1408  din : in std_logic_vector(15 downto 0);
1409  wr_en : in std_logic;
1410  rd_en : in std_logic;
1411  dout : out std_logic_vector(15 downto 0);
1412  full : out std_logic;
1413  empty : out std_logic;
1414  wr_rst_busy : out std_logic;
1415  rd_rst_busy : out std_logic
1416  );
1417  end component Fifo_16x16;
1418 
1419  component Fifo_16x73 is
1420  port (
1421  clk : in std_logic;
1422  srst : in std_logic;
1423  din : in std_logic_vector(72 downto 0);
1424  wr_en : in std_logic;
1425  rd_en : in std_logic;
1426  dout : out std_logic_vector(72 downto 0);
1427  full : out std_logic;
1428  empty : out std_logic;
1429  wr_rst_busy : out std_logic;
1430  rd_rst_busy : out std_logic
1431  );
1432  end component Fifo_16x73;
1433 
1434  component Fifo_16x96 is
1435  port (
1436  clk : in std_logic;
1437  srst : in std_logic;
1438  din : in std_logic_vector(95 downto 0);
1439  wr_en : in std_logic;
1440  rd_en : in std_logic;
1441  dout : out std_logic_vector(95 downto 0);
1442  full : out std_logic;
1443  empty : out std_logic;
1444  wr_rst_busy : out std_logic;
1445  rd_rst_busy : out std_logic
1446  );
1447  end component Fifo_16x96;
1448 
1449  --===========================================================================
1450  --== FUNCTION DECLARATIONS [TODO-Move to a package]
1451  --===========================================================================
1452  function fVectorize(s: std_ulogic) return std_ulogic_vector is
1453  variable v: std_ulogic_vector(0 downto 0);
1454  begin
1455  v(0) := s;
1456  return v;
1457  end fVectorize;
1458 
1459  function fScalarize(v: in std_ulogic_vector) return std_ulogic is
1460  begin
1461  assert v'length = 1
1462  report "scalarize: output port must be single bit!"
1463  severity FAILURE;
1464  return v(v'LEFT);
1465  end;
1466 
1467 
1468 --################################################################################
1469 --# #
1470 --# ##### #### #### # # #
1471 --# # # # # # # # # #
1472 --# # # # # # # ### #
1473 --# ##### # # # # # #
1474 --# # # # # # # # #
1475 --# # # # # # # # #
1476 --# ##### #### #### # #
1477 --# #
1478 --################################################################################
1479 
1480 begin
1481 
1482  --################################################################################
1483  --# #
1484  --# # # ###### ### ####### #
1485  --# # # # # # #
1486  --# # # # # # #
1487  --# # # ###### # #### #
1488  --# # # # # # #
1489  --# ####### ###### ### # #
1490  --# #
1491  --################################################################################
1492  gUdpShellInterface : if gVivadoVersion = 2016 generate
1493  USIF : UdpShellInterface_Deprecated
1494  port map (
1495  ------------------------------------------------------
1496  -- From SHELL / Clock and Reset
1497  ------------------------------------------------------
1498  aclk => piSHL_156_25Clk,
1499  aresetn => not piSHL_Mmio_Ly7Rst ,
1500  --------------------------------------------------------
1501  -- SHELL / Mmio Interface
1502  --------------------------------------------------------
1503  piSHL_Mmio_En_V(0) => piSHL_Mmio_Ly7En,
1504  --------------------------------------------------------
1505  -- SHELL / UDP Control Port Interfaces
1506  --------------------------------------------------------
1507  soSHL_LsnReq_tdata => soSHL_Nts_Udp_LsnReq_tdata ,
1508  soSHL_LsnReq_tvalid => soSHL_Nts_Udp_LsnReq_tvalid,
1509  soSHL_LsnReq_tready => soSHL_Nts_Udp_LsnReq_tready,
1510  --
1511  siSHL_LsnRep_tdata => siSHL_Nts_Udp_LsnRep_tdata ,
1512  siSHL_LsnRep_tvalid => siSHL_Nts_Udp_LsnRep_tvalid,
1513  siSHL_LsnRep_tready => siSHL_Nts_Udp_LsnRep_tready,
1514  --
1515  soSHL_ClsReq_tdata => soSHL_Nts_Udp_ClsReq_tdata ,
1516  soSHL_ClsReq_tvalid => soSHL_Nts_Udp_ClsReq_tvalid,
1517  soSHL_ClsReq_tready => soSHL_Nts_Udp_ClsReq_tready,
1518  --
1519  siSHL_ClsRep_tdata => siSHL_Nts_Udp_ClsRep_tdata ,
1520  siSHL_ClsRep_tvalid => siSHL_Nts_Udp_ClsRep_tvalid,
1521  siSHL_ClsRep_tready => siSHL_Nts_Udp_ClsRep_tready,
1522  --------------------------------------------------------
1523  -- SHELL / UDP Rx Data Interfaces
1524  --------------------------------------------------------
1525  siSHL_Data_tdata => siSHL_Nts_Udp_Data_tdata,
1526  siSHL_Data_tkeep => siSHL_Nts_Udp_Data_tkeep,
1527  siSHL_Data_tlast => siSHL_Nts_Udp_Data_tlast,
1528  siSHL_Data_tvalid => siSHL_Nts_Udp_Data_tvalid,
1529  siSHL_Data_tready => siSHL_Nts_Udp_Data_tready,
1530  --
1531  siSHL_Meta_tdata => siSHL_Nts_Udp_Meta_tdata,
1532  siSHL_Meta_tvalid => siSHL_Nts_Udp_Meta_tvalid,
1533  siSHL_Meta_tready => siSHL_Nts_Udp_Meta_tready,
1534  --
1535  siSHL_DLen_tdata => siSHL_Nts_Udp_DLen_tdata,
1536  siSHL_DLen_tvalid => siSHL_Nts_Udp_DLen_tvalid,
1537  siSHL_DLen_tready => siSHL_Nts_Udp_DLen_tready,
1538  --------------------------------------------------------
1539  -- SHELL / UDP Tx Data Interfaces
1540  --------------------------------------------------------
1541  soSHL_Data_tdata => soSHL_Nts_Udp_Data_tdata,
1542  soSHL_Data_tkeep => soSHL_Nts_Udp_Data_tkeep,
1543  soSHL_Data_tlast => soSHL_Nts_Udp_Data_tlast,
1544  soSHL_Data_tvalid => soSHL_Nts_Udp_Data_tvalid,
1545  soSHL_Data_tready => soSHL_Nts_Udp_Data_tready,
1546  --
1547  soSHL_Meta_tdata => soSHL_Nts_Udp_Meta_tdata,
1548  soSHL_Meta_tvalid => soSHL_Nts_Udp_Meta_tvalid,
1549  soSHL_Meta_tready => soSHL_Nts_Udp_Meta_tready,
1550  --
1551  soSHL_DLen_tdata => soSHL_Nts_Udp_DLen_tdata,
1552  soSHL_DLen_tvalid => soSHL_Nts_Udp_DLen_tvalid,
1553  soSHL_DLen_tready => soSHL_Nts_Udp_DLen_tready,
1554  --------------------------------------------------------
1555  -- UAF / UDP Tx Data Interfaces
1556  --------------------------------------------------------
1557  siUAF_Data_tdata => ssUAF_USIF_Data_tdata,
1558  siUAF_Data_tkeep => ssUAF_USIF_Data_tkeep,
1559  siUAF_Data_tlast => ssUAF_USIF_Data_tlast,
1560  siUAF_Data_tvalid => ssUAF_USIF_Data_tvalid,
1561  siUAF_Data_tready => ssUAF_USIF_Data_tready,
1562  --
1563  siUAF_Meta_tdata => ssUAF_USIF_Meta_tdata,
1564  siUAF_Meta_tvalid => ssUAF_USIF_Meta_tvalid,
1565  siUAF_Meta_tready => ssUAF_USIF_Meta_tready,
1566  --
1567  siUAF_DLen_tdata => ssUAF_USIF_DLen_tdata,
1568  siUAF_DLen_tvalid => ssUAF_USIF_DLen_tvalid,
1569  siUAF_DLen_tready => ssUAF_USIF_DLen_tready,
1570  --------------------------------------------------------
1571  -- UAF / UDP Rx Data Interfaces
1572  --------------------------------------------------------
1573  soUAF_Data_tdata => ssUSIF_UAF_Data_tdata,
1574  soUAF_Data_tkeep => ssUSIF_UAF_Data_tkeep,
1575  soUAF_Data_tlast => ssUSIF_UAF_Data_tlast,
1576  soUAF_Data_tvalid => ssUSIF_UAF_Data_tvalid,
1577  soUAF_Data_tready => ssUSIF_UAF_Data_tready,
1578  --
1579  soUAF_Meta_tdata => ssUSIF_UAF_Meta_tdata,
1580  soUAF_Meta_tvalid => ssUSIF_UAF_Meta_tvalid,
1581  soUAF_Meta_tready => ssUSIF_UAF_Meta_tready,
1582  --
1583  soUAF_DLen_tdata => ssUSIF_UAF_DLen_tdata,
1584  soUAF_DLen_tvalid => ssUSIF_UAF_DLen_tvalid,
1585  soUAF_DLen_tready => ssUSIF_UAF_DLen_tready
1586  ); -- End-of: UdpShellInterface_Deprecated
1587  else generate
1588  USIF : UdpShellInterface
1589  port map (
1590  ------------------------------------------------------
1591  -- From SHELL / Clock and Reset
1592  ------------------------------------------------------
1593  ap_clk => piSHL_156_25Clk,
1594  ap_rst_n => not piSHL_Mmio_Ly7Rst ,
1595  --------------------------------------------------------
1596  -- SHELL / Mmio Interface
1597  --------------------------------------------------------
1598  piSHL_Mmio_En_V => piSHL_Mmio_Ly7En,
1599  --------------------------------------------------------
1600  -- SHELL / UDP Control Port Interfaces
1601  --------------------------------------------------------
1602  soSHL_LsnReq_V_V_tdata => soSHL_Nts_Udp_LsnReq_tdata ,
1603  soSHL_LsnReq_V_V_tvalid => soSHL_Nts_Udp_LsnReq_tvalid,
1604  soSHL_LsnReq_V_V_tready => soSHL_Nts_Udp_LsnReq_tready,
1605  --
1606  siSHL_LsnRep_V_tdata => siSHL_Nts_Udp_LsnRep_tdata ,
1607  siSHL_LsnRep_V_tvalid => siSHL_Nts_Udp_LsnRep_tvalid,
1608  siSHL_LsnRep_V_tready => siSHL_Nts_Udp_LsnRep_tready,
1609  --
1610  soSHL_ClsReq_V_V_tdata => soSHL_Nts_Udp_ClsReq_tdata ,
1611  soSHL_ClsReq_V_V_tvalid => soSHL_Nts_Udp_ClsReq_tvalid,
1612  soSHL_ClsReq_V_V_tready => soSHL_Nts_Udp_ClsReq_tready,
1613  --
1614  siSHL_ClsRep_V_tdata => siSHL_Nts_Udp_ClsRep_tdata ,
1615  siSHL_ClsRep_V_tvalid => siSHL_Nts_Udp_ClsRep_tvalid,
1616  siSHL_ClsRep_V_tready => siSHL_Nts_Udp_ClsRep_tready,
1617  --------------------------------------------------------
1618  -- SHELL / UDP Rx Data Interfaces
1619  --------------------------------------------------------
1620  siSHL_Data_tdata => siSHL_Nts_Udp_Data_tdata,
1621  siSHL_Data_tkeep => siSHL_Nts_Udp_Data_tkeep,
1622  siSHL_Data_tlast => siSHL_Nts_Udp_Data_tlast,
1623  siSHL_Data_tvalid => siSHL_Nts_Udp_Data_tvalid,
1624  siSHL_Data_tready => siSHL_Nts_Udp_Data_tready,
1625 
1626  siSHL_Meta_V_tdata => siSHL_Nts_Udp_Meta_tdata,
1627  siSHL_Meta_V_tvalid => siSHL_Nts_Udp_Meta_tvalid,
1628  siSHL_Meta_V_tready => siSHL_Nts_Udp_Meta_tready,
1629 
1630  siSHL_DLen_V_V_tdata => siSHL_Nts_Udp_DLen_tdata,
1631  siSHL_DLen_V_V_tvalid => siSHL_Nts_Udp_DLen_tvalid,
1632  siSHL_DLen_V_V_tready => siSHL_Nts_Udp_DLen_tready,
1633  --------------------------------------------------------
1634  -- SHELL / UDP Tx Data Interfaces
1635  --------------------------------------------------------
1636  soSHL_Data_tdata => soSHL_Nts_Udp_Data_tdata,
1637  soSHL_Data_tkeep => soSHL_Nts_Udp_Data_tkeep,
1638  soSHL_Data_tlast => soSHL_Nts_Udp_Data_tlast,
1639  soSHL_Data_tvalid => soSHL_Nts_Udp_Data_tvalid,
1640  soSHL_Data_tready => soSHL_Nts_Udp_Data_tready,
1641  --
1642  soSHL_Meta_V_tdata => soSHL_Nts_Udp_Meta_tdata,
1643  soSHL_Meta_V_tvalid => soSHL_Nts_Udp_Meta_tvalid,
1644  soSHL_Meta_V_tready => soSHL_Nts_Udp_Meta_tready,
1645 
1646  soSHL_DLen_V_V_tdata => soSHL_Nts_Udp_DLen_tdata,
1647  soSHL_DLen_V_V_tvalid => soSHL_Nts_Udp_DLen_tvalid,
1648  soSHL_DLen_V_V_tready => soSHL_Nts_Udp_DLen_tready,
1649  --------------------------------------------------------
1650  -- UAF / UDP Tx Data Interfaces
1651  --------------------------------------------------------
1652  siUAF_Data_tdata => ssUARS_USIF_Data_tdata,
1653  siUAF_Data_tkeep => ssUARS_USIF_Data_tkeep,
1654  siUAF_Data_tlast => ssUARS_USIF_Data_tlast,
1655  siUAF_Data_tvalid => ssUARS_USIF_Data_tvalid,
1656  siUAF_Data_tready => ssUARS_USIF_Data_tready,
1657  --
1658  siUAF_Meta_V_tdata => ssUARS_USIF_Meta_tdata,
1659  siUAF_Meta_V_tvalid => ssUARS_USIF_Meta_tvalid,
1660  siUAF_Meta_V_tready => ssUARS_USIF_Meta_tready,
1661  --
1662  siUAF_DLen_V_V_tdata => ssUARS_USIF_DLen_tdata,
1663  siUAF_DLen_V_V_tvalid => ssUARS_USIF_DLen_tvalid,
1664  siUAF_DLen_V_V_tready => ssUARS_USIF_DLen_tready,
1665  --------------------------------------------------------
1666  -- UAF / UDP Rx Data Interfaces
1667  --------------------------------------------------------
1668  soUAF_Data_tdata => ssUSIF_UARS_Data_tdata,
1669  soUAF_Data_tkeep => ssUSIF_UARS_Data_tkeep,
1670  soUAF_Data_tlast => ssUSIF_UARS_Data_tlast,
1671  soUAF_Data_tvalid => ssUSIF_UARS_Data_tvalid,
1672  soUAF_Data_tready => ssUSIF_UARS_Data_tready,
1673  --
1674  soUAF_Meta_V_tdata => ssUSIF_UARS_Meta_tdata,
1675  soUAF_Meta_V_tvalid => ssUSIF_UARS_Meta_tvalid,
1676  soUAF_Meta_V_tready => ssUSIF_UARS_Meta_tready,
1677  --
1678  soUAF_DLen_V_V_tdata => ssUSIF_UARS_DLen_tdata,
1679  soUAF_DLen_V_V_tvalid => ssUSIF_UARS_DLen_tvalid,
1680  soUAF_DLen_V_V_tready => ssUSIF_UARS_DLen_tready
1681  ); -- End-of: UdpShellInterface
1682  end generate;
1683 
1684  --###############################################################################
1685  --# #
1686  --# # # ##### ###### ##### #
1687  --# # # # # # # # # ##### ##### #
1688  --# # # # # # # # # # # # # #
1689  --# # # # # ###### ####### ##### ##### #
1690  --# # # # # # # # # # #
1691  --# ####### ##### # # # # # #
1692  --# #
1693  --###############################################################################
1694 
1695  --==========================================================================
1696  --== INST: UDP-APPLICATION_FLASH (UAF) for cFp_HelloKale
1697  --== This application implements a set of UDP-oriented tests. The [UAF]
1698  --== connects to the SHELL via a UDP Shell Interface (USIF) block. The
1699  --== main purpose of the [USIF] is to provide a placeholder for the
1700  --== opening of one or multiple listening port(s). The use of the [USIF] is
1701  --== not a prerequisite, but it is provided here for sake of simplicity.
1702  --==========================================================================
1703  gUdpAppFlash : if gVivadoVersion = 2016 generate
1704  UAF : UdpApplicationFlash_Deprecated
1705  port map (
1706  ------------------------------------------------------
1707  -- From SHELL / Clock and Reset
1708  ------------------------------------------------------
1709  aclk => piSHL_156_25Clk,
1710  aresetn => not piSHL_Mmio_Ly7Rst ,
1711  --------------------------------------------------------
1712  -- From SHELL / Mmio Interfaces
1713  --------------------------------------------------------
1714  piSHL_Mmio_En_V(0) => piSHL_Mmio_Ly7En,
1715  --[NOT_USED] piSHL_Mmio_EchoCtrl_V => piSHL_Mmio_UdpEchoCtrl,
1716  --[NOT_USED] piSHL_Mmio_PostDgmEn_V => piSHL_Mmio_UdpPostDgmEn,
1717  --[NOT_USED] piSHL_Mmio_CaptDgmEn_V => piSHL_Mmio_UdpCaptDgmEn,
1718  --------------------------------------------------------
1719  -- From USIF / UDP Rx Data Interfaces
1720  --------------------------------------------------------
1721  siUSIF_Data_tdata => ssUSIF_UAF_Data_tdata,
1722  siUSIF_Data_tkeep => ssUSIF_UAF_Data_tkeep,
1723  siUSIF_Data_tlast => ssUSIF_UAF_Data_tlast,
1724  siUSIF_Data_tvalid => ssUSIF_UAF_Data_tvalid,
1725  siUSIF_Data_tready => ssUSIF_UAF_Data_tready,
1726  --
1727  siUSIF_Meta_tdata => ssUSIF_UAF_Meta_tdata,
1728  siUSIF_Meta_tvalid => ssUSIF_UAF_Meta_tvalid,
1729  siUSIF_Meta_tready => ssUSIF_UAF_Meta_tready,
1730  --
1731  siUSIF_DLen_tdata => ssUSIF_UAF_DLen_tdata,
1732  siUSIF_DLen_tvalid => ssUSIF_UAF_DLen_tvalid,
1733  siUSIF_DLen_tready => ssUSIF_UAF_DLen_tready,
1734  --------------------------------------------------------
1735  -- To USIF / UDP Tx Data Interfaces
1736  --------------------------------------------------------
1737  soUSIF_Data_tdata => ssUAF_USIF_Data_tdata ,
1738  soUSIF_Data_tkeep => ssUAF_USIF_Data_tkeep ,
1739  soUSIF_Data_tlast => ssUAF_USIF_Data_tlast ,
1740  soUSIF_Data_tvalid => ssUAF_USIF_Data_tvalid,
1741  soUSIF_Data_tready => ssUAF_USIF_Data_tready,
1742  --
1743  soUSIF_Meta_tdata => ssUAF_USIF_Meta_tdata ,
1744  soUSIF_Meta_tvalid => ssUAF_USIF_Meta_tvalid,
1745  soUSIF_Meta_tready => ssUAF_USIF_Meta_tready,
1746  --
1747  soUSIF_DLen_tdata => ssUAF_USIF_DLen_tdata ,
1748  soUSIF_DLen_tvalid => ssUAF_USIF_DLen_tvalid,
1749  soUSIF_DLen_tready => ssUAF_USIF_DLen_tready
1750  );
1751  else generate
1752  UAF : UdpApplicationFlash
1753  port map (
1754  ------------------------------------------------------
1755  -- From SHELL / Clock and Reset
1756  ------------------------------------------------------
1757  ap_clk => piSHL_156_25Clk,
1758  ap_rst_n => not piSHL_Mmio_Ly7Rst ,
1759  --------------------------------------------------------
1760  -- From SHELL / Mmio Interfaces
1761  --------------------------------------------------------
1762  piSHL_Mmio_En_V(0) => piSHL_Mmio_Ly7En,
1763  --[NOT_USED] piSHL_Mmio_EchoCtrl_V => piSHL_Mmio_UdpEchoCtrl,
1764  --[NOT_USED] piSHL_Mmio_PostDgmEn_V => piSHL_Mmio_UdpPostDgmEn,
1765  --[NOT_USED] piSHL_Mmio_CaptDgmEn_V => piSHL_Mmio_UdpCaptDgmEn,
1766  --------------------------------------------------------
1767  -- From USIF / UDP Rx Data Interfaces
1768  --------------------------------------------------------
1769  siUSIF_Data_tdata => ssUARS_UAF_Data_tdata,
1770  siUSIF_Data_tkeep => ssUARS_UAF_Data_tkeep,
1771  siUSIF_Data_tlast => ssUARS_UAF_Data_tlast,
1772  siUSIF_Data_tvalid => ssUARS_UAF_Data_tvalid,
1773  siUSIF_Data_tready => ssUARS_UAF_Data_tready,
1774  --
1775  siUSIF_Meta_V_tdata => ssUARS_UAF_Meta_tdata,
1776  siUSIF_Meta_V_tvalid => ssUARS_UAF_Meta_tvalid,
1777  siUSIF_Meta_V_tready => ssUARS_UAF_Meta_tready,
1778  --
1779  siUSIF_DLen_V_V_tdata => ssUARS_UAF_DLen_tdata,
1780  siUSIF_DLen_V_V_tvalid=> ssUARS_UAF_DLen_tvalid,
1781  siUSIF_DLen_V_V_tready=> ssUARS_UAF_DLen_tready,
1782  --------------------------------------------------------
1783  -- To USIF / UDP Tx Data Interfaces
1784  --------------------------------------------------------
1785  soUSIF_Data_tdata => ssUAF_UARS_Data_tdata ,
1786  soUSIF_Data_tkeep => ssUAF_UARS_Data_tkeep ,
1787  soUSIF_Data_tlast => ssUAF_UARS_Data_tlast ,
1788  soUSIF_Data_tvalid => ssUAF_UARS_Data_tvalid,
1789  soUSIF_Data_tready => ssUAF_UARS_Data_tready,
1790  --
1791  soUSIF_Meta_V_tdata => ssUAF_UARS_Meta_tdata ,
1792  soUSIF_Meta_V_tvalid => ssUAF_UARS_Meta_tvalid,
1793  soUSIF_Meta_V_tready => ssUAF_UARS_Meta_tready,
1794  --
1795  soUSIF_DLen_V_V_tdata => ssUAF_UARS_DLen_tdata ,
1796  soUSIF_DLen_V_V_tvalid => ssUAF_UARS_DLen_tvalid,
1797  soUSIF_DLen_V_V_tready => ssUAF_UARS_DLen_tready
1798  );
1799  end generate;
1800 
1801  --###############################################################################
1802  --# #
1803  --# # # ##### ###### ###### #
1804  --# # # # # # # # # ##### #### #### #
1805  --# # # # # # # # # # # # #
1806  --# # # # # ###### ##### # #### # # ##### #
1807  --# # # # # # # # # # # # #
1808  --# ####### ##### # # # # #### #### #
1809  --# #
1810  --###############################################################################
1811  gUdpTxFifos : if gVivadoVersion /= 2016 generate
1812  ARS_UDP_RX_DATA : AxisRegisterSlice_64_8_1
1813  port map (
1814  aclk => piSHL_156_25Clk,
1815  aresetn => not piSHL_Mmio_Ly7Rst ,
1816  s_axis_tdata => ssUSIF_UARS_Data_tdata,
1817  s_axis_tkeep => ssUSIF_UARS_Data_tkeep,
1818  s_axis_tlast => ssUSIF_UARS_Data_tlast,
1819  s_axis_tvalid => ssUSIF_UARS_Data_tvalid,
1820  s_axis_tready => ssUSIF_UARS_Data_tready,
1821  --
1822  m_axis_tdata => ssUARS_UAF_Data_tdata,
1823  m_axis_tkeep => ssUARS_UAF_Data_tkeep,
1824  m_axis_tlast => ssUARS_UAF_Data_tlast,
1825  m_axis_tvalid => ssUARS_UAF_Data_tvalid,
1826  m_axis_tready => ssUARS_UAF_Data_tready
1827  );
1828  ARS_UDP_RX_META : AxisRegisterSlice_96
1829  port map (
1830  aclk => piSHL_156_25Clk,
1831  aresetn => not piSHL_Mmio_Ly7Rst ,
1832  s_axis_tdata => ssUSIF_UARS_Meta_tdata,
1833  s_axis_tvalid => ssUSIF_UARS_Meta_tvalid,
1834  s_axis_tready => ssUSIF_UARS_Meta_tready,
1835  --
1836  m_axis_tdata => ssUARS_UAF_Meta_tdata,
1837  m_axis_tvalid => ssUARS_UAF_Meta_tvalid,
1838  m_axis_tready => ssUARS_UAF_Meta_tready
1839  );
1840  --
1841  ARS_UDP_RX_DLEN : AxisRegisterSlice_16
1842  port map (
1843  aclk => piSHL_156_25Clk,
1844  aresetn => not piSHL_Mmio_Ly7Rst ,
1845  s_axis_tdata => ssUSIF_UARS_DLen_tdata,
1846  s_axis_tvalid => ssUSIF_UARS_DLen_tvalid,
1847  s_axis_tready => ssUSIF_UARS_DLen_tready,
1848  --
1849  m_axis_tdata => ssUARS_UAF_DLen_tdata,
1850  m_axis_tvalid => ssUARS_UAF_DLen_tvalid,
1851  m_axis_tready => ssUARS_UAF_DLen_tready
1852  );
1853  --
1854  ARS_UDP_TX_DATA : AxisRegisterSlice_64_8_1
1855  port map (
1856  aclk => piSHL_156_25Clk,
1857  aresetn => not piSHL_Mmio_Ly7Rst ,
1858  s_axis_tdata => ssUAF_UARS_Data_tdata,
1859  s_axis_tkeep => ssUAF_UARS_Data_tkeep,
1860  s_axis_tlast => ssUAF_UARS_Data_tlast,
1861  s_axis_tvalid => ssUAF_UARS_Data_tvalid,
1862  s_axis_tready => ssUAF_UARS_Data_tready,
1863  --
1864  m_axis_tdata => ssUARS_USIF_Data_tdata,
1865  m_axis_tkeep => ssUARS_USIF_Data_tkeep,
1866  m_axis_tlast => ssUARS_USIF_Data_tlast,
1867  m_axis_tvalid => ssUARS_USIF_Data_tvalid,
1868  m_axis_tready => ssUARS_USIF_Data_tready
1869  );
1870  ARS_UDP_TX_META : AxisRegisterSlice_96
1871  port map (
1872  aclk => piSHL_156_25Clk,
1873  aresetn => not piSHL_Mmio_Ly7Rst ,
1874  s_axis_tdata => ssUAF_UARS_Meta_tdata,
1875  s_axis_tvalid => ssUAF_UARS_Meta_tvalid,
1876  s_axis_tready => ssUAF_UARS_Meta_tready,
1877  --
1878  m_axis_tdata => ssUARS_USIF_Meta_tdata,
1879  m_axis_tvalid => ssUARS_USIF_Meta_tvalid,
1880  m_axis_tready => ssUARS_USIF_Meta_tready
1881  );
1882  ARS_UDP_TX_DLEN : AxisRegisterSlice_16
1883  port map (
1884  aclk => piSHL_156_25Clk,
1885  aresetn => not piSHL_Mmio_Ly7Rst ,
1886  s_axis_tdata => ssUAF_UARS_DLen_tdata,
1887  s_axis_tvalid => ssUAF_UARS_DLen_tvalid,
1888  s_axis_tready => ssUAF_UARS_DLen_tready,
1889  --
1890  m_axis_tdata => ssUARS_USIF_DLen_tdata,
1891  m_axis_tvalid => ssUARS_USIF_DLen_tvalid,
1892  m_axis_tready => ssUARS_USIF_DLen_tready
1893  );
1894 -- FIFO_UDP_RX_DATA : Fifo_16x73
1895 -- port map (
1896 -- clk => piSHL_156_25Clk,
1897 -- srst => piSHL_Mmio_Ly7Rst,
1898 -- din => ssUSIF_FIFO_Udp_Data_data,
1899 -- wr_en => ssUSIF_FIFO_Udp_Data_write,
1900 -- full => ssUSIF_FIFO_Udp_Data_full,
1901 -- --
1902 -- dout => ssFIFO_UAF_Udp_Data_data,
1903 -- rd_en => ssFIFO_UAF_Udp_Data_read,
1904 -- empty => ssFIFO_UAF_Udp_Data_empty,
1905 -- wr_rst_busy => open,
1906 -- rd_rst_busy => open
1907 -- );
1908 -- FIFO_UDP_RX_META : Fifo_16x96
1909 -- port map (
1910 -- clk => piSHL_156_25Clk,
1911 -- srst => piSHL_Mmio_Ly7Rst,
1912 -- din => ssUSIF_FIFO_Udp_Meta_data,
1913 -- wr_en => ssUSIF_FIFO_Udp_Meta_write,
1914 -- full => ssUSIF_FIFO_Udp_Meta_full,
1915 -- --
1916 -- dout => ssFIFO_UAF_Udp_Meta_data,
1917 -- rd_en => ssFIFO_UAF_Udp_Meta_read,
1918 -- empty => ssFIFO_UAF_Udp_Meta_empty,
1919 -- wr_rst_busy => open,
1920 -- rd_rst_busy => open
1921 -- );
1922 -- --
1923 -- FIFO_UDP_TX_DATA : Fifo_16x73
1924 -- port map (
1925 -- clk => piSHL_156_25Clk,
1926 -- srst => piSHL_Mmio_Ly7Rst,
1927 -- din => ssUAF_FIFO_Udp_Data_data,
1928 -- wr_en => ssUAF_FIFO_Udp_Data_write,
1929 -- full => ssUAF_FIFO_Udp_Data_full,
1930 -- --
1931 -- dout => ssFIFO_USIF_Udp_Data_data,
1932 -- rd_en => ssFIFO_USIF_Udp_Data_read,
1933 -- empty => ssFIFO_USIF_Udp_Data_empty,
1934 -- wr_rst_busy => open,
1935 -- rd_rst_busy => open
1936 -- );
1937 -- FIFO_UDP_TX_META : Fifo_16x96
1938 -- port map (
1939 -- clk => piSHL_156_25Clk,
1940 -- srst => piSHL_Mmio_Ly7Rst,
1941 -- din => ssUAF_FIFO_Udp_Meta_data,
1942 -- wr_en => ssUAF_FIFO_Udp_Meta_write,
1943 -- full => ssUAF_FIFO_Udp_Meta_full,
1944 -- --
1945 -- dout => ssFIFO_USIF_Udp_Meta_data,
1946 -- rd_en => ssFIFO_USIF_Udp_Meta_read,
1947 -- empty => ssFIFO_USIF_Udp_Meta_empty,
1948 -- wr_rst_busy => open,
1949 -- rd_rst_busy => open
1950 -- );
1951 -- FIFO_UDP_TX_DLEN : Fifo_16x16
1952 -- port map (
1953 -- clk => piSHL_156_25Clk,
1954 -- srst => piSHL_Mmio_Ly7Rst,
1955 -- din => ssUAF_FIFO_Udp_DLen_data,
1956 -- wr_en => ssUAF_FIFO_Udp_DLen_write,
1957 -- full => ssUAF_FIFO_Udp_DLen_full,
1958 -- --
1959 -- dout => ssFIFO_USIF_Udp_DLen_data,
1960 -- rd_en => ssFIFO_USIF_Udp_DLen_read,
1961 -- empty => ssFIFO_USIF_Udp_DLen_empty,
1962 -- wr_rst_busy => open,
1963 -- rd_rst_busy => open
1964 -- );
1965  end generate;
1966 
1967  --################################################################################
1968  --# #
1969  --# ####### ###### ### ####### #
1970  --# # # # # #
1971  --# # # # # #
1972  --# # ###### # #### #
1973  --# # # # # #
1974  --# # ###### ### # #
1975  --# #
1976  --################################################################################
1977  gTcpShellInterface : if gVivadoVersion = 2016 generate
1978  TSIF : TcpShellInterface_Deprecated
1979  port map (
1980  ------------------------------------------------------
1981  -- From SHELL / Clock and Reset
1982  ------------------------------------------------------
1983  aclk => piSHL_156_25Clk,
1984  aresetn => not piSHL_Mmio_Ly7Rst ,
1985  --------------------------------------------------------
1986  -- From SHELL / Mmio Interfaces
1987  --------------------------------------------------------
1988  piSHL_Mmio_En_V => piSHL_Mmio_Ly7En,
1989  ------------------------------------------------------
1990  -- TAF (via TARS) / Tx Data Interfaces (APP-->SHELL)
1991  ------------------------------------------------------
1992  siTAF_Data_tdata => ssTARS_TSIF_Data_tdata,
1993  siTAF_Data_tkeep => ssTARS_TSIF_Data_tkeep,
1994  siTAF_Data_tlast => ssTARS_TSIF_Data_tlast,
1995  siTAF_Data_tvalid => ssTARS_TSIF_Data_tvalid,
1996  siTAF_Data_tready => ssTARS_TSIF_Data_tready,
1997  --
1998  siTAF_SessId_tdata => ssTARS_TSIF_SessId_tdata,
1999  siTAF_SessId_tvalid => ssTARS_TSIF_SessId_tvalid,
2000  siTAF_SessId_tready => ssTARS_TSIF_SessId_tready,
2001  --
2002  siTAF_DatLen_tdata => ssTARS_TSIF_DatLen_tdata,
2003  siTAF_DatLen_tvalid => ssTARS_TSIF_DatLen_tvalid,
2004  siTAF_DatLen_tready => ssTARS_TSIF_DatLen_tready,
2005  ------------------------------------------------------
2006  -- TAF (via TARS) / Rx Data Interfaces (SHELL-->APP)
2007  ------------------------------------------------------
2008  soTAF_Data_tdata => ssTSIF_TARS_Data_tdata,
2009  soTAF_Data_tkeep => ssTSIF_TARS_Data_tkeep,
2010  soTAF_Data_tlast => ssTSIF_TARS_Data_tlast,
2011  soTAF_Data_tvalid => ssTSIF_TARS_Data_tvalid,
2012  soTAF_Data_tready => ssTSIF_TARS_Data_tready,
2013  --
2014  soTAF_SessId_tdata => ssTSIF_TARS_SessId_tdata,
2015  soTAF_SessId_tvalid => ssTSIF_TARS_SessId_tvalid,
2016  soTAF_SessId_tready => ssTSIF_TARS_SessId_tready,
2017  --
2018  soTAF_DatLen_tdata => ssTSIF_TARS_DatLen_tdata,
2019  soTAF_DatLen_tvalid => ssTSIF_TARS_DatLen_tvalid,
2020  soTAF_DatLen_tready => ssTSIF_TARS_DatLen_tready,
2021  ------------------------------------------------------
2022  -- SHELL / RxP Data Flow Interfaces
2023  ------------------------------------------------------
2024  ---- TCP Data Stream Notification
2025  siSHL_Notif_tdata => siSHL_Nts_Tcp_Notif_tdata,
2026  siSHL_Notif_tvalid => siSHL_Nts_Tcp_Notif_tvalid,
2027  siSHL_Notif_tready => siSHL_Nts_Tcp_Notif_tready,
2028  ---- TCP Data Request Stream -----
2029  soSHL_DReq_tdata => soSHL_Nts_Tcp_DReq_tdata,
2030  soSHL_DReq_tvalid => soSHL_Nts_Tcp_DReq_tvalid,
2031  soSHL_DReq_tready => soSHL_Nts_Tcp_DReq_tready,
2032  ---- TCP Data Stream ------------
2033  siSHL_Data_tdata => siSHL_Nts_Tcp_Data_tdata,
2034  siSHL_Data_tkeep => siSHL_Nts_Tcp_Data_tkeep,
2035  siSHL_Data_tlast => siSHL_Nts_Tcp_Data_tlast,
2036  siSHL_Data_tvalid => siSHL_Nts_Tcp_Data_tvalid,
2037  siSHL_Data_tready => siSHL_Nts_Tcp_Data_tready,
2038  ---- TCP Meta Stream -------------
2039  siSHL_Meta_tdata => siSHL_Nts_Tcp_Meta_tdata,
2040  siSHL_Meta_tvalid => siSHL_Nts_Tcp_Meta_tvalid,
2041  siSHL_Meta_tready => siSHL_Nts_Tcp_Meta_tready,
2042  ------------------------------------------------------
2043  -- SHELL / RxP Ctlr Flow Interfaces
2044  ------------------------------------------------------
2045  -- FPGA Receive Path (SHELL-->APP) --------
2046  ---- TCP Listen Request Stream -----
2047  soSHL_LsnReq_tdata => soSHL_Nts_Tcp_LsnReq_tdata,
2048  soSHL_LsnReq_tvalid => soSHL_Nts_Tcp_LsnReq_tvalid,
2049  soSHL_LsnReq_tready => soSHL_Nts_Tcp_LsnReq_tready,
2050  ---- TCP Listen Rep Stream ---------
2051  siSHL_LsnRep_tdata => siSHL_Nts_Tcp_LsnRep_tdata,
2052  siSHL_LsnRep_tvalid => siSHL_Nts_Tcp_LsnRep_tvalid,
2053  siSHL_LsnRep_tready => siSHL_Nts_Tcp_LsnRep_tready,
2054  ------------------------------------------------------
2055  -- SHELL / TxP Data Flow Interfaces
2056  ------------------------------------------------------
2057  ---- TCP Data Stream -------------
2058  soSHL_Data_tdata => soSHL_Nts_Tcp_Data_tdata,
2059  soSHL_Data_tkeep => soSHL_Nts_Tcp_Data_tkeep,
2060  soSHL_Data_tlast => soSHL_Nts_Tcp_Data_tlast,
2061  soSHL_Data_tvalid => soSHL_Nts_Tcp_Data_tvalid,
2062  soSHL_Data_tready => soSHL_Nts_Tcp_Data_tready,
2063  ---- TCP Send Request ------------
2064  soSHL_SndReq_tdata => soSHL_Nts_Tcp_SndReq_tdata,
2065  soSHL_SndReq_tvalid => soSHL_Nts_Tcp_SndReq_tvalid,
2066  soSHL_SndReq_tready => soSHL_Nts_Tcp_SndReq_tready,
2067  ---- TCP Send Reply --------------
2068  siSHL_SndRep_tdata => siSHL_Nts_Tcp_SndRep_tdata,
2069  siSHL_SndRep_tvalid => siSHL_Nts_Tcp_SndRep_tvalid,
2070  siSHL_SndRep_tready => siSHL_Nts_Tcp_SndRep_tready,
2071  ------------------------------------------------------
2072  -- SHELL / TxP Ctlr Flow Interfaces
2073  ------------------------------------------------------
2074  -- FPGA Transmit Path (APP-->SHELL) -------
2075  ---- TCP Open Session Request Stream
2076  soSHL_OpnReq_tdata => soSHL_Nts_Tcp_OpnReq_tdata,
2077  soSHL_OpnReq_tvalid => soSHL_Nts_Tcp_OpnReq_tvalid,
2078  soSHL_OpnReq_tready => soSHL_Nts_Tcp_OpnReq_tready,
2079  ---- TCP Open Session Status Stream
2080  siSHL_OpnRep_tdata => siSHL_Nts_Tcp_OpnRep_tdata,
2081  siSHL_OpnRep_tvalid => siSHL_Nts_Tcp_OpnRep_tvalid,
2082  siSHL_OpnRep_tready => siSHL_Nts_Tcp_OpnRep_tready,
2083  ---- TCP Close Request Stream ---
2084  soSHL_ClsReq_tdata => soSHL_Nts_Tcp_ClsReq_tdata,
2085  soSHL_ClsReq_tvalid => soSHL_Nts_Tcp_ClsReq_tvalid,
2086  soSHL_ClsReq_tready => soSHL_Nts_Tcp_ClsReq_tready
2087  ); -- End of: TcpShellInterface_Deprecated
2088  else generate
2089  TSIF : TcpShellInterface
2090  port map (
2091  ------------------------------------------------------
2092  -- From SHELL / Clock and Reset
2093  ------------------------------------------------------
2094  ap_clk => piSHL_156_25Clk,
2095  ap_rst_n => not piSHL_Mmio_Ly7Rst ,
2096  --------------------------------------------------------
2097  -- From SHELL / Mmio Interfaces
2098  --------------------------------------------------------
2099  piSHL_Mmio_En_V => piSHL_Mmio_Ly7En,
2100  ------------------------------------------------------
2101  -- TAF (via TARS) / TxP Data Flow Interfaces (APP-->SHELL)
2102  ------------------------------------------------------
2103  siTAF_Data_tdata => ssTARS_TSIF_Data_tdata,
2104  siTAF_Data_tkeep => ssTARS_TSIF_Data_tkeep,
2105  siTAF_Data_tlast => ssTARS_TSIF_Data_tlast,
2106  siTAF_Data_tvalid => ssTARS_TSIF_Data_tvalid,
2107  siTAF_Data_tready => ssTARS_TSIF_Data_tready,
2108  --
2109  siTAF_SessId_V_V_tdata => ssTARS_TSIF_SessId_tdata,
2110  siTAF_SessId_V_V_tvalid => ssTARS_TSIF_SessId_tvalid,
2111  siTAF_SessId_V_V_tready => ssTARS_TSIF_SessId_tready,
2112  --
2113  siTAF_DatLen_V_V_tdata => ssTARS_TSIF_DatLen_tdata,
2114  siTAF_DatLen_V_V_tvalid => ssTARS_TSIF_DatLen_tvalid,
2115  siTAF_DatLen_V_V_tready => ssTARS_TSIF_DatLen_tready,
2116  ------------------------------------------------------
2117  -- TAF (via TARS) / RxP Data Flow Interfaces (SHELL-->APP)
2118  ------------------------------------------------------
2119  soTAF_Data_tdata => ssTSIF_TARS_Data_tdata,
2120  soTAF_Data_tkeep => ssTSIF_TARS_Data_tkeep,
2121  soTAF_Data_tlast => ssTSIF_TARS_Data_tlast,
2122  soTAF_Data_tvalid => ssTSIF_TARS_Data_tvalid,
2123  soTAF_Data_tready => ssTSIF_TARS_Data_tready,
2124  --
2125  soTAF_SessId_V_V_tdata => ssTSIF_TARS_SessId_tdata,
2126  soTAF_SessId_V_V_tvalid => ssTSIF_TARS_SessId_tvalid,
2127  soTAF_SessId_V_V_tready => ssTSIF_TARS_SessId_tready,
2128  --
2129  soTAF_DatLen_V_V_tdata => ssTSIF_TARS_DatLen_tdata,
2130  soTAF_DatLen_V_V_tvalid => ssTSIF_TARS_DatLen_tvalid,
2131  soTAF_DatLen_V_V_tready => ssTSIF_TARS_DatLen_tready,
2132  ------------------------------------------------------
2133  -- SHELL / RxP Data Flow Interfaces
2134  ------------------------------------------------------
2135  ---- TCP Data Notification Stream
2136  siSHL_Notif_V_tdata => siSHL_Nts_Tcp_Notif_tdata,
2137  siSHL_Notif_V_tvalid => siSHL_Nts_Tcp_Notif_tvalid,
2138  siSHL_Notif_V_tready => siSHL_Nts_Tcp_Notif_tready,
2139  ---- TCP Data Request Stream
2140  soSHL_DReq_V_tdata => soSHL_Nts_Tcp_DReq_tdata,
2141  soSHL_DReq_V_tvalid => soSHL_Nts_Tcp_DReq_tvalid,
2142  soSHL_DReq_V_tready => soSHL_Nts_Tcp_DReq_tready,
2143  ---- TCP Data Stream
2144  siSHL_Data_tdata => siSHL_Nts_Tcp_Data_tdata,
2145  siSHL_Data_tkeep => siSHL_Nts_Tcp_Data_tkeep,
2146  siSHL_Data_tlast => siSHL_Nts_Tcp_Data_tlast,
2147  siSHL_Data_tvalid => siSHL_Nts_Tcp_Data_tvalid,
2148  siSHL_Data_tready => siSHL_Nts_Tcp_Data_tready,
2149  ---- TCP Metadata Stream
2150  siSHL_Meta_V_V_tdata => siSHL_Nts_Tcp_Meta_tdata,
2151  siSHL_Meta_V_V_tvalid => siSHL_Nts_Tcp_Meta_tvalid,
2152  siSHL_Meta_V_V_tready => siSHL_Nts_Tcp_Meta_tready,
2153  ------------------------------------------------------
2154  -- SHELL / RxP Ctlr Flow Interfaces
2155  ------------------------------------------------------
2156  -- FPGA Receive Path (SHELL-->APP) ------- :
2157  ---- TCP Listen Request Stream
2158  soSHL_LsnReq_V_V_tdata => soSHL_Nts_Tcp_LsnReq_tdata,
2159  soSHL_LsnReq_V_V_tvalid => soSHL_Nts_Tcp_LsnReq_tvalid,
2160  soSHL_LsnReq_V_V_tready => soSHL_Nts_Tcp_LsnReq_tready,
2161  ---- TCP Listen Stream
2162  siSHL_LsnRep_V_tdata => siSHL_Nts_Tcp_LsnRep_tdata,
2163  siSHL_LsnRep_V_tvalid => siSHL_Nts_Tcp_LsnRep_tvalid,
2164  siSHL_LsnRep_V_tready => siSHL_Nts_Tcp_LsnRep_tready,
2165  ------------------------------------------------------
2166  -- SHELL / TxP Data Flow Interfaces
2167  ------------------------------------------------------
2168  ---- TCP Data Stream
2169  soSHL_Data_tdata => soSHL_Nts_Tcp_Data_tdata,
2170  soSHL_Data_tkeep => soSHL_Nts_Tcp_Data_tkeep,
2171  soSHL_Data_tlast => soSHL_Nts_Tcp_Data_tlast,
2172  soSHL_Data_tvalid => soSHL_Nts_Tcp_Data_tvalid,
2173  soSHL_Data_tready => soSHL_Nts_Tcp_Data_tready,
2174  ---- TCP Send Request
2175  soSHL_SndReq_V_tdata => soSHL_Nts_Tcp_SndReq_tdata,
2176  soSHL_SndReq_V_tvalid => soSHL_Nts_Tcp_SndReq_tvalid,
2177  soSHL_SndReq_V_tready => soSHL_Nts_Tcp_SndReq_tready,
2178  ---- TCP Send Reply
2179  siSHL_SndRep_V_tdata => siSHL_Nts_Tcp_SndRep_tdata,
2180  siSHL_SndRep_V_tvalid => siSHL_Nts_Tcp_SndRep_tvalid,
2181  siSHL_SndRep_V_tready => siSHL_Nts_Tcp_SndRep_tready,
2182  ------------------------------------------------------
2183  -- SHELL / TxP Ctlr Flow Interfaces
2184  ------------------------------------------------------
2185  -- FPGA Transmit Path (APP-->SHELL) ------
2186  ---- TCP Open Session Request Stream
2187  soSHL_OpnReq_V_tdata => soSHL_Nts_Tcp_OpnReq_tdata,
2188  soSHL_OpnReq_V_tvalid => soSHL_Nts_Tcp_OpnReq_tvalid,
2189  soSHL_OpnReq_V_tready => soSHL_Nts_Tcp_OpnReq_tready,
2190  ---- TCP Open Session Status Stream
2191  siSHL_OpnRep_V_tdata => siSHL_Nts_Tcp_OpnRep_tdata,
2192  siSHL_OpnRep_V_tvalid => siSHL_Nts_Tcp_OpnRep_tvalid,
2193  siSHL_OpnRep_V_tready => siSHL_Nts_Tcp_OpnRep_tready,
2194  ---- TCP Close Request Stream
2195  soSHL_ClsReq_V_V_tdata => soSHL_Nts_Tcp_ClsReq_tdata,
2196  soSHL_ClsReq_V_V_tvalid => soSHL_Nts_Tcp_ClsReq_tvalid,
2197  soSHL_ClsReq_V_V_tready => soSHL_Nts_Tcp_ClsReq_tready,
2198  ------------------------------------------------------
2199  -- DEBUG Interfaces
2200  ------------------------------------------------------
2201  ---- Sink Counter Stream
2202  soDBG_SinkCnt_V_V_tdata => ssTSIF_ARS_SinkCnt_tdata,
2203  soDBG_SinkCnt_V_V_tvalid => ssTSIF_ARS_SinkCnt_tvalid,
2204  soDBG_SinkCnt_V_V_tready => ssTSIF_ARS_SinkCnt_tready,
2205  ---- Input Buffer Space Stream
2206  soDBG_InpBufSpace_V_V_tdata => sTSIF_DBG_InpBufSpace,
2207  soDBG_InpBufSpace_V_V_tvalid => open,
2208  soDBG_InpBufSpace_V_V_tready => '1'
2209  ); -- End of: TcpShellInterface
2210  end generate;
2211 
2212  --###############################################################################
2213  --# #
2214  --# ####### #### ###### ### #
2215  --# # # # # # # #### #### #
2216  --# # # # # # # # # # #
2217  --# # # ###### ##### #### ##### #
2218  --# # # # # # # # # #
2219  --# # #### # # # # # #### #
2220  --# #
2221  --###############################################################################
2222  gArsTcp : if gVivadoVersion /= 2016 generate
2223  ARS_TCP_RX_DATA : AxisRegisterSlice_64_8_1
2224  port map (
2225  aclk => piSHL_156_25Clk,
2226  aresetn => not piSHL_Mmio_Ly7Rst ,
2227  s_axis_tdata => ssTSIF_TARS_Data_tdata,
2228  s_axis_tkeep => ssTSIF_TARS_Data_tkeep,
2229  s_axis_tlast => ssTSIF_TARS_Data_tlast,
2230  s_axis_tvalid => ssTSIF_TARS_Data_tvalid,
2231  s_axis_tready => ssTSIF_TARS_Data_tready,
2232  --
2233  m_axis_tdata => ssTARS_TAF_Data_tdata,
2234  m_axis_tkeep => ssTARS_TAF_Data_tkeep,
2235  m_axis_tlast => ssTARS_TAF_Data_tlast,
2236  m_axis_tvalid => ssTARS_TAF_Data_tvalid,
2237  m_axis_tready => ssTARS_TAF_Data_tready
2238  );
2239  ARS_TCP_RX_SESSID : AxisRegisterSlice_16
2240  port map (
2241  aclk => piSHL_156_25Clk,
2242  aresetn => not piSHL_Mmio_Ly7Rst ,
2243  s_axis_tdata => ssTSIF_TARS_SessId_tdata,
2244  s_axis_tvalid => ssTSIF_TARS_SessId_tvalid,
2245  s_axis_tready => ssTSIF_TARS_SessId_tready,
2246  --
2247  m_axis_tdata => ssTARS_TAF_SessId_tdata,
2248  m_axis_tvalid => ssTARS_TAF_SessId_tvalid,
2249  m_axis_tready => ssTARS_TAF_SessId_tready
2250  );
2251  ARS_TCP_RX_DATLEN : AxisRegisterSlice_16
2252  port map (
2253  aclk => piSHL_156_25Clk,
2254  aresetn => not piSHL_Mmio_Ly7Rst ,
2255  s_axis_tdata => ssTSIF_TARS_DatLen_tdata,
2256  s_axis_tvalid => ssTSIF_TARS_DatLen_tvalid,
2257  s_axis_tready => ssTSIF_TARS_DatLen_tready,
2258  --
2259  m_axis_tdata => ssTARS_TAF_DatLen_tdata,
2260  m_axis_tvalid => ssTARS_TAF_DatLen_tvalid,
2261  m_axis_tready => ssTARS_TAF_DatLen_tready
2262  );
2263  --
2264  ARS_TCP_TX_DATA : AxisRegisterSlice_64_8_1
2265  port map (
2266  aclk => piSHL_156_25Clk,
2267  aresetn => not piSHL_Mmio_Ly7Rst ,
2268  s_axis_tdata => ssTAF_TARS_Data_tdata,
2269  s_axis_tkeep => ssTAF_TARS_Data_tkeep,
2270  s_axis_tlast => ssTAF_TARS_Data_tlast,
2271  s_axis_tvalid => ssTAF_TARS_Data_tvalid,
2272  s_axis_tready => ssTAF_TARS_Data_tready,
2273  --
2274  m_axis_tdata => ssTARS_TSIF_Data_tdata,
2275  m_axis_tkeep => ssTARS_TSIF_Data_tkeep,
2276  m_axis_tlast => ssTARS_TSIF_Data_tlast,
2277  m_axis_tvalid => ssTARS_TSIF_Data_tvalid,
2278  m_axis_tready => ssTARS_TSIF_Data_tready
2279  );
2280  ARS_TCP_TX_SESSID : AxisRegisterSlice_16
2281  port map (
2282  aclk => piSHL_156_25Clk,
2283  aresetn => not piSHL_Mmio_Ly7Rst ,
2284  s_axis_tdata => ssTAF_TARS_SessId_tdata,
2285  s_axis_tvalid => ssTAF_TARS_SessId_tvalid,
2286  s_axis_tready => ssTAF_TARS_SessId_tready,
2287  --
2288  m_axis_tdata => ssTARS_TSIF_SessId_tdata,
2289  m_axis_tvalid => ssTARS_TSIF_SessId_tvalid,
2290  m_axis_tready => ssTARS_TSIF_SessId_tready
2291  );
2292  ARS_TCP_TX_DATLEN : AxisRegisterSlice_16
2293  port map (
2294  aclk => piSHL_156_25Clk,
2295  aresetn => not piSHL_Mmio_Ly7Rst ,
2296  s_axis_tdata => ssTAF_TARS_DatLen_tdata,
2297  s_axis_tvalid => ssTAF_TARS_DatLen_tvalid,
2298  s_axis_tready => ssTAF_TARS_DatLen_tready,
2299  --
2300  m_axis_tdata => ssTARS_TSIF_DatLen_tdata,
2301  m_axis_tvalid => ssTARS_TSIF_DatLen_tvalid,
2302  m_axis_tready => ssTARS_TSIF_DatLen_tready
2303  );
2304  --
2305  ARS_TCP_DBG_SINK_CNT : AxisRegisterSlice_32
2306  port map (
2307  aclk => piSHL_156_25Clk,
2308  aresetn => not piSHL_Mmio_Ly7Rst ,
2309  s_axis_tdata => ssTSIF_ARS_SinkCnt_tdata,
2310  s_axis_tvalid => ssTSIF_ARS_SinkCnt_tvalid,
2311  s_axis_tready => ssTSIF_ARS_SinkCnt_tready,
2312  --
2313  m_axis_tdata => sTSIF_DBG_SinkCnt,
2314  m_axis_tvalid => open,
2315  m_axis_tready => '1'
2316  );
2317  end generate;
2318 
2319  --################################################################################
2320  --# #
2321  --# ####### #### ###### ##### #
2322  --# # # # # # # ##### ##### #
2323  --# # # # # # # # # # # #
2324  --# # # ###### ####### ##### ##### #
2325  --# # # # # # # # #
2326  --# # #### # # # # # #
2327  --# #
2328  --################################################################################
2329 
2330  --==========================================================================
2331  --== INST: TCP-APPLICATION_FLASH (TAF) for cFp_HelloKale
2332  --== This application implements a set of TCP-oriented tests. The [TAF]
2333  --== connects to the SHELL via a TCP Shell Interface (TSIF) block. The
2334  --== main purpose of the [TSIF] is to provide a placeholder for the
2335  --== opening of one or multiple listening port(s). The use of the [TSIF] is
2336  --== not a prerequisite, but it is provided here for sake of simplicity.
2337  --==========================================================================
2338  gTcpAppFlash : if gVivadoVersion = 2016 generate
2339  TAF : TcpApplicationFlash_Deprecated
2340  port map (
2341  ------------------------------------------------------
2342  -- From SHELL / Clock and Reset
2343  ------------------------------------------------------
2344  aclk => piSHL_156_25Clk,
2345  aresetn => not piSHL_Mmio_Ly7Rst ,
2346  -------------------- ------------------------------------
2347  -- From SHELL / Mmio Interfaces
2348  -------------------- ------------------------------------
2349  --[NOT_USED] piSHL_MmioEchoCtrl_V => piSHL_Mmio_TcpEchoCtrl,
2350  --[NOT_USED] piSHL_MmioPostSegEn_V => piSHL_Mmio_TcpPostSegEn,
2351  --[NOT_USED] piSHL_MmioCaptSegEn_V => piSHL_Mmio_TcpCaptSegEn,
2352  --------------------- -----------------------------------
2353  -- From TSIF (via TARS) / Tcp Rx Data Interfaces
2354  --------------------- -----------------------------------
2355  siTSIF_Data_tdata => ssTARS_TAF_Data_tdata,
2356  siTSIF_Data_tkeep => ssTARS_TAF_Data_tkeep,
2357  siTSIF_Data_tlast => ssTARS_TAF_Data_tlast,
2358  siTSIF_Data_tvalid => ssTARS_TAF_Data_tvalid,
2359  siTSIF_Data_tready => ssTARS_TAF_Data_tready,
2360  --
2361  siTSIF_SessId_tdata => ssTARS_TAF_SessId_tdata,
2362  siTSIF_SessId_tvalid => ssTARS_TAF_SessId_tvalid,
2363  siTSIF_SessId_tready => ssTARS_TAF_SessId_tready,
2364  --TSIF
2365  siTSIF_DatLen_tdata => ssTARS_TAF_DatLen_tdata,
2366  siTSIF_DatLen_tvalid => ssTARS_TAF_DatLen_tvalid,
2367  siTSIF_DatLen_tready => ssTARS_TAF_DatLen_tready,
2368  --------------------- -----------------------------------
2369  -- To TSIF (via TARS) / Tcp Tx Data Interfaces
2370  --------------------- -----------------------------------
2371  soTSIF_Data_tdata => ssTAF_TARS_Data_tdata,
2372  soTSIF_Data_tkeep => ssTAF_TARS_Data_tkeep,
2373  soTSIF_Data_tlast => ssTAF_TARS_Data_tlast,
2374  soTSIF_Data_tvalid => ssTAF_TARS_Data_tvalid,
2375  soTSIF_Data_tready => ssTAF_TARS_Data_tready,
2376  --
2377  soTSIF_SessId_tdata => ssTAF_TARS_SessId_tdata,
2378  soTSIF_SessId_tvalid => ssTAF_TARS_SessId_tvalid,
2379  soTSIF_SessId_tready => ssTAF_TARS_SessId_tready,
2380  --
2381  soTSIF_DatLen_tdata => ssTAF_TARS_DatLen_tdata,
2382  soTSIF_DatLen_tvalid => ssTAF_TARS_DatLen_tvalid,
2383  soTSIF_DatLen_tready => ssTAF_TARS_DatLen_tready
2384  );
2385  else generate
2386  TAF : TcpApplicationFlash
2387  port map (
2388  ------------------------------------------------------
2389  -- From SHELL / Clock and Reset
2390  ------------------------------------------------------
2391  ap_clk => piSHL_156_25Clk,
2392  ap_rst_n => not (piSHL_Mmio_Ly7Rst),
2393  --------------------------------------------------------
2394  -- From SHELL / Mmio Interfaces
2395  --------------------------------------------------------
2396  --[NOT_USED] piSHL_MmioEchoCtrl_V => piSHL_Mmio_TcpEchoCtrl,
2397  --[NOT_USED] piSHL_MmioPostSegEn_V => piSHL_Mmio_TcpPostSegEn,
2398  --[NOT_USED] piSHL_MmioCaptSegEn => piSHL_Mmio_TcpCaptSegEn,
2399  --------------------------------------------------------
2400  -- From TSIF (via TARS) / Tcp Rx Data Interfaces
2401  --------------------------------------------------------
2402  siTSIF_Data_tdata => ssTARS_TAF_Data_tdata,
2403  siTSIF_Data_tkeep => ssTARS_TAF_Data_tkeep,
2404  siTSIF_Data_tlast => ssTARS_TAF_Data_tlast,
2405  siTSIF_Data_tvalid => ssTARS_TAF_Data_tvalid,
2406  siTSIF_Data_tready => ssTARS_TAF_Data_tready,
2407  --
2408  siTSIF_SessId_V_V_tdata => ssTARS_TAF_SessId_tdata,
2409  siTSIF_SessId_V_V_tvalid => ssTARS_TAF_SessId_tvalid,
2410  siTSIF_SessId_V_V_tready => ssTARS_TAF_SessId_tready,
2411  --
2412  siTSIF_DatLen_V_V_tdata => ssTARS_TAF_DatLen_tdata,
2413  siTSIF_DatLen_V_V_tvalid => ssTARS_TAF_DatLen_tvalid,
2414  siTSIF_DatLen_V_V_tready => ssTARS_TAF_DatLen_tready,
2415  --------------------------------------------------------
2416  -- To TSIF (via TARS) / Tcp Tx Data Interfaces
2417  --------------------------------------------------------
2418  soTSIF_Data_tdata => ssTAF_TARS_Data_tdata,
2419  soTSIF_Data_tkeep => ssTAF_TARS_Data_tkeep,
2420  soTSIF_Data_tlast => ssTAF_TARS_Data_tlast,
2421  soTSIF_Data_tvalid => ssTAF_TARS_Data_tvalid,
2422  soTSIF_Data_tready => ssTAF_TARS_Data_tready,
2423  --
2424  soTSIF_SessId_V_V_tdata => ssTAF_TARS_SessId_tdata,
2425  soTSIF_SessId_V_V_tvalid => ssTAF_TARS_SessId_tvalid,
2426  soTSIF_SessId_V_V_tready => ssTAF_TARS_SessId_tready,
2427  --
2428  soTSIF_DatLen_V_V_tdata => ssTAF_TARS_DatLen_tdata,
2429  soTSIF_DatLen_V_V_tvalid => ssTAF_TARS_DatLen_tvalid,
2430  soTSIF_DatLen_V_V_tready => ssTAF_TARS_DatLen_tready
2431  );
2432  end generate;
2433 
2434  -- ========================================================================
2435  -- == Generation of a delayed reset for the MemTest core
2436  -- == [TODO: Can we get ret rid of this reset]
2437  -- ========================================================================
2438  process(piSHL_156_25Clk)
2439  begin
2440  if rising_edge(piSHL_156_25Clk) then
2441  if piSHL_156_25Rst = '1' then
2442  s156_25Rst_delayed <= '0';
2443  sRstDelayCounter <= (others => '0');
2444  else
2445  if unsigned(sRstDelayCounter) <= 20 then
2446  s156_25Rst_delayed <= '1';
2447  sRstDelayCounter <= std_logic_vector(unsigned(sRstDelayCounter) + 1);
2448  else
2449  s156_25Rst_delayed <= '0';
2450  end if;
2451  end if;
2452  end if;
2453  end process;
2454 
2455 
2456  --################################################################################
2457  --# #
2458  --# # # ###### # # ###### ##### #### #
2459  --# ## ## # ## ## # ###### ###### ###### # # # ## #
2460  --# # ## # ##### # ## # # # # # ##### # # # #
2461  --# # # # # # # #### ###### # # # # # #
2462  --# # # # # # # # # # # ## # #
2463  --# # # ###### # # # ###### ###### # # #### #
2464  --# #
2465  --################################################################################
2466 
2467  MEM_TEST: MemTestFlash
2468  port map(
2469  ------------------------------------------------------
2470  -- From SHELL / Clock and Reset
2471  ------------------------------------------------------
2472  ap_clk => piSHL_156_25Clk,
2473  ap_rst_n => not piSHL_Mmio_Ly7Rst ,
2474  ------------------------------------------------------
2475  -- BLock-Level I/O Protocol
2476  ------------------------------------------------------
2477  ap_start => '1',
2478  ap_done => open,
2479  ap_idle => open,
2480  ap_ready => open,
2481  ------------------------------------------------------
2482  -- From ROLE / Delayed Reset
2483  ------------------------------------------------------
2484  piSysReset_V => fVectorize(s156_25Rst_delayed),
2485  piSysReset_V_ap_vld => '1',
2486  --------------------------------------------------------
2487  -- From SHELL / Mmio Interfaces
2488  --------------------------------------------------------
2489  piMMIO_diag_ctrl_V => piSHL_Mmio_Mc1_MemTestCtrl,
2490  piMMIO_diag_ctrl_V_ap_vld => '1',
2491  poMMIO_diag_stat_V => poSHL_Mmio_Mc1_MemTestStat,
2492  poDebug_V => poSHL_Mmio_RdReg,
2493  --------------------------------------------------------
2494  -- SHELL / Mem / Mp0 Interface
2495  --------------------------------------------------------
2496  ---- Stream Read Command ---------
2497  soMemRdCmdP0_TDATA => soSHL_Mem_Mp0_RdCmd_tdata,
2498  soMemRdCmdP0_TVALID => soSHL_Mem_Mp0_RdCmd_tvalid,
2499  soMemRdCmdP0_TREADY => soSHL_Mem_Mp0_RdCmd_tready,
2500  ---- Stream Read Status ----------
2501  siMemRdStsP0_TDATA => siSHL_Mem_Mp0_RdSts_tdata,
2502  siMemRdStsP0_TVALID => siSHL_Mem_Mp0_RdSts_tvalid,
2503  siMemRdStsP0_TREADY => siSHL_Mem_Mp0_RdSts_tready,
2504  ---- Stream Read Data ------------
2505  siMemReadP0_TDATA => siSHL_Mem_Mp0_Read_tdata,
2506  siMemReadP0_TVALID => siSHL_Mem_Mp0_Read_tvalid,
2507  siMemReadP0_TREADY => siSHL_Mem_Mp0_Read_tready,
2508  siMemReadP0_TKEEP => siSHL_Mem_Mp0_Read_tkeep,
2509  siMemReadP0_TLAST => fVectorize(siSHL_Mem_Mp0_Read_tlast),
2510  ---- Stream Write Command --------
2511  soMemWrCmdP0_TDATA => soSHL_Mem_Mp0_WrCmd_tdata,
2512  soMemWrCmdP0_TVALID => soSHL_Mem_Mp0_WrCmd_tvalid,
2513  soMemWrCmdP0_TREADY => soSHL_Mem_Mp0_WrCmd_tready,
2514  ---- Stream Write Status ---------
2515  siMemWrStsP0_TDATA => siSHL_Mem_Mp0_WrSts_tdata,
2516  siMemWrStsP0_TVALID => siSHL_Mem_Mp0_WrSts_tvalid,
2517  siMemWrStsP0_TREADY => siSHL_Mem_Mp0_WrSts_tready,
2518  ---- Stream Write Data ---------
2519  soMemWriteP0_TDATA => soSHL_Mem_Mp0_Write_tdata,
2520  soMemWriteP0_TVALID => soSHL_Mem_Mp0_Write_tvalid,
2521  soMemWriteP0_TREADY => soSHL_Mem_Mp0_Write_tready,
2522  soMemWriteP0_TKEEP => soSHL_Mem_Mp0_Write_tkeep,
2523  soMemWriteP0_TLAST => sSHL_Mem_Mp0_Write_tlast
2524  ); -- End-of: MemTestFlash
2525 
2526  soSHL_Mem_Mp0_Write_tlast <= fScalarize(sSHL_Mem_Mp0_Write_tlast);
2527 
2528  --################################################################################
2529  --# #
2530  --# # # ###### # # ###### ##### # #
2531  --# ## ## # ## ## # ###### ###### ###### # # ## #
2532  --# # ## # ##### # ## # # # # # ##### # # #
2533  --# # # # # # # #### ###### # # # #
2534  --# # # # # # # # # # # # #
2535  --# # # ###### # # # ###### ###### # # ##### #
2536  --# #
2537  --################################################################################
2538 
2539  --------------------------------------------------------
2540  -- SHELL / Mem / Mp1 Interface
2541  --------------------------------------------------------
2542  ---- Write Address Channel -------------
2543  moSHL_Mem_Mp1_AWID <= (others => '0');
2544  moSHL_Mem_Mp1_AWADDR <= (others => '0');
2545  moSHL_Mem_Mp1_AWLEN <= (others => '0');
2546  moSHL_Mem_Mp1_AWSIZE <= (others => '0');
2547  moSHL_Mem_Mp1_AWBURST <= (others => '0');
2548  moSHL_Mem_Mp1_AWVALID <= '0' ;
2549  ---- Write Data Channel ----------------
2550  moSHL_Mem_Mp1_WDATA <= (others => '0');
2551  moSHL_Mem_Mp1_WSTRB <= (others => '0');
2552  moSHL_Mem_Mp1_WLAST <= '0' ;
2553  moSHL_Mem_Mp1_WVALID <= '0' ;
2554  ---- Write Response Channel ------------
2555  moSHL_Mem_Mp1_BREADY <= '0' ;
2556  ---- Read Address Channel --------------
2557  moSHL_Mem_Mp1_ARID <= (others => '0');
2558  moSHL_Mem_Mp1_ARADDR <= (others => '0');
2559  moSHL_Mem_Mp1_ARLEN <= (others => '0');
2560  moSHL_Mem_Mp1_ARSIZE <= (others => '0');
2561  moSHL_Mem_Mp1_ARBURST <= (others => '0');
2562  moSHL_Mem_Mp1_ARVALID <= '0' ;
2563  ---- Read Data Channel -----------------
2564  moSHL_Mem_Mp1_RREADY <= '0' ;
2565 
2566 end architecture BringUp;
2567 
Role_Kale
Definition: Role.vhdl:74
Role_Kale.soSHL_Mem_Mp0_RdCmd_tvalid
out soSHL_Mem_Mp0_RdCmd_tvalidstd_ulogic
Definition: Role.vhdl:179
Role_Kale.soSHL_Nts_Udp_DLen_tready
in soSHL_Nts_Udp_DLen_treadystd_ulogic
Definition: Role.vhdl:94
Role_Kale.siSHL_Nts_Tcp_Data_tkeep
in siSHL_Nts_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:124
Role_Kale.siSHL_Nts_Tcp_Notif_tvalid
in siSHL_Nts_Tcp_Notif_tvalidstd_ulogic
Definition: Role.vhdl:136
Role_Kale.siSHL_Nts_Tcp_SndRep_tdata
in siSHL_Nts_Tcp_SndRep_tdatastd_ulogic_vector(55 downto 0)
Definition: Role.vhdl:128
Role_Kale.siSHL_Nts_Tcp_LsnRep_tdata
in siSHL_Nts_Tcp_LsnRep_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:175
Role_Kale.siSHL_Mem_Mp0_Read_tlast
in siSHL_Mem_Mp0_Read_tlaststd_ulogic
Definition: Role.vhdl:188
Role_Kale.soSHL_Nts_Tcp_Data_tvalid
out soSHL_Nts_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:107
Role_Kale.moSHL_Mem_Mp1_RREADY
out moSHL_Mem_Mp1_RREADYstd_ulogic
Definition: Role.vhdl:246
Role_Kale.moSHL_Mem_Mp1_WREADY
in moSHL_Mem_Mp1_WREADYstd_ulogic
Definition: Role.vhdl:226
Role_Kale.siSHL_Nts_Tcp_OpnRep_tdata
in siSHL_Nts_Tcp_OpnRep_tdatastd_ulogic_vector(23 downto 0)
Definition: Role.vhdl:152
Role_Kale.siSHL_Mem_Mp0_WrSts_tvalid
in siSHL_Mem_Mp0_WrSts_tvalidstd_ulogic
Definition: Role.vhdl:197
Role_Kale.poSHL_Mmio_RdReg
out poSHL_Mmio_RdRegstd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:258
Role_Kale.piSHL_156_25Rst
in piSHL_156_25Rststd_ulogic
Definition: Role.vhdl:81
Role_Kale.siSHL_Nts_Udp_Data_tlast
in siSHL_Nts_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:89
Role_Kale.siSHL_Mem_Mp0_Read_tkeep
in siSHL_Mem_Mp0_Read_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:187
Role_Kale.soSHL_Nts_Tcp_SndReq_tvalid
out soSHL_Nts_Tcp_SndReq_tvalidstd_ulogic
Definition: Role.vhdl:125
Role_Kale.moSHL_Mem_Mp1_AWBURST
out moSHL_Mem_Mp1_AWBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:218
Role_Kale.soSHL_Nts_Tcp_DReq_tvalid
out soSHL_Nts_Tcp_DReq_tvalidstd_ulogic
Definition: Role.vhdl:140
Role_Kale.moSHL_Mem_Mp1_RID
in moSHL_Mem_Mp1_RIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:241
Role_Kale.soSHL_Nts_Tcp_OpnReq_tready
in soSHL_Nts_Tcp_OpnReq_treadystd_ulogic
Definition: Role.vhdl:150
Role_Kale.siSHL_Mem_Mp0_RdSts_tvalid
in siSHL_Mem_Mp0_RdSts_tvalidstd_ulogic
Definition: Role.vhdl:183
Role_Kale.soSHL_Mem_Mp0_WrCmd_tvalid
out soSHL_Mem_Mp0_WrCmd_tvalidstd_ulogic
Definition: Role.vhdl:193
Role_Kale.piSHL_Mmio_Ly7En
in piSHL_Mmio_Ly7Enstd_ulogic
Definition: Role.vhdl:245
Role_Kale.soSHL_Nts_Udp_LsnReq_tdata
out soSHL_Nts_Udp_LsnReq_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:99
Role_Kale.soSHL_Nts_Tcp_Data_tlast
out soSHL_Nts_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:106
Role_Kale.moSHL_Mem_Mp1_WVALID
out moSHL_Mem_Mp1_WVALIDstd_ulogic
Definition: Role.vhdl:225
Role_Kale.siSHL_Mem_Mp0_Read_tready
out siSHL_Mem_Mp0_Read_treadystd_ulogic
Definition: Role.vhdl:190
Role_Kale.soSHL_Nts_Udp_DLen_tvalid
out soSHL_Nts_Udp_DLen_tvalidstd_ulogic
Definition: Role.vhdl:93
Role_Kale.soSHL_Nts_Tcp_ClsReq_tdata
out soSHL_Nts_Tcp_ClsReq_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:156
Role_Kale.soSHL_Nts_Udp_Meta_tdata
out soSHL_Nts_Udp_Meta_tdatastd_ulogic_vector(95 downto 0)
Definition: Role.vhdl:88
Role_Kale.moSHL_Mem_Mp1_BREADY
out moSHL_Mem_Mp1_BREADYstd_ulogic
Definition: Role.vhdl:231
Role_Kale.siSHL_Nts_Udp_Data_tready
out siSHL_Nts_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:91
Role_Kale.siSHL_Nts_Udp_ClsRep_tvalid
in siSHL_Nts_Udp_ClsRep_tvalidstd_ulogic
Definition: Role.vhdl:112
Role_Kale.siSHL_Nts_Udp_ClsRep_tdata
in siSHL_Nts_Udp_ClsRep_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:111
Role_Kale.siSHL_Mem_Mp0_WrSts_tdata
in siSHL_Mem_Mp0_WrSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:196
Role_Kale.soSHL_Nts_Tcp_DReq_tready
in soSHL_Nts_Tcp_DReq_treadystd_ulogic
Definition: Role.vhdl:141
Role_Kale.piSHL_156_25Clk
in piSHL_156_25Clkstd_ulogic
Definition: Role.vhdl:80
Role_Kale.soSHL_Nts_Tcp_LsnReq_tvalid
out soSHL_Nts_Tcp_LsnReq_tvalidstd_ulogic
Definition: Role.vhdl:166
Role_Kale.siSHL_Nts_Tcp_Meta_tready
out siSHL_Nts_Tcp_Meta_treadystd_ulogic
Definition: Role.vhdl:133
Role_Kale.siSHL_Nts_Udp_Meta_tdata
in siSHL_Nts_Udp_Meta_tdatastd_ulogic_vector(95 downto 0)
Definition: Role.vhdl:71
Role_Kale.moSHL_Mem_Mp1_AWREADY
in moSHL_Mem_Mp1_AWREADYstd_ulogic
Definition: Role.vhdl:220
Role_Kale.moSHL_Mem_Mp1_RRESP
in moSHL_Mem_Mp1_RRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:243
Role_Kale.soSHL_Nts_Udp_Data_tvalid
out soSHL_Nts_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:96
Role_Kale.siSHL_Nts_Tcp_Data_tready
out siSHL_Nts_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:127
Role_Kale.siSHL_Nts_Udp_Data_tdata
in siSHL_Nts_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:87
Role_Kale.poSHL_Mmio_Mc1_MemTestStat
out poSHL_Mmio_Mc1_MemTestStatstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:249
Role_Kale.soSHL_Nts_Tcp_Data_tready
in soSHL_Nts_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:108
Role_Kale.soSHL_Mem_Mp0_Write_tready
in soSHL_Mem_Mp0_Write_treadystd_ulogic
Definition: Role.vhdl:204
Role_Kale.moSHL_Mem_Mp1_BID
in moSHL_Mem_Mp1_BIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:228
Role_Kale.soSHL_Nts_Udp_ClsReq_tready
in soSHL_Nts_Udp_ClsReq_treadystd_ulogic
Definition: Role.vhdl:109
Role_Kale.siSHL_Nts_Tcp_Notif_tready
out siSHL_Nts_Tcp_Notif_treadystd_ulogic
Definition: Role.vhdl:137
Role_Kale.siSHL_Nts_Tcp_OpnRep_tvalid
in siSHL_Nts_Tcp_OpnRep_tvalidstd_ulogic
Definition: Role.vhdl:153
Role_Kale.soSHL_Mem_Mp0_WrCmd_tdata
out soSHL_Mem_Mp0_WrCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:192
Role_Kale.siSHL_Nts_Tcp_OpnRep_tready
out siSHL_Nts_Tcp_OpnRep_treadystd_ulogic
Definition: Role.vhdl:154
Role_Kale.siSHL_Nts_Tcp_Data_tlast
in siSHL_Nts_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:125
Role_Kale.siSHL_Nts_Udp_Meta_tvalid
in siSHL_Nts_Udp_Meta_tvalidstd_ulogic
Definition: Role.vhdl:72
Role_Kale.soSHL_Nts_Udp_Data_tready
in soSHL_Nts_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:97
Role_Kale.moSHL_Mem_Mp1_BRESP
in moSHL_Mem_Mp1_BRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:229
Role_Kale.siSHL_Nts_Udp_DLen_tdata
in siSHL_Nts_Udp_DLen_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:75
Role_Kale.soSHL_Mem_Mp0_Write_tdata
out soSHL_Mem_Mp0_Write_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:200
Role_Kale.siSHL_Mem_Mp0_RdSts_tdata
in siSHL_Mem_Mp0_RdSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:182
Role_Kale.soSHL_Nts_Tcp_LsnReq_tdata
out soSHL_Nts_Tcp_LsnReq_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:165
Role_Kale.moSHL_Mem_Mp1_AWSIZE
out moSHL_Mem_Mp1_AWSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:217
Role_Kale.soSHL_Mem_Mp0_RdCmd_tready
in soSHL_Mem_Mp0_RdCmd_treadystd_ulogic
Definition: Role.vhdl:180
Role_Kale.piSHL_Mmio_Mc1_MemTestCtrl
in piSHL_Mmio_Mc1_MemTestCtrlstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:247
Role_Kale.soSHL_Nts_Udp_Data_tlast
out soSHL_Nts_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:95
Role_Kale.siSHL_Nts_Udp_LsnRep_tready
out siSHL_Nts_Udp_LsnRep_treadystd_ulogic
Definition: Role.vhdl:105
Role_Kale.soSHL_Nts_Udp_LsnReq_tready
in soSHL_Nts_Udp_LsnReq_treadystd_ulogic
Definition: Role.vhdl:101
Role_Kale.soSHL_Nts_Udp_DLen_tdata
out soSHL_Nts_Udp_DLen_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:92
Role_Kale.soSHL_Nts_Tcp_OpnReq_tvalid
out soSHL_Nts_Tcp_OpnReq_tvalidstd_ulogic
Definition: Role.vhdl:149
Role_Kale.gVivadoVersion
gVivadoVersioninteger :=2019
Definition: Role.vhdl:54
Role_Kale.soSHL_Nts_Tcp_OpnReq_tdata
out soSHL_Nts_Tcp_OpnReq_tdatastd_ulogic_vector(47 downto 0)
Definition: Role.vhdl:148
Role_Kale.moSHL_Mem_Mp1_RDATA
in moSHL_Mem_Mp1_RDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:242
Role_Kale.siSHL_Nts_Udp_DLen_tvalid
in siSHL_Nts_Udp_DLen_tvalidstd_ulogic
Definition: Role.vhdl:76
Role_Kale.moSHL_Mem_Mp1_RVALID
in moSHL_Mem_Mp1_RVALIDstd_ulogic
Definition: Role.vhdl:245
Role_Kale.moSHL_Mem_Mp1_WSTRB
out moSHL_Mem_Mp1_WSTRBstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:223
Role_Kale.soSHL_Nts_Tcp_ClsReq_tvalid
out soSHL_Nts_Tcp_ClsReq_tvalidstd_ulogic
Definition: Role.vhdl:157
Role_Kale.moSHL_Mem_Mp1_AWVALID
out moSHL_Mem_Mp1_AWVALIDstd_ulogic
Definition: Role.vhdl:219
Role_Kale.moSHL_Mem_Mp1_AWID
out moSHL_Mem_Mp1_AWIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:214
Role_Kale.soSHL_Mem_Mp0_Write_tvalid
out soSHL_Mem_Mp0_Write_tvalidstd_ulogic
Definition: Role.vhdl:203
Role_Kale.siSHL_Nts_Udp_ClsRep_tready
out siSHL_Nts_Udp_ClsRep_treadystd_ulogic
Definition: Role.vhdl:113
Role_Kale.siSHL_Nts_Tcp_SndRep_tready
out siSHL_Nts_Tcp_SndRep_treadystd_ulogic
Definition: Role.vhdl:130
Role_Kale.siSHL_Nts_Udp_Data_tkeep
in siSHL_Nts_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:88
Role_Kale.soSHL_Nts_Tcp_LsnReq_tready
in soSHL_Nts_Tcp_LsnReq_treadystd_ulogic
Definition: Role.vhdl:167
Role_Kale.soSHL_Nts_Tcp_SndReq_tready
in soSHL_Nts_Tcp_SndReq_treadystd_ulogic
Definition: Role.vhdl:126
Role_Kale.siSHL_Nts_Udp_LsnRep_tdata
in siSHL_Nts_Udp_LsnRep_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:103
Role_Kale.moSHL_Mem_Mp1_ARADDR
out moSHL_Mem_Mp1_ARADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:234
Role_Kale.soSHL_Mem_Mp0_WrCmd_tready
in soSHL_Mem_Mp0_WrCmd_treadystd_ulogic
Definition: Role.vhdl:194
Role_Kale.soSHL_Mem_Mp0_Write_tlast
out soSHL_Mem_Mp0_Write_tlaststd_ulogic
Definition: Role.vhdl:202
Role_Kale.siSHL_Nts_Tcp_Notif_tdata
in siSHL_Nts_Tcp_Notif_tdatastd_ulogic_vector(7+96 downto 0)
Definition: Role.vhdl:135
Role_Kale.soSHL_Nts_Tcp_Data_tdata
out soSHL_Nts_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:104
Role_Kale.soSHL_Nts_Udp_Meta_tvalid
out soSHL_Nts_Udp_Meta_tvalidstd_ulogic
Definition: Role.vhdl:89
Role_Kale.moSHL_Mem_Mp1_ARLEN
out moSHL_Mem_Mp1_ARLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:235
Role_Kale.siSHL_Nts_Udp_Meta_tready
out siSHL_Nts_Udp_Meta_treadystd_ulogic
Definition: Role.vhdl:73
Role_Kale.soSHL_Nts_Tcp_Data_tkeep
out soSHL_Nts_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:105
Role_Kale.soSHL_Nts_Udp_Data_tdata
out soSHL_Nts_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:93
Role_Kale.moSHL_Mem_Mp1_ARREADY
in moSHL_Mem_Mp1_ARREADYstd_ulogic
Definition: Role.vhdl:239
Role_Kale.siSHL_Nts_Tcp_Meta_tdata
in siSHL_Nts_Tcp_Meta_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:129
Role_Kale.soSHL_Nts_Udp_LsnReq_tvalid
out soSHL_Nts_Udp_LsnReq_tvalidstd_ulogic
Definition: Role.vhdl:100
Role_Kale.soSHL_Mem_Mp0_RdCmd_tdata
out soSHL_Mem_Mp0_RdCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:178
Role_Kale.siSHL_Nts_Tcp_Data_tdata
in siSHL_Nts_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:123
Role_Kale.moSHL_Mem_Mp1_AWLEN
out moSHL_Mem_Mp1_AWLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:216
Role_Kale.moSHL_Mem_Mp1_ARSIZE
out moSHL_Mem_Mp1_ARSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:236
Role_Kale.soSHL_Nts_Tcp_SndReq_tdata
out soSHL_Nts_Tcp_SndReq_tdatastd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:124
Role_Kale.siSHL_Nts_Udp_DLen_tready
out siSHL_Nts_Udp_DLen_treadystd_ulogic
Definition: Role.vhdl:77
Role_Kale.soSHL_Nts_Udp_Meta_tready
in soSHL_Nts_Udp_Meta_treadystd_ulogic
Definition: Role.vhdl:90
Role_Kale.moSHL_Mem_Mp1_WLAST
out moSHL_Mem_Mp1_WLASTstd_ulogic
Definition: Role.vhdl:224
Role_Kale.siSHL_Nts_Udp_LsnRep_tvalid
in siSHL_Nts_Udp_LsnRep_tvalidstd_ulogic
Definition: Role.vhdl:104
Role_Kale.soSHL_Nts_Tcp_DReq_tdata
out soSHL_Nts_Tcp_DReq_tdatastd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:139
Role_Kale.moSHL_Mem_Mp1_WDATA
out moSHL_Mem_Mp1_WDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:222
Role_Kale.soSHL_Nts_Udp_Data_tkeep
out soSHL_Nts_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:94
Role_Kale.siSHL_Nts_Tcp_SndRep_tvalid
in siSHL_Nts_Tcp_SndRep_tvalidstd_ulogic
Definition: Role.vhdl:129
Role_Kale.soSHL_Nts_Udp_ClsReq_tvalid
out soSHL_Nts_Udp_ClsReq_tvalidstd_ulogic
Definition: Role.vhdl:108
Role_Kale.soSHL_Nts_Udp_ClsReq_tdata
out soSHL_Nts_Udp_ClsReq_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:107
Role_Kale.siSHL_Mem_Mp0_Read_tvalid
in siSHL_Mem_Mp0_Read_tvalidstd_ulogic
Definition: Role.vhdl:189
Role_Kale.soSHL_Mem_Mp0_Write_tkeep
out soSHL_Mem_Mp0_Write_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:201
Role_Kale.siSHL_Nts_Udp_Data_tvalid
in siSHL_Nts_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:90
Role_Kale.siSHL_Nts_Tcp_LsnRep_tready
out siSHL_Nts_Tcp_LsnRep_treadystd_ulogic
Definition: Role.vhdl:177
Role_Kale.piTOP_250_00Clk
in piTOP_250_00Clkstd_ulogic
Definition: Role.vhdl:265
Role_Kale.moSHL_Mem_Mp1_RLAST
in moSHL_Mem_Mp1_RLASTstd_ulogic
Definition: Role.vhdl:244
Role_Kale.moSHL_Mem_Mp1_ARBURST
out moSHL_Mem_Mp1_ARBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:237
Role_Kale.siSHL_Nts_Tcp_Meta_tvalid
in siSHL_Nts_Tcp_Meta_tvalidstd_ulogic
Definition: Role.vhdl:132
Role_Kale.piSHL_Mmio_WrReg
in piSHL_Mmio_WrRegstd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:260
Role_Kale.moSHL_Mem_Mp1_BVALID
in moSHL_Mem_Mp1_BVALIDstd_ulogic
Definition: Role.vhdl:230
Role_Kale.siSHL_Nts_Tcp_LsnRep_tvalid
in siSHL_Nts_Tcp_LsnRep_tvalidstd_ulogic
Definition: Role.vhdl:176
Role_Kale.soSHL_Nts_Tcp_ClsReq_tready
in soSHL_Nts_Tcp_ClsReq_treadystd_ulogic
Definition: Role.vhdl:158
Role_Kale.moSHL_Mem_Mp1_ARID
out moSHL_Mem_Mp1_ARIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:233
Role_Kale.siSHL_Mem_Mp0_WrSts_tready
out siSHL_Mem_Mp0_WrSts_treadystd_ulogic
Definition: Role.vhdl:198
Role_Kale.siSHL_Mem_Mp0_RdSts_tready
out siSHL_Mem_Mp0_RdSts_treadystd_ulogic
Definition: Role.vhdl:184
Role_Kale.moSHL_Mem_Mp1_ARVALID
out moSHL_Mem_Mp1_ARVALIDstd_ulogic
Definition: Role.vhdl:238
Role_Kale.siSHL_Mem_Mp0_Read_tdata
in siSHL_Mem_Mp0_Read_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:186
Role_Kale.moSHL_Mem_Mp1_AWADDR
out moSHL_Mem_Mp1_AWADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:215
Role_Kale.piSHL_Mmio_Ly7Rst
in piSHL_Mmio_Ly7Rststd_ulogic
Definition: Role.vhdl:243
Role_Kale.siSHL_Nts_Tcp_Data_tvalid
in siSHL_Nts_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:126