cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
Macros | Functions
tb_mem_test_flash.cpp File Reference
#include "../src/mem_test_flash.hpp"
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Macros

#define TEST_MEM_SIZE   512
 
#define DUT   mem_test_flash_main(sys_reset, DIAG_CTRL_IN, &DIAG_STAT_OUT, &debug_out,sROL_Shl_Mem_RdCmdP0, sSHL_Rol_Mem_RdStsP0, sSHL_Rol_Mem_ReadP0,sROL_Shl_Mem_WrCmdP0, sSHL_Rol_Mem_WrStsP0, sROL_Shl_Mem_WriteP0);
 
#define TEST_ITERATIONS   (MEM_END_ADDR/CHECK_CHUNK_SIZE + 1)
 

Functions

int main ()
 

Macro Definition Documentation

◆ DUT

#define DUT   mem_test_flash_main(sys_reset, DIAG_CTRL_IN, &DIAG_STAT_OUT, &debug_out,sROL_Shl_Mem_RdCmdP0, sSHL_Rol_Mem_RdStsP0, sSHL_Rol_Mem_ReadP0,sROL_Shl_Mem_WrCmdP0, sSHL_Rol_Mem_WrStsP0, sROL_Shl_Mem_WriteP0);

◆ TEST_ITERATIONS

#define TEST_ITERATIONS   (MEM_END_ADDR/CHECK_CHUNK_SIZE + 1)

◆ TEST_MEM_SIZE

#define TEST_MEM_SIZE   512

Definition at line 42 of file tb_mem_test_flash.cpp.

Function Documentation

◆ main()

int main ( )

Definition at line 44 of file tb_mem_test_flash.cpp.

44  {
45 
46 
47  //-- SHELL / Role / Mem / Mp0 Interface
48  //---- Read Path (MM2S) ------------
49  stream<DmCmd> sROL_Shl_Mem_RdCmdP0("sROL_Shl_Mem_RdCmdP0");
50  stream<DmSts> sSHL_Rol_Mem_RdStsP0("sSHL_Rol_Mem_RdStsP0");
51  stream<Axis<512> > sSHL_Rol_Mem_ReadP0("sSHL_Rol_Mem_ReadP0");
52  //---- Write Path (S2MM) -----------
53  stream<DmCmd> sROL_Shl_Mem_WrCmdP0("sROL_Shl_Mem_WrCmdP0");
54  stream<DmSts> sSHL_Rol_Mem_WrStsP0("sSHL_Rol_Mem_WrStsP0");
55  stream<Axis<512> > sROL_Shl_Mem_WriteP0("sROL_Shl_Mem_WriteP0");
56  // ----- system reset ---
57  ap_uint<1> sys_reset;
58  // ----- MMIO ------
59  ap_uint<2> DIAG_CTRL_IN;
60  ap_uint<2> DIAG_STAT_OUT;
61  ap_uint<16> debug_out;
62 
63 
64  DmCmd dmCmd_MemCmdP0;
65  DmSts dmSts_MemWrStsP0;
66  DmSts dmSts_MemRdStsP0;
67  Axis<512> memP0;
68  ap_uint<64> currentMemPattern = 0;
69 
70  sys_reset = 1;
71 
72 #define DUT mem_test_flash_main(sys_reset, DIAG_CTRL_IN, &DIAG_STAT_OUT, &debug_out,sROL_Shl_Mem_RdCmdP0, sSHL_Rol_Mem_RdStsP0, sSHL_Rol_Mem_ReadP0,sROL_Shl_Mem_WrCmdP0, sSHL_Rol_Mem_WrStsP0, sROL_Shl_Mem_WriteP0);
73  DUT
74  sys_reset = 0;
75  DUT
76 
77  DIAG_CTRL_IN = 0b01;
78  DUT
79  assert(DIAG_STAT_OUT = 0b10);
80 
81 #define TEST_ITERATIONS (MEM_END_ADDR/CHECK_CHUNK_SIZE + 1)
82 
83  //phase ramp write
84 
85  currentMemPattern = 0;
86  for(int j = 0; j< TEST_ITERATIONS; j++)
87  {
88  DUT
89  sROL_Shl_Mem_WrCmdP0.read(dmCmd_MemCmdP0);
90  assert(dmCmd_MemCmdP0.btt == CHECK_CHUNK_SIZE);
91  assert(dmCmd_MemCmdP0.saddr == CHECK_CHUNK_SIZE*j);
92  assert(dmCmd_MemCmdP0.type == 1 && dmCmd_MemCmdP0.dsa == 0 && dmCmd_MemCmdP0.eof == 1 && dmCmd_MemCmdP0.drr == 0 && dmCmd_MemCmdP0.tag == 0x7);
93  //Pattern
94  for(int i = 0; i < TRANSFERS_PER_CHUNK; i++)
95  {
96  DUT
97  sROL_Shl_Mem_WriteP0.read(memP0);
98  //printf("tdata: 0x64%llX)\n", (uint512_t) ((ap_uint<512>) memP0.tdata));
99  //printf("tkeep: 0x%llX\n", (uint64_t) memP0.tkeep);
100  if(i < 63)
101  {
102  assert(memP0.tlast == 0);
103  } else {
104  assert(memP0.tlast == 1);
105  }
106  //assert(memP0.tkeep == (0xFF, 0xFF, 0xFF, 0xFF,0xFF, 0xFF, 0xFF, 0xFF) );
107  assert(memP0.tkeep == 0xffffffffffffffff);
108  currentMemPattern++;
109  assert(memP0.tdata == (ap_uint<512>) (currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern));
110 
111  sSHL_Rol_Mem_ReadP0.write(memP0);
112 
113  }
114  dmSts_MemWrStsP0.tag = 7;
115  dmSts_MemWrStsP0.okay = 1;
116  dmSts_MemWrStsP0.interr = 0;
117  dmSts_MemWrStsP0.slverr = 0;
118  dmSts_MemWrStsP0.decerr = 0;
119  sSHL_Rol_Mem_WrStsP0.write(dmSts_MemWrStsP0);
120  DUT
121  printf("debug_out: 0x%x\n", (uint16_t) debug_out);
122  assert((debug_out & 0xFF) == 0x0087);
123 
124  //idle State
125  DUT
126 
127  }
128 
129  printf("write done.\n");
130 
131  //phase ramp read
132 
133  for(int j = 0; j<TEST_ITERATIONS; j++)
134  {
135 
136  DUT
137  sROL_Shl_Mem_RdCmdP0.read(dmCmd_MemCmdP0);
138  assert(dmCmd_MemCmdP0.btt == CHECK_CHUNK_SIZE);
139  assert(dmCmd_MemCmdP0.saddr == CHECK_CHUNK_SIZE * j);
140  assert(dmCmd_MemCmdP0.type == 1 && dmCmd_MemCmdP0.dsa == 0 && dmCmd_MemCmdP0.eof == 1 && dmCmd_MemCmdP0.drr == 0 && dmCmd_MemCmdP0.tag == 0x7);
141 
142  for(int i = 0; i < TRANSFERS_PER_CHUNK; i++)
143  {
144  DUT
145  }
146 
147  dmSts_MemRdStsP0.tag = 7;
148  dmSts_MemRdStsP0.okay = 1;
149  dmSts_MemRdStsP0.interr = 0;
150  dmSts_MemRdStsP0.slverr = 0;
151  dmSts_MemRdStsP0.decerr = 0;
152  sSHL_Rol_Mem_RdStsP0.write(dmSts_MemWrStsP0);
153  DUT
154  printf("debug_out: 0x%x\n", (uint16_t) debug_out);
155  assert(debug_out == 0x8787);
156 
157  //idle State
158  DUT
159 
160  }
161 
162  printf("RAMD completed\n");
163  //idle State
164  DUT
165 
166  //phase stress
167  for(int j = 0; j<TEST_ITERATIONS; j++)
168  {
169 
170  DUT
171  sROL_Shl_Mem_WrCmdP0.read(dmCmd_MemCmdP0);
172  assert(dmCmd_MemCmdP0.btt == CHECK_CHUNK_SIZE);
173  assert(dmCmd_MemCmdP0.saddr == CHECK_CHUNK_SIZE*j);
174  assert(dmCmd_MemCmdP0.type == 1 && dmCmd_MemCmdP0.dsa == 0 && dmCmd_MemCmdP0.eof == 1 && dmCmd_MemCmdP0.drr == 0 && dmCmd_MemCmdP0.tag == 0x7);
175 
176  //Pattern
177  for(int i = 0; i < TRANSFERS_PER_CHUNK; i++)
178  {
179  DUT
180  sROL_Shl_Mem_WriteP0.read(memP0);
181  //printf("tdata: 0x64%llX)\n", (uint512_t) ((ap_uint<512>) memP0.tdata));
182  //printf("tkeep: 0x%llX\n", (uint64_t) memP0.tkeep);
183  if(i < 63)
184  {
185  assert(memP0.tlast == 0);
186  } else {
187  assert(memP0.tlast == 1);
188  }
189  //assert(memP0.tkeep == (0xFF, 0xFF, 0xFF, 0xFF,0xFF, 0xFF, 0xFF, 0xFF) );
190  assert(memP0.tkeep == 0xffffffffffffffff);
191  currentMemPattern = i+1;
192  assert(memP0.tdata == (ap_uint<512>) (currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern));
193 
194  sSHL_Rol_Mem_ReadP0.write(memP0);
195 
196  }
197 
198  dmSts_MemWrStsP0.tag = 7;
199  dmSts_MemWrStsP0.okay = 1;
200  dmSts_MemWrStsP0.interr = 0;
201  dmSts_MemWrStsP0.slverr = 0;
202  dmSts_MemWrStsP0.decerr = 0;
203  sSHL_Rol_Mem_WrStsP0.write(dmSts_MemWrStsP0);
204  DUT
205  printf("debug_out: 0x%x\n", (uint16_t) debug_out);
206  assert((debug_out & 0xFF) == 0x0087);
207 
208  DUT
209  sROL_Shl_Mem_RdCmdP0.read(dmCmd_MemCmdP0);
210  assert(dmCmd_MemCmdP0.btt == CHECK_CHUNK_SIZE);
211  assert(dmCmd_MemCmdP0.saddr == CHECK_CHUNK_SIZE * j);
212  assert(dmCmd_MemCmdP0.type == 1 && dmCmd_MemCmdP0.dsa == 0 && dmCmd_MemCmdP0.eof == 1 && dmCmd_MemCmdP0.drr == 0 && dmCmd_MemCmdP0.tag == 0x7);
213 
214  for(int i = 0; i < TRANSFERS_PER_CHUNK; i++)
215  {
216  DUT
217  }
218 
219  dmSts_MemRdStsP0.tag = 7;
220  dmSts_MemRdStsP0.okay = 1;
221  dmSts_MemRdStsP0.interr = 0;
222  dmSts_MemRdStsP0.slverr = 0;
223  dmSts_MemRdStsP0.decerr = 0;
224  sSHL_Rol_Mem_RdStsP0.write(dmSts_MemWrStsP0);
225  DUT
226  printf("debug_out: 0x%x\n", (uint16_t) debug_out);
227  assert(debug_out == 0x8787);
228 
229  printf("%d. Write & Read Pattern completed.\n", j);
230 
231 
232  DUT
233  sROL_Shl_Mem_WrCmdP0.read(dmCmd_MemCmdP0);
234  assert(dmCmd_MemCmdP0.btt == CHECK_CHUNK_SIZE);
235  assert(dmCmd_MemCmdP0.saddr == CHECK_CHUNK_SIZE*j);
236  assert(dmCmd_MemCmdP0.type == 1 && dmCmd_MemCmdP0.dsa == 0 && dmCmd_MemCmdP0.eof == 1 && dmCmd_MemCmdP0.drr == 0 && dmCmd_MemCmdP0.tag == 0x7);
237 
238 
239  //Antipattern
240  for(int i = 0; i < TRANSFERS_PER_CHUNK; i++)
241  {
242  DUT
243  sROL_Shl_Mem_WriteP0.read(memP0);
244  //printf("tdata: 0x64%llX)\n", (uint512_t) ((ap_uint<512>) memP0.tdata));
245  //printf("tkeep: 0x%llX\n", (uint64_t) memP0.tkeep);
246  if(i < 63)
247  {
248  assert(memP0.tlast == 0);
249  } else {
250  assert(memP0.tlast == 1);
251  }
252  //assert(memP0.tkeep == (0xFF, 0xFF, 0xFF, 0xFF,0xFF, 0xFF, 0xFF, 0xFF) );
253  assert(memP0.tkeep == 0xffffffffffffffff);
254  currentMemPattern = ~(i+1);
255  assert(memP0.tdata == (ap_uint<512>) (currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern));
256 
257  sSHL_Rol_Mem_ReadP0.write(memP0);
258 
259  }
260 
261  dmSts_MemWrStsP0.tag = 7;
262  dmSts_MemWrStsP0.okay = 1;
263  dmSts_MemWrStsP0.interr = 0;
264  dmSts_MemWrStsP0.slverr = 0;
265  dmSts_MemWrStsP0.decerr = 0;
266  sSHL_Rol_Mem_WrStsP0.write(dmSts_MemWrStsP0);
267  DUT
268  printf("debug_out: 0x%x\n", (uint16_t) debug_out);
269  assert(debug_out == 0x8787);
270 
271  DUT
272  sROL_Shl_Mem_RdCmdP0.read(dmCmd_MemCmdP0);
273  assert(dmCmd_MemCmdP0.btt == CHECK_CHUNK_SIZE);
274  assert(dmCmd_MemCmdP0.saddr == CHECK_CHUNK_SIZE * j);
275  assert(dmCmd_MemCmdP0.type == 1 && dmCmd_MemCmdP0.dsa == 0 && dmCmd_MemCmdP0.eof == 1 && dmCmd_MemCmdP0.drr == 0 && dmCmd_MemCmdP0.tag == 0x7);
276 
277  for(int i = 0; i < TRANSFERS_PER_CHUNK; i++)
278  {
279  DUT
280  }
281 
282  dmSts_MemRdStsP0.tag = 7;
283  dmSts_MemRdStsP0.okay = 1;
284  dmSts_MemRdStsP0.interr = 0;
285  dmSts_MemRdStsP0.slverr = 0;
286  dmSts_MemRdStsP0.decerr = 0;
287  sSHL_Rol_Mem_RdStsP0.write(dmSts_MemWrStsP0);
288  DUT
289  printf("debug_out: 0x%x\n", (uint16_t) debug_out);
290  assert(debug_out == 0x8787);
291 
292  printf("%d. Write & Read Antipattern completed.\n", j);
293 
294  //Idle State
295  DUT
296 
297  }
298 
299 
300  printf("------ DONE ------\n");
301  return 0;
302 }
TEST_ITERATIONS
#define TEST_ITERATIONS
DUT
#define DUT
currentMemPattern
ap_uint< 64 > currentMemPattern
Definition: mem_test_flash.cpp:30
DmCmd::saddr
ap_uint< 40 > saddr
Definition: memory_utils.hpp:50
DmCmd::drr
ap_uint< 1 > drr
Definition: memory_utils.hpp:49
DmCmd::eof
ap_uint< 1 > eof
Definition: memory_utils.hpp:48
DmCmd::tag
ap_uint< 4 > tag
Definition: memory_utils.hpp:51
DmCmd::dsa
ap_uint< 6 > dsa
Definition: memory_utils.hpp:47
DmCmd::btt
ap_uint< 23 > btt
Definition: mem.hpp:85
DmCmd::type
ap_uint< 1 > type
Definition: memory_utils.hpp:46
DmSts::okay
ap_uint< 1 > okay
Definition: memory_utils.hpp:84
DmSts::decerr
ap_uint< 1 > decerr
Definition: memory_utils.hpp:82
DmSts::slverr
ap_uint< 1 > slverr
Definition: memory_utils.hpp:83
DmSts::tag
ap_uint< 4 > tag
Definition: memory_utils.hpp:80
DmSts::interr
ap_uint< 1 > interr
Definition: memory_utils.hpp:81
CHECK_CHUNK_SIZE
#define CHECK_CHUNK_SIZE
This define configures tha AXI burst size of DDRM memory-mapped interfaces AXI4 allows 4KiB,...
Definition: harris.hpp:131
TRANSFERS_PER_CHUNK
#define TRANSFERS_PER_CHUNK
Definition: harris.hpp:133
sSHL_Rol_Mem_RdStsP0
stream< DmSts > sSHL_Rol_Mem_RdStsP0("sSHL_Rol_Mem_RdStsP0")
sSHL_Rol_Mem_ReadP0
stream< Axis< 512 > > sSHL_Rol_Mem_ReadP0("sSHL_Rol_Mem_ReadP0")
sROL_Shl_Mem_WriteP0
stream< Axis< 512 > > sROL_Shl_Mem_WriteP0("sROL_Shl_Mem_WriteP0")
sROL_Shl_Mem_WrCmdP0
stream< DmCmd > sROL_Shl_Mem_WrCmdP0("sROL_Shl_Mem_WrCmdP0")
sROL_Shl_Mem_RdCmdP0
stream< DmCmd > sROL_Shl_Mem_RdCmdP0("sROL_Shl_Mem_RdCmdP0")
sSHL_Rol_Mem_WrStsP0
stream< DmSts > sSHL_Rol_Mem_WrStsP0("sSHL_Rol_Mem_WrStsP0")
Axis::tkeep
ap_uint<(D+7)/8 > tkeep
Definition: axi_utils.hpp:49
Axis::tlast
ap_uint< 1 > tlast
Definition: axi_utils.hpp:50
Axis::tdata
ap_uint< D > tdata
Definition: axi_utils.hpp:48
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