cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
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Harris Vivado HLS
cF » cFp » cFp_Zoo » cF Vitis Vision » Harris

This is a subgroup of Harris accelerated function with only synthesizable (Vivado HLS) functions/classes. More...

Collaboration diagram for Harris Vivado HLS:

Files

file  harris.hpp
 The Role for a Harris Example application (UDP or TCP)
 
file  xf_config_params.h
 The Harris IP configuration header.
 
file  harris.cpp
 The Role for a Harris Example application (UDP or TCP)
 
file  xf_harris_accel.cpp
 The Harris top-level.
 

Classes

struct  Axis< D >
 

Macros

#define ROLE_IS_HARRIS
 
#define WAIT_FOR_META   0
 
#define WAIT_FOR_STREAM_PAIR   1
 
#define PROCESSING_PACKET   2
 
#define LOAD_IN_STREAM   3
 
#define HARRIS_RETURN_RESULTS   4
 
#define HARRIS_RETURN_RESULTS_ABSORB_DDR_LAT   5
 
#define HARRIS_RETURN_RESULTS_UNPACK   6
 
#define HARRIS_RETURN_RESULTS_FWD   7
 
#define WAIT_FOR_TX   8
 
#define FSM_IDLE   9
 
#define FSM_CHK_SKIP   10
 
#define FSM_CHK_PROC_BYTES   11
 
#define FSM_CHK_WRT_CHNK_TO_DDR_PND   12
 
#define FSM_WR_PAT_CMD   13
 
#define FSM_WR_PAT_LOAD   14
 
#define FSM_WR_PAT_DATA   15
 
#define FSM_WR_PAT_STS_A   16
 
#define FSM_WR_PAT_STS_B   17
 
#define FSM_WR_PAT_STS_C   18
 
#define PacketFsmType   uint8_t
 
#define FSM_WRITE_NEW_DATA   0
 
#define FSM_DONE   1
 
#define PortFsmType   uint8_t
 
#define DEFAULT_TX_PORT   2718
 
#define DEFAULT_RX_PORT   2718
 
#define PORTS_OPENED   0x1F
 
#define Data_t_in   ap_axiu<INPUT_PTR_WIDTH, 0, 0, 0>
 
#define Data_t_out   ap_axiu<OUTPUT_PTR_WIDTH, 0, 0, 0>
 
#define MAX_NB_OF_ELMT_READ   16
 
#define MAX_NB_OF_WORDS_READ   (MAX_NB_OF_ELMT_READ*sizeof(mat_elmt_t)/BPERDW)
 
#define MAX_NB_OF_ELMT_PERDW   (BPERDW/sizeof(mat_elmt_t))
 
#define MEMDW_512   512
 
#define BPERMDW_512   (MEMDW_512/8)
 
#define KWPERMDW_512   (BPERMDW_512/sizeof(IN_TYPE))
 
#define TOTMEMDW_512   (1 + (IMGSIZE - 1) / BPERMDW_512)
 
#define CHECK_CHUNK_SIZE   0x400
 This define configures tha AXI burst size of DDRM memory-mapped interfaces AXI4 allows 4KiB, but Role's AXI interconnect is configured at max 1KiB 0x40->64, 0x400->1024B(1KiB), 0x1000->4KiB. More...
 
#define BYTE_PER_MEM_WORD   BPERMDW_512
 
#define TRANSFERS_PER_CHUNK   (CHECK_CHUNK_SIZE/BYTE_PER_MEM_WORD)
 
#define TRANSFERS_PER_CHUNK_DIVEND   (TOTMEMDW_512-(TOTMEMDW_512/TRANSFERS_PER_CHUNK)*TRANSFERS_PER_CHUNK)
 
#define fsmStateDDRdef   uint8_t
 
#define CYCLES_UNTIL_TIMEOUT   0x0100
 
#define TYPICAL_DDR_LATENCY   4
 
#define DDR_LATENCY   (52/4)
 
#define EXTRA_DDR_LATENCY_DUE_II   (64 + 8)
 
#define RO   0
 
#define NO   1
 
#define FILTER_WIDTH   3
 
#define BLOCK_WIDTH   3
 
#define NMS_RADIUS   1
 
#define MAXCORNERS   1024
 
#define XF_USE_URAM   false
 

Typedefs

typedef uint8_t mat_elmt_t
 
typedef ap_uint< 512 > membus_512_t
 
typedef membus_512_t membus_t
 

Enumerations

enum  EchoCtrl {
  ECHO_PATH_THRU = 0 , ECHO_STORE_FWD = 1 , ECHO_OFF = 2 , ECHO_PATH_THRU = 0 ,
  ECHO_STORE_FWD = 1 , ECHO_OFF = 2 , ECHO_PATH_THRU = 0 , ECHO_STORE_FWD = 1 ,
  ECHO_OFF = 2 , ECHO_PATH_THRU = 0 , ECHO_STORE_FWD = 1 , ECHO_OFF = 2 ,
  ECHO_PATH_THRU = 0 , ECHO_STORE_FWD = 1 , ECHO_OFF = 2 , ECHO_PATH_THRU = 0 ,
  ECHO_STORE_FWD = 1 , ECHO_OFF = 2 , ECHO_PATH_THRU = 0 , ECHO_STORE_FWD = 1 ,
  ECHO_OFF = 2 , ECHO_STORE_FWD = 0 , ECHO_PATH_THRU = 1 , ECHO_CTRL_DISABLED = 0 ,
  ECHO_PATH_THRU = 1 , ECHO_STORE_FWD = 2 , ECHO_OFF = 3
}
 

Functions

void harris (ap_uint< 32 > *pi_rank, ap_uint< 32 > *pi_size, stream< NetworkWord > &siSHL_This_Data, stream< NetworkWord > &soTHIS_Shl_Data, stream< NetworkMetaStream > &siNrc_meta, stream< NetworkMetaStream > &soNrc_meta, ap_uint< 32 > *po_rx_ports)
 Main process of the Harris Application directives. More...
 
void pPortAndDestionation (ap_uint< 32 > *pi_rank, ap_uint< 32 > *pi_size, stream< NodeId > &sDstNode_sig, ap_uint< 32 > *po_rx_ports)
 
void storeWordToArray (uint64_t input, ap_uint< 8 > img[16 *16/((64/8))], unsigned int *processed_word, unsigned int *image_loaded)
 Store a net word to local memory. More...
 
void storeWordToAxiStream (NetworkWord word, stream< ap_uint< 8 >> &img_in_axi_stream, unsigned int *processed_word_rx, unsigned int *processed_bytes_rx, stream< bool > &sImageLoaded)
 Store a net word to a local AXI stream. More...
 
void pRXPath (stream< NetworkWord > &siSHL_This_Data, stream< NetworkMetaStream > &siNrc_meta, stream< NetworkMetaStream > &sRxtoTx_Meta, stream< ap_uint< 8 >> &img_in_axi_stream, NetworkMetaStream meta_tmp, unsigned int *processed_word_rx, unsigned int *processed_bytes_rx, stream< bool > &sImageLoaded)
 Receive Path - From SHELL to THIS. More...
 
void pProcPath (stream< NetworkWord > &sRxpToTxp_Data, stream< ap_uint< 8 >> &img_in_axi_stream, stream< ap_uint< 64 >> &img_out_axi_stream, stream< bool > &sImageLoaded)
 Processing Path - Main processing FSM for Vitis kernels. More...
 
void pTXPath (stream< NodeId > &sDstNode_sig, stream< NetworkWord > &soTHIS_Shl_Data, stream< NetworkMetaStream > &soNrc_meta, stream< NetworkWord > &sRxpToTxp_Data, stream< NetworkMetaStream > &sRxtoTx_Meta, unsigned int *processed_word_tx, ap_uint< 32 > *pi_rank, ap_uint< 32 > *pi_size)
 Transmit Path - From THIS to SHELL. More...
 
void harris_accel (xf::cv::Mat< XF_8UC1, 16, 16, XF_NPPC1 > &_src, xf::cv::Mat< XF_8UC1, 16, 16, XF_NPPC1 > &_dst, unsigned short Thresh, unsigned short k)
 Top-level accelerated function of the Harris Application with xf::cv I/F. More...
 
void cornerHarrisAccelArray (ap_uint< 8 > *img_inp, ap_uint< 64 > *img_out, int rows, int cols, int threshold, int k)
 Top-level accelerated function of the Harris Application with array I/F. More...
 
void cornerHarrisAccelStream (hls::stream< ap_uint< 8 >> &img_in_axi_stream, hls::stream< ap_uint< 64 >> &img_out_axi_stream, int rows, int cols, int threshold, int k)
 Top-level accelerated function of the Harris Application with array I/F. More...
 
void cornerHarrisAccelMem (membus_t *img_inp, membus_t *img_out, int rows, int cols, int threshold, int k)
 Top-level accelerated function of the Harris Application with array I/F. More...
 

Variables

uint8_t enqueueFSM = 0
 
uint8_t dequeueFSM = 0
 
uint8_t HarrisFSM = 0
 
uint8_t fsmStateDDR = 9
 
unsigned int sRxpToTxp_DataCounter = 0
 

Detailed Description

This is a subgroup of Harris accelerated function with only synthesizable (Vivado HLS) functions/classes.

This is a subgroup of Harris accelerated function with only synthesizable (HLS) functions/classes.

Macro Definition Documentation

◆ BLOCK_WIDTH

#define BLOCK_WIDTH   3

Definition at line 60 of file xf_config_params.h.

◆ BPERMDW_512

#define BPERMDW_512   (MEMDW_512/8)

Definition at line 120 of file harris.hpp.

◆ BYTE_PER_MEM_WORD

#define BYTE_PER_MEM_WORD   BPERMDW_512

Definition at line 132 of file harris.hpp.

◆ CHECK_CHUNK_SIZE

#define CHECK_CHUNK_SIZE   0x400

This define configures tha AXI burst size of DDRM memory-mapped interfaces AXI4 allows 4KiB, but Role's AXI interconnect is configured at max 1KiB 0x40->64, 0x400->1024B(1KiB), 0x1000->4KiB.

Definition at line 131 of file harris.hpp.

◆ CYCLES_UNTIL_TIMEOUT

#define CYCLES_UNTIL_TIMEOUT   0x0100

Definition at line 147 of file harris.hpp.

◆ Data_t_in

#define Data_t_in   ap_axiu<INPUT_PTR_WIDTH, 0, 0, 0>

Definition at line 104 of file harris.hpp.

◆ Data_t_out

#define Data_t_out   ap_axiu<OUTPUT_PTR_WIDTH, 0, 0, 0>

Definition at line 105 of file harris.hpp.

◆ DDR_LATENCY

#define DDR_LATENCY   (52/4)

Definition at line 151 of file harris.hpp.

◆ DEFAULT_RX_PORT

#define DEFAULT_RX_PORT   2718

Definition at line 97 of file harris.hpp.

◆ DEFAULT_TX_PORT

#define DEFAULT_TX_PORT   2718

Definition at line 96 of file harris.hpp.

◆ EXTRA_DDR_LATENCY_DUE_II

#define EXTRA_DDR_LATENCY_DUE_II   (64 + 8)

Definition at line 152 of file harris.hpp.

◆ FILTER_WIDTH

#define FILTER_WIDTH   3

Definition at line 59 of file xf_config_params.h.

◆ FSM_CHK_PROC_BYTES

#define FSM_CHK_PROC_BYTES   11

Definition at line 81 of file harris.hpp.

◆ FSM_CHK_SKIP

#define FSM_CHK_SKIP   10

Definition at line 80 of file harris.hpp.

◆ FSM_CHK_WRT_CHNK_TO_DDR_PND

#define FSM_CHK_WRT_CHNK_TO_DDR_PND   12

Definition at line 82 of file harris.hpp.

◆ FSM_DONE

#define FSM_DONE   1

Definition at line 93 of file harris.hpp.

◆ FSM_IDLE

#define FSM_IDLE   9

Definition at line 79 of file harris.hpp.

◆ FSM_WR_PAT_CMD

#define FSM_WR_PAT_CMD   13

Definition at line 83 of file harris.hpp.

◆ FSM_WR_PAT_DATA

#define FSM_WR_PAT_DATA   15

Definition at line 85 of file harris.hpp.

◆ FSM_WR_PAT_LOAD

#define FSM_WR_PAT_LOAD   14

Definition at line 84 of file harris.hpp.

◆ FSM_WR_PAT_STS_A

#define FSM_WR_PAT_STS_A   16

Definition at line 86 of file harris.hpp.

◆ FSM_WR_PAT_STS_B

#define FSM_WR_PAT_STS_B   17

Definition at line 87 of file harris.hpp.

◆ FSM_WR_PAT_STS_C

#define FSM_WR_PAT_STS_C   18

Definition at line 88 of file harris.hpp.

◆ FSM_WRITE_NEW_DATA

#define FSM_WRITE_NEW_DATA   0

Definition at line 92 of file harris.hpp.

◆ fsmStateDDRdef

#define fsmStateDDRdef   uint8_t

Definition at line 144 of file harris.hpp.

◆ HARRIS_RETURN_RESULTS

#define HARRIS_RETURN_RESULTS   4

Definition at line 74 of file harris.hpp.

◆ HARRIS_RETURN_RESULTS_ABSORB_DDR_LAT

#define HARRIS_RETURN_RESULTS_ABSORB_DDR_LAT   5

Definition at line 75 of file harris.hpp.

◆ HARRIS_RETURN_RESULTS_FWD

#define HARRIS_RETURN_RESULTS_FWD   7

Definition at line 77 of file harris.hpp.

◆ HARRIS_RETURN_RESULTS_UNPACK

#define HARRIS_RETURN_RESULTS_UNPACK   6

Definition at line 76 of file harris.hpp.

◆ KWPERMDW_512

#define KWPERMDW_512   (BPERMDW_512/sizeof(IN_TYPE))

Definition at line 121 of file harris.hpp.

◆ LOAD_IN_STREAM

#define LOAD_IN_STREAM   3

Definition at line 73 of file harris.hpp.

◆ MAX_NB_OF_ELMT_PERDW

#define MAX_NB_OF_ELMT_PERDW   (BPERDW/sizeof(mat_elmt_t))

Definition at line 112 of file harris.hpp.

◆ MAX_NB_OF_ELMT_READ

#define MAX_NB_OF_ELMT_READ   16

Definition at line 108 of file harris.hpp.

◆ MAX_NB_OF_WORDS_READ

#define MAX_NB_OF_WORDS_READ   (MAX_NB_OF_ELMT_READ*sizeof(mat_elmt_t)/BPERDW)

Definition at line 111 of file harris.hpp.

◆ MAXCORNERS

#define MAXCORNERS   1024

Definition at line 63 of file xf_config_params.h.

◆ MEMDW_512

#define MEMDW_512   512

Definition at line 119 of file harris.hpp.

◆ NMS_RADIUS

#define NMS_RADIUS   1

Definition at line 61 of file xf_config_params.h.

◆ NO

#define NO   1

Definition at line 57 of file xf_config_params.h.

◆ PacketFsmType

#define PacketFsmType   uint8_t

Definition at line 89 of file harris.hpp.

◆ PortFsmType

#define PortFsmType   uint8_t

Definition at line 94 of file harris.hpp.

◆ PORTS_OPENED

#define PORTS_OPENED   0x1F

Definition at line 102 of file harris.hpp.

◆ PROCESSING_PACKET

#define PROCESSING_PACKET   2

Definition at line 72 of file harris.hpp.

◆ RO

#define RO   0

Definition at line 56 of file xf_config_params.h.

◆ ROLE_IS_HARRIS

#define ROLE_IS_HARRIS

Definition at line 67 of file harris.hpp.

◆ TOTMEMDW_512

#define TOTMEMDW_512   (1 + (IMGSIZE - 1) / BPERMDW_512)

Definition at line 124 of file harris.hpp.

◆ TRANSFERS_PER_CHUNK

#define TRANSFERS_PER_CHUNK   (CHECK_CHUNK_SIZE/BYTE_PER_MEM_WORD)

Definition at line 133 of file harris.hpp.

◆ TRANSFERS_PER_CHUNK_DIVEND

#define TRANSFERS_PER_CHUNK_DIVEND   (TOTMEMDW_512-(TOTMEMDW_512/TRANSFERS_PER_CHUNK)*TRANSFERS_PER_CHUNK)

Definition at line 134 of file harris.hpp.

◆ TYPICAL_DDR_LATENCY

#define TYPICAL_DDR_LATENCY   4

Definition at line 148 of file harris.hpp.

◆ WAIT_FOR_META

#define WAIT_FOR_META   0

Definition at line 70 of file harris.hpp.

◆ WAIT_FOR_STREAM_PAIR

#define WAIT_FOR_STREAM_PAIR   1

Definition at line 71 of file harris.hpp.

◆ WAIT_FOR_TX

#define WAIT_FOR_TX   8

Definition at line 78 of file harris.hpp.

◆ XF_USE_URAM

#define XF_USE_URAM   false

Definition at line 65 of file xf_config_params.h.

Typedef Documentation

◆ mat_elmt_t

typedef uint8_t mat_elmt_t

Definition at line 109 of file harris.hpp.

◆ membus_512_t

typedef ap_uint< 512 > membus_512_t

Definition at line 122 of file harris.hpp.

◆ membus_t

typedef membus_512_t membus_t

Definition at line 123 of file harris.hpp.

Enumeration Type Documentation

◆ EchoCtrl

enum EchoCtrl

SHELL/MMIO/EchoCtrl - Config Register

Enumerator
ECHO_PATH_THRU 
ECHO_STORE_FWD 
ECHO_OFF 
ECHO_PATH_THRU 
ECHO_STORE_FWD 
ECHO_OFF 
ECHO_PATH_THRU 
ECHO_STORE_FWD 
ECHO_OFF 
ECHO_PATH_THRU 
ECHO_STORE_FWD 
ECHO_OFF 
ECHO_PATH_THRU 
ECHO_STORE_FWD 
ECHO_OFF 
ECHO_PATH_THRU 
ECHO_STORE_FWD 
ECHO_OFF 
ECHO_PATH_THRU 
ECHO_STORE_FWD 
ECHO_OFF 
ECHO_STORE_FWD 
ECHO_PATH_THRU 
ECHO_CTRL_DISABLED 
ECHO_PATH_THRU 
ECHO_STORE_FWD 
ECHO_OFF 

Definition at line 60 of file harris.hpp.

60  {
61  ECHO_PATH_THRU = 0,
62  ECHO_STORE_FWD = 1,
63  ECHO_OFF = 2
64 };
ECHO_STORE_FWD
@ ECHO_STORE_FWD
Definition: harris.hpp:62
ECHO_OFF
@ ECHO_OFF
Definition: harris.hpp:63
ECHO_PATH_THRU
@ ECHO_PATH_THRU
Definition: harris.hpp:61

Function Documentation

◆ cornerHarrisAccelArray()

void cornerHarrisAccelArray ( ap_uint< 8 > *  img_inp,
ap_uint< 64 > *  img_out,
int  rows,
int  cols,
int  threshold,
int  k 
)

Top-level accelerated function of the Harris Application with array I/F.

Returns
Nothing.

Definition at line 58 of file xf_harris_accel.cpp.

59  {
60 // clang-format off
61 /* #pragma HLS INTERFACE m_axi port=img_inp offset=slave bundle=gmem1
62  #pragma HLS INTERFACE m_axi port=img_out offset=slave bundle=gmem2
63 
64  #pragma HLS INTERFACE s_axilite port=rows bundle=control
65  #pragma HLS INTERFACE s_axilite port=cols bundle=control
66  #pragma HLS INTERFACE s_axilite port=threshold bundle=control
67  #pragma HLS INTERFACE s_axilite port=k bundle=control
68  #pragma HLS INTERFACE s_axilite port=return bundle=control
69  // clang-format on
70 */
71  const int pROWS = HEIGHT;
72  const int pCOLS = WIDTH;
73  const int pNPC1 = NPIX;
74 
75  xf::cv::Mat<XF_8UC1, HEIGHT, WIDTH, NPIX> in_mat(rows, cols);
76 // clang-format off
77  #pragma HLS stream variable=in_mat.data depth=2
78  // clang-format on
79 
80  xf::cv::Mat<XF_8UC1, HEIGHT, WIDTH, NPIX> out_mat(rows, cols);
81 // clang-format off
82  #pragma HLS stream variable=out_mat.data depth=2
83 // clang-format on
84 
85 // clang-format off
86  #pragma HLS DATAFLOW
87  // clang-format on
88  xf::cv::Array2xfMat<INPUT_PTR_WIDTH, XF_8UC1, HEIGHT, WIDTH, NPIX>(img_inp, in_mat);
89  xf::cv::cornerHarris<FILTER_WIDTH, BLOCK_WIDTH, NMS_RADIUS, XF_8UC1, HEIGHT, WIDTH, NPIX, XF_USE_URAM>(
90  in_mat, out_mat, threshold, k);
91  xf::cv::xfMat2Array<OUTPUT_PTR_WIDTH, XF_8UC1, HEIGHT, WIDTH, NPIX>(out_mat, img_out);
92 }
WIDTH
#define WIDTH
Definition: xf_gammacorrection_config.h:64
NPIX
#define NPIX
Definition: xf_gammacorrection_config.h:61
HEIGHT
#define HEIGHT
Definition: xf_gammacorrection_config.h:65
test_harris_standalone.rows
rows
Definition: test_harris_standalone.py:167
test_harris_standalone.cols
cols
Definition: test_harris_standalone.py:167
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◆ cornerHarrisAccelMem()

void cornerHarrisAccelMem ( membus_t *  img_inp,
membus_t *  img_out,
int  rows,
int  cols,
int  threshold,
int  k 
)

Top-level accelerated function of the Harris Application with array I/F.

Returns
Nothing.

Definition at line 216 of file xf_harris_accel.cpp.

218  {
219  // clang-format on
220  #pragma HLS INLINE off
221 
222  const int pROWS = HEIGHT;
223  const int pCOLS = WIDTH;
224  const int pNPC1 = NPIX;
225 
226  xf::cv::Mat<IN_TYPE, HEIGHT, WIDTH, NPIX> in_mat(rows, cols);
227  // clang-format off
228  #pragma HLS stream variable=in_mat.data depth=2
229  // clang-format on
230 
231  #ifndef FAKE_Harris
232  xf::cv::Mat<OUT_TYPE, HEIGHT, WIDTH, NPIX> out_mat(rows, cols);
233  // clang-format off
234  #pragma HLS stream variable=out_mat.data depth=2
235  // clang-format on
236  #endif
237 
238  // clang-format off
239  #pragma HLS DATAFLOW
240  // clang-format on
241 
242  // Feed a cv matrix from ddr memory
243  xf::cv::Array2xfMat<MEMDW_512, XF_8UC1, HEIGHT, WIDTH, NPIX>(img_inp, in_mat);
244 
245  #ifdef FAKE_Harris
246 
247  // Feed ddr memory from a cv matrix
248  xf::cv::xfMat2Array<MEMDW_512, XF_8UC1, HEIGHT, WIDTH, NPIX>(in_mat, img_out);
249  #else
250 
251  xf::cv::cornerHarris<FILTER_WIDTH, BLOCK_WIDTH, NMS_RADIUS, IN_TYPE, HEIGHT, WIDTH, NPIX, XF_USE_URAM>(
252  in_mat, out_mat, threshold, k);
253 
254  // Feed ddr memory from a cv matrix
255  xf::cv::xfMat2Array<MEMDW_512, XF_8UC1, HEIGHT, WIDTH, NPIX>(out_mat, img_out);
256 
257  #endif
258 
259 
260 }
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◆ cornerHarrisAccelStream()

void cornerHarrisAccelStream ( hls::stream< ap_uint< 8 >> &  img_in_axi_stream,
hls::stream< ap_uint< 64 >> &  img_out_axi_stream,
int  rows,
int  cols,
int  threshold,
int  k 
)

Top-level accelerated function of the Harris Application with array I/F.

Returns
Nothing.

Definition at line 106 of file xf_harris_accel.cpp.

111  {
112  // clang-format on
113  #pragma HLS INLINE off
114 
115  const int pROWS = HEIGHT;
116  const int pCOLS = WIDTH;
117  const int pNPC1 = NPIX;
118 
119  xf::cv::Mat<IN_TYPE, HEIGHT, WIDTH, NPIX> in_mat(rows, cols);
120  // clang-format off
121  #pragma HLS stream variable=in_mat.data depth=2
122  // clang-format on
123 
124  xf::cv::Mat<OUT_TYPE, HEIGHT, WIDTH, NPIX> out_mat(rows, cols);
125  // clang-format off
126  #pragma HLS stream variable=out_mat.data depth=2
127  // clang-format on
128 
129  // clang-format off
130  #pragma HLS DATAFLOW
131  // clang-format on
132 
133  accel_utils accel_utils_obj;
134 
135  int dstMat_cols_align_npc = ((in_mat.cols + (NPIX - 1)) >> XF_BITSHIFT(NPIX)) << XF_BITSHIFT(NPIX);
136 
137  accel_utils_obj.hlsStrm2xfMat<INPUT_PTR_WIDTH, IN_TYPE, HEIGHT, WIDTH, NPIX, (HEIGHT * WIDTH) / NPIX>(img_in_axi_stream, in_mat, dstMat_cols_align_npc);
138 
139  //xf::cv::axiStrm2xfMat<INPUT_PTR_WIDTH, IN_TYPE, HEIGHT, WIDTH, NPIX>(
140  // img_in_axi_stream, in_mat);
141 
142  xf::cv::cornerHarris<FILTER_WIDTH, BLOCK_WIDTH, NMS_RADIUS, IN_TYPE, HEIGHT, WIDTH, NPIX, XF_USE_URAM>(
143  in_mat, out_mat, threshold, k);
144 
145  //xf::cv::xfMat2axiStrm<OUTPUT_PTR_WIDTH, OUT_TYPE, HEIGHT, WIDTH, NPIX>(
146  // out_mat, img_out_axi_stream);
147 
148  int srcMat_cols_align_npc = ((out_mat.cols + (NPIX - 1)) >> XF_BITSHIFT(NPIX)) << XF_BITSHIFT(NPIX);
149 
150  accel_utils_obj.xfMat2hlsStrm<OUTPUT_PTR_WIDTH, OUT_TYPE, HEIGHT, WIDTH, NPIX, HEIGHT*((WIDTH + NPIX - 1) / NPIX)>(out_mat, img_out_axi_stream,
151  srcMat_cols_align_npc);
152 
153 
154 }
OUT_TYPE
#define OUT_TYPE
Definition: xf_gammacorrection_config.h:72
IN_TYPE
#define IN_TYPE
Definition: xf_gammacorrection_config.h:71
INPUT_PTR_WIDTH
#define INPUT_PTR_WIDTH
Definition: mceuropeanengine.hpp:71
OUTPUT_PTR_WIDTH
#define OUTPUT_PTR_WIDTH
Definition: mceuropeanengine.hpp:75
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◆ harris()

void harris ( ap_uint< 32 > *  pi_rank,
ap_uint< 32 > *  pi_size,
stream< NetworkWord > &  siSHL_This_Data,
stream< NetworkWord > &  soTHIS_Shl_Data,
stream< NetworkMetaStream > &  siNrc_meta,
stream< NetworkMetaStream > &  soNrc_meta,
ap_uint< 32 > *  po_rx_ports 
)

Main process of the Harris Application directives.

Deprecated:
This functions is using deprecated AXI stream interface
Returns
Nothing.

Definition at line 918 of file harris.cpp.

951 {
952 
953 
954 //-- DIRECTIVES FOR THE BLOCK ---------------------------------------------
955 //#pragma HLS INTERFACE ap_ctrl_none port=return
956 
957 //#pragma HLS INTERFACE ap_stable port=piSHL_This_MmioEchoCtrl
958 
959 #pragma HLS INTERFACE axis register both port=siSHL_This_Data
960 #pragma HLS INTERFACE axis register both port=soTHIS_Shl_Data
961 
962 #pragma HLS INTERFACE axis register both port=siNrc_meta
963 #pragma HLS INTERFACE axis register both port=soNrc_meta
964 
965 #pragma HLS INTERFACE ap_ovld register port=po_rx_ports name=poROL_NRC_Rx_ports
966 
967 #if HLS_VERSION < 20211
968 #pragma HLS INTERFACE ap_stable register port=pi_rank name=piFMC_ROL_rank
969 #pragma HLS INTERFACE ap_stable register port=pi_size name=piFMC_ROL_size
970 #elif HLS_VERSION >= 20211
971  #pragma HLS stable variable=pi_rank
972  #pragma HLS stable variable=pi_size
973 #else
974  printf("ERROR: Invalid HLS_VERSION=%s\n", HLS_VERSION);
975  exit(-1);
976 #endif
977 
978 #ifdef ENABLE_DDR
979 
980 // Bundling: SHELL / Role / Mem / Mp0 / Read Interface
981 // #pragma HLS INTERFACE axis register both port=soMemRdCmdP0
982 // #pragma HLS INTERFACE axis register both port=siMemRdStsP0
983 // #pragma HLS INTERFACE axis register both port=siMemReadP0
984 
985 // #pragma HLS DATA_PACK variable=soMemRdCmdP0 instance=soMemRdCmdP0
986 // #pragma HLS DATA_PACK variable=siMemRdStsP0 instance=siMemRdStsP0
987 
988 // Bundling: SHELL / Role / Mem / Mp0 / Write Interface
989 #pragma HLS INTERFACE axis register both port=soMemWrCmdP0
990 #pragma HLS INTERFACE axis register both port=siMemWrStsP0
991 #pragma HLS INTERFACE axis register both port=soMemWriteP0
992 
993 #if HLS_VERSION <= 20201
994 #pragma HLS DATA_PACK variable=soMemWrCmdP0 instance=soMemWrCmdP0
995 #pragma HLS DATA_PACK variable=siMemWrStsP0 instance=siMemWrStsP0
996 #elif HLS_VERSION >= 20211
997 #pragma HLS aggregate variable=soMemWrCmdP0 compact=bit
998 #pragma HLS aggregate variable=siMemWrStsP0 compact=bit
999 #else
1000  printf("ERROR: Invalid HLS_VERSION=%s\n", HLS_VERSION);
1001  exit(-1);
1002 #endif
1003 
1004 const unsigned int ddr_mem_depth = TOTMEMDW_512;
1005 const unsigned int ddr_latency = DDR_LATENCY;
1006 
1007 
1008 // Max burst size is 1KB, thus with 512bit bus we get 16 burst transactions
1009 const unsigned int max_axi_rw_burst_length = 16;
1010 
1011 // Mapping LCL_MEM0 interface to moMEM_Mp1 channel
1012 #pragma HLS INTERFACE m_axi depth=ddr_mem_depth port=lcl_mem0 bundle=moMEM_Mp1\
1013  max_read_burst_length=max_axi_rw_burst_length max_write_burst_length=max_axi_rw_burst_length offset=direct \
1014  num_read_outstanding=16 num_write_outstanding=16 latency=ddr_latency
1015 
1016 // Mapping LCL_MEM1 interface to moMEM_Mp1 channel
1017 #pragma HLS INTERFACE m_axi depth=ddr_mem_depth port=lcl_mem1 bundle=moMEM_Mp1 \
1018  max_read_burst_length=max_axi_rw_burst_length max_write_burst_length=max_axi_rw_burst_length offset=direct \
1019  num_read_outstanding=16 num_write_outstanding=16 latency=ddr_latency
1020 
1021 #endif
1022 
1023  #pragma HLS DATAFLOW
1024 
1025  //-- LOCAL VARIABLES ------------------------------------------------------
1026  NetworkMetaStream meta_tmp = NetworkMetaStream();
1027  static stream<NetworkWord> sRxpToTxp_Data("sRxpToTxP_Data"); // FIXME: works even with no static
1028  static stream<NetworkMetaStream> sRxtoTx_Meta("sRxtoTx_Meta");
1029  static unsigned int processed_word_rx;
1030  static unsigned int processed_bytes_rx;
1031  static unsigned int processed_word_tx = 0;
1032  static stream<bool> sImageLoaded("sImageLoaded");
1033  static bool skip_read;
1034  static bool write_chunk_to_ddr_pending;
1035  static bool ready_to_accept_new_data;
1036  static bool signal_init;
1037  const int img_in_axi_stream_depth = MIN_RX_LOOPS;
1038  const int img_out_axi_stream_depth = MIN_TX_LOOPS;
1039  const int tot_transfers = TOT_TRANSFERS;
1040 #ifndef ENABLE_DDR
1041 #ifdef USE_HLSLIB_DATAFLOW
1042  static hlslib::Stream<Data_t_in, MIN_RX_LOOPS> img_in_axi_stream ("img_in_axi_stream");
1043  static hlslib::Stream<Data_t_out, MIN_TX_LOOPS> img_out_axi_stream ("img_out_axi_stream");
1044 #else
1045  static stream<ap_uint<INPUT_PTR_WIDTH>> img_in_axi_stream ("img_in_axi_stream");
1046  static stream<ap_uint<OUTPUT_PTR_WIDTH>> img_out_axi_stream ("img_out_axi_stream");
1047 #endif
1048 #endif
1049  //*po_rx_ports = 0x1; //currently work only with default ports...
1050  static stream<NodeId> sDstNode_sig("sDstNode_sig");
1051 
1052 
1053  //-- DIRECTIVES FOR THIS PROCESS ------------------------------------------
1054 #pragma HLS stream variable=sRxtoTx_Meta depth=tot_transfers
1055 #pragma HLS reset variable=enqueueFSM
1056 #pragma HLS reset variable=dequeueFSM
1057 #pragma HLS reset variable=HarrisFSM
1058 #pragma HLS reset variable=processed_word_rx
1059 #pragma HLS reset variable=processed_word_tx
1060 #pragma HLS reset variable=processed_bytes_rx
1061 //#pragma HLS reset variable=image_loaded
1062 #pragma HLS stream variable=sImageLoaded depth=1
1063 #pragma HLS reset variable=skip_read
1064 #pragma HLS reset variable=write_chunk_to_ddr_pending
1065 //#pragma HLS stream variable=sWriteChunkToDdrPending depth=2
1066 #pragma HLS reset variable=ready_to_accept_new_data
1067 #pragma HLS reset variable=signal_init
1068 #pragma HLS STREAM variable=sDstNode_sig depth=1
1069 
1070 #ifndef ENABLE_DDR
1071 #pragma HLS stream variable=img_in_axi_stream depth=img_in_axi_stream_depth
1072 #pragma HLS stream variable=img_out_axi_stream depth=img_out_axi_stream_depth
1073 #else
1074 #pragma HLS reset variable=fsmStateDDR
1075 #endif
1076 
1077 
1078 
1079 
1080 #ifdef USE_HLSLIB_DATAFLOW
1096  // Dataflow functions running in parallel
1097  HLSLIB_DATAFLOW_INIT();
1098 
1099  HLSLIB_DATAFLOW_FUNCTION(pRXPath,
1100  siSHL_This_Data,
1101  siNrc_meta,
1102  sRxtoTx_Meta,
1103  img_in_axi_stream,
1104  meta_tmp,
1105  &processed_word_rx,
1106  &processed_bytes_rx,
1107  //&image_loaded
1108  sImageLoaded
1109  );
1110 
1111  HLSLIB_DATAFLOW_FUNCTION(pProcPath,
1112  sRxpToTxp_Data,
1113 #ifdef ENABLE_DDR
1114  lcl_mem0,
1115  lcl_mem1,
1116 #else
1117  img_in_axi_stream,
1118  img_out_axi_stream,
1119 #endif
1120  &image_loaded
1121  );
1122 
1123  HLSLIB_DATAFLOW_FUNCTION(pTXPath,
1124  soTHIS_Shl_Data,
1125  soNrc_meta,
1126  sRxpToTxp_Data,
1127  sRxtoTx_Meta,
1128  &processed_word_tx,
1129  pi_rank,
1130  pi_size);
1131 
1132  HLSLIB_DATAFLOW_FINALIZE();
1133 
1134 #else // !USE_HLSLIB_DATAFLOW
1135 
1136  pPortAndDestionation(
1137  pi_rank,
1138  pi_size,
1139  sDstNode_sig,
1140  po_rx_ports
1141  );
1142 
1143 #ifdef ENABLE_DDR
1144 
1145  pRXPathDDR(
1146  siSHL_This_Data,
1147  siNrc_meta,
1148  sRxtoTx_Meta,
1149  //---- P0 Write Path (S2MM) -----------
1150  soMemWrCmdP0,
1151  siMemWrStsP0,
1152  soMemWriteP0,
1153  // ---- P1 Memory mapped --------------
1154  lcl_mem0,
1155  meta_tmp,
1156  &processed_bytes_rx,
1157  sImageLoaded
1158  );
1159 
1160  #else // !ENABLE_DDR
1161 
1162  pRXPath(
1163  siSHL_This_Data,
1164  siNrc_meta,
1165  sRxtoTx_Meta,
1166  img_in_axi_stream,
1167  meta_tmp,
1168  &processed_word_rx,
1169  &processed_bytes_rx,
1170  sImageLoaded
1171  );
1172 
1173 #endif // ENABLE_DDR
1174 
1175  pProcPath(
1176  sRxpToTxp_Data,
1177 #ifdef ENABLE_DDR
1178  lcl_mem0,
1179  lcl_mem1,
1180 #else
1181  img_in_axi_stream,
1182  img_out_axi_stream,
1183 #endif
1184  sImageLoaded
1185  );
1186 
1187  pTXPath(
1188  sDstNode_sig,
1189  soTHIS_Shl_Data,
1190  soNrc_meta,
1191  sRxpToTxp_Data,
1192  sRxtoTx_Meta,
1193  &processed_word_tx,
1194  pi_rank,
1195  pi_size
1196  );
1197 
1198 #endif // USE_HLSLIB_DATAFLOW
1199 }
pPortAndDestionation
void pPortAndDestionation(ap_uint< 32 > *pi_rank, ap_uint< 32 > *pi_size, stream< NodeId > &sDstNode_sig, ap_uint< 32 > *po_rx_ports)
Definition: harris.cpp:63
pTXPath
void pTXPath(stream< NodeId > &sDstNode_sig, stream< NetworkWord > &soTHIS_Shl_Data, stream< NetworkMetaStream > &soNrc_meta, stream< NetworkWord > &sRxpToTxp_Data, stream< NetworkMetaStream > &sRxtoTx_Meta, unsigned int *processed_word_tx, ap_uint< 32 > *pi_rank, ap_uint< 32 > *pi_size)
Transmit Path - From THIS to SHELL.
Definition: harris.cpp:782
pRXPath
void pRXPath(stream< NetworkWord > &siSHL_This_Data, stream< NetworkMetaStream > &siNrc_meta, stream< NetworkMetaStream > &sRxtoTx_Meta, stream< ap_uint< 8 >> &img_in_axi_stream, NetworkMetaStream meta_tmp, unsigned int *processed_word_rx, unsigned int *processed_bytes_rx, stream< bool > &sImageLoaded)
Receive Path - From SHELL to THIS.
Definition: harris.cpp:513
pProcPath
void pProcPath(stream< NetworkWord > &sRxpToTxp_Data, stream< ap_uint< 8 >> &img_in_axi_stream, stream< ap_uint< 64 >> &img_out_axi_stream, stream< bool > &sImageLoaded)
Processing Path - Main processing FSM for Vitis kernels.
Definition: harris.cpp:580
MIN_TX_LOOPS
#define MIN_TX_LOOPS
Definition: mceuropeanengine.hpp:88
MIN_RX_LOOPS
#define MIN_RX_LOOPS
Definition: mceuropeanengine.hpp:87
TOT_TRANSFERS
#define TOT_TRANSFERS
Definition: config.h:70
DDR_LATENCY
#define DDR_LATENCY
Definition: memtest.hpp:98
ENABLE_DDR
#define ENABLE_DDR
Definition: memtest.hpp:42
TOTMEMDW_512
#define TOTMEMDW_512
Definition: memtest.hpp:93
lcl_mem0
membus_t lcl_mem0[16384]
Definition: test_memtest.cpp:87
lcl_mem1
membus_t lcl_mem1[16384]
Definition: test_memtest.cpp:88
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◆ harris_accel()

void harris_accel ( xf::cv::Mat< XF_8UC1, 16, 16, XF_NPPC1 > &  _src,
xf::cv::Mat< XF_8UC1, 16, 16, XF_NPPC1 > &  _dst,
unsigned short  Thresh,
unsigned short  k 
)

Top-level accelerated function of the Harris Application with xf::cv I/F.

Returns
Nothing.

Definition at line 41 of file xf_harris_accel.cpp.

44  {
45  xf::cv::cornerHarris<FILTER_WIDTH, BLOCK_WIDTH, NMS_RADIUS, XF_8UC1, HEIGHT, WIDTH, NPIX, XF_USE_URAM>(_src, _dst,
46  Thresh, k);
47 }
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◆ pPortAndDestionation()

void pPortAndDestionation ( ap_uint< 32 > *  pi_rank,
ap_uint< 32 > *  pi_size,
stream< NodeId > &  sDstNode_sig,
ap_uint< 32 > *  po_rx_ports 
)

Definition at line 63 of file harris.cpp.

69 {
70  //-- DIRECTIVES FOR THIS PROCESS ------------------------------------------
71 #pragma HLS inline off
72 //#pragma HLS pipeline II=1 //not necessary
73  //-- STATIC VARIABLES (with RESET) ------------------------------------------
74  static PortFsmType port_fsm = FSM_WRITE_NEW_DATA;
75 #pragma HLS reset variable=port_fsm
76 
77 
78  switch(port_fsm)
79  {
80  default:
81  case FSM_WRITE_NEW_DATA:
82  printf("DEBUG in pPortAndDestionation: port_fsm - FSM_WRITE_NEW_DATA\n");
83  //Triangle app needs to be reset to process new rank
84  if(!sDstNode_sig.full())
85  {
86  NodeId dst_rank = (*pi_rank + 1) % *pi_size;
87  printf("rank: %d; size: %d; \n", (int) *pi_rank, (int) *pi_size);
88  sDstNode_sig.write(dst_rank);
89  port_fsm = FSM_DONE;
90  }
91  break;
92  case FSM_DONE:
93  printf("DEBUG in pPortAndDestionation: port_fsm - FSM_DONE\n");
94  *po_rx_ports = PORTS_OPENED;
95  break;
96  }
97 }
PORTS_OPENED
#define PORTS_OPENED
Definition: harris.hpp:102
FSM_WRITE_NEW_DATA
#define FSM_WRITE_NEW_DATA
Definition: memtest.hpp:78
FSM_DONE
#define FSM_DONE
Definition: memtest.hpp:79
PortFsmType
#define PortFsmType
Definition: memtest.hpp:80
NodeId
ap_uint< 8 > NodeId
Definition: network.hpp:82
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◆ pProcPath()

void pProcPath ( stream< NetworkWord > &  sRxpToTxp_Data,
stream< ap_uint< 8 >> &  img_in_axi_stream,
stream< ap_uint< 64 >> &  img_out_axi_stream,
stream< bool > &  sImageLoaded 
)

Processing Path - Main processing FSM for Vitis kernels.

Parameters
[out]sRxpToTxp_Data
[in]img_in_axi_stream
[in]img_out_axi_stream
[out]processed_word_rx
[in]sImageLoaded
Returns
Nothing.

Definition at line 580 of file harris.cpp.

599 {
600  //-- DIRECTIVES FOR THIS PROCESS ------------------------------------------
601  #pragma HLS INLINE off
602  #pragma HLS pipeline II=1
603 
604  //-- LOCAL VARIABLES ------------------------------------------------------
605  NetworkWord newWord;
606  uint16_t Thresh = 442;
607  float K = 0.04;
608  uint16_t k = K * (1 << 16); // Convert to Q0.16 format
609  static bool accel_called;
610  static unsigned int processed_word_proc;
611  static unsigned int timeoutCntAbs;
612  static unsigned int cnt_i;
613  static membus_t tmp;
614  ap_uint<OUTPUT_PTR_WIDTH> raw64;
615  Data_t_out temp;
616  #ifdef ENABLE_DDR
617  //static stream<ap_uint<OUTPUT_PTR_WIDTH>> img_out_axi_stream ("img_out_axi_stream");
618  //#pragma HLS stream variable=img_out_axi_stream depth=9
619  static unsigned int ddr_addr_out;
620  #pragma HLS reset variable=ddr_addr_out
621  #endif
622 
623  #pragma HLS reset variable=accel_called
624  #pragma HLS reset variable=processed_word_proc
625  #pragma HLS reset variable=timeoutCntAbs
626  #pragma HLS reset variable=cnt_i
627  #pragma HLS reset variable=tmp
628  #pragma HLS reset variable=raw64
629  #pragma HLS reset variable=temp
630 
631  switch(HarrisFSM)
632  {
633  case WAIT_FOR_META:
634  printf("DEBUG in pProcPath: WAIT_FOR_META\n");
635  if (!sImageLoaded.empty())
636  {
637  if (sImageLoaded.read() == true) {
638  HarrisFSM = PROCESSING_PACKET;
639  accel_called = false;
640  processed_word_proc = 0;
641  #ifdef ENABLE_DDR
642  ddr_addr_out = 0;
643  timeoutCntAbs = 0;
644  cnt_i = 0;
645  #endif
646  }
647  }
648  break;
649 
650  case PROCESSING_PACKET:
651  printf("DEBUG in pProcPath: PROCESSING_PACKET\n");
652  #ifndef ENABLE_DDR
653  if ( !img_in_axi_stream.empty() && !img_out_axi_stream.full() )
654  {
655  #endif
656  if (accel_called == false) {
657  #ifdef ENABLE_DDR
658  cornerHarrisAccelMem(lcl_mem0, lcl_mem1, WIDTH, HEIGHT, Thresh, k);
659  #else // ! ENABLE_DDR
660  #ifdef FAKE_Harris
661  fakeCornerHarrisAccelStream(img_in_axi_stream, img_out_axi_stream, MIN_RX_LOOPS, MIN_TX_LOOPS);
662  #else // !FAKE_Harris
663  cornerHarrisAccelStream(img_in_axi_stream, img_out_axi_stream, WIDTH, HEIGHT, Thresh, k);
664  #endif // FAKE_Harris
665  #endif // ENABLE_DDR
666  accel_called = true;
667  HarrisFSM = HARRIS_RETURN_RESULTS;
668  }
669  #ifndef ENABLE_DDR
670  }
671  #endif
672  break;
673 
674  #ifdef ENABLE_DDR
675  case HARRIS_RETURN_RESULTS:
676  printf("DEBUG in pProcPath: HARRIS_RETURN_RESULTS, ddr_addr_out=%u\n", ddr_addr_out);
677  if (accel_called == true) {
678 
679  printf("DEBUG in pProcPath: Accumulated %u net words (%u B) to complete a single DDR word\n",
680  KWPERMDW_512, BPERMDW_512);
681  tmp = lcl_mem1[ddr_addr_out];
682  ddr_addr_out++;
683  HarrisFSM = HARRIS_RETURN_RESULTS_ABSORB_DDR_LAT;
684  timeoutCntAbs = 0;
685  }
686  break;
687 
688  case HARRIS_RETURN_RESULTS_ABSORB_DDR_LAT:
689  printf("DEBUG in pProcPath: HARRIS_RETURN_RESULTS_ABSORB_DDR_LAT [%u out of %u]\n", timeoutCntAbs, DDR_LATENCY);
690  if (timeoutCntAbs++ == DDR_LATENCY) {
691  HarrisFSM = HARRIS_RETURN_RESULTS_FWD; //HARRIS_RETURN_RESULTS_UNPACK;
692  cnt_i = 0;
693  }
694  break;
695  /*
696  case HARRIS_RETURN_RESULTS_UNPACK:
697  printf("DEBUG in pProcPath: HARRIS_RETURN_RESULTS_UNPACK, cnt_i=%u\n", cnt_i);
698  //for (unsigned int cnt_i=0; cnt_i<(MEMDW_512/OUTPUT_PTR_WIDTH); cnt_i++) {
699  #if OUTPUT_PTR_WIDTH == 64
700  raw64(0 ,63) = tmp(cnt_i*OUTPUT_PTR_WIDTH , cnt_i*OUTPUT_PTR_WIDTH+63);
701  #endif
702  if ( !img_out_axi_stream.full() ) {
703  img_out_axi_stream.write(raw64);
704  }
705  if (cnt_i == (MEMDW_512/OUTPUT_PTR_WIDTH) - 1) {
706  HarrisFSM = HARRIS_RETURN_RESULTS_FWD;
707  }
708  cnt_i++;
709  //}
710  break;
711  */
712  case HARRIS_RETURN_RESULTS_FWD:
713  printf("DEBUG in pProcPath: HARRIS_RETURN_RESULTS_FWD\n");
714  //if ( !img_out_axi_stream.empty() && !sRxpToTxp_Data.full() ) {
715  if ( (cnt_i <= (MEMDW_512/OUTPUT_PTR_WIDTH) - 1) && !sRxpToTxp_Data.full() ) {
716 
717  //temp.data = img_out_axi_stream.read();
718  temp.data(0 ,63) = tmp(cnt_i*OUTPUT_PTR_WIDTH , cnt_i*OUTPUT_PTR_WIDTH+63);
719  if (processed_word_proc++ == MIN_TX_LOOPS-1) {
720  temp.last = 1;
721  HarrisFSM = WAIT_FOR_META;
722  }
723  else {
724  temp.last = 0;
725  }
726  //TODO: find why Vitis kernel does not set keep and last by itself
727  temp.keep = 255;
728  newWord = NetworkWord(temp.data, temp.keep, temp.last);
729  sRxpToTxp_Data.write(newWord);
730  cnt_i++;
731  }
732  else {
733  HarrisFSM = HARRIS_RETURN_RESULTS;
734  }
735 
736  break;
737 
738  #else // ! ENABLE_DDR
739  case HARRIS_RETURN_RESULTS:
740  printf("DEBUG in pProcPath: HARRIS_RETURN_RESULTS\n");
741  if ( !img_out_axi_stream.empty() && !sRxpToTxp_Data.full() )
742  {
743 
744  temp.data = img_out_axi_stream.read();
745  if ( img_out_axi_stream.empty() )
746  //if (processed_word_proc++ == MIN_TX_LOOPS-1)
747  {
748  temp.last = 1;
749  HarrisFSM = WAIT_FOR_META;
750  accel_called = false;
751  }
752  else
753  {
754  temp.last = 0;
755  }
756  //TODO: find why Vitis kernel does not set keep and last by itself
757  temp.keep = 255;
758  newWord = NetworkWord(temp.data, temp.keep, temp.last);
759  sRxpToTxp_Data.write(newWord);
760  }
761  break;
762  #endif // ENABLE_DDR
763  } // end switch
764 
765 }
HARRIS_RETURN_RESULTS_ABSORB_DDR_LAT
#define HARRIS_RETURN_RESULTS_ABSORB_DDR_LAT
Definition: harris.hpp:75
HarrisFSM
uint8_t HarrisFSM
Definition: harris.cpp:52
BPERMDW_512
#define BPERMDW_512
Definition: harris.hpp:120
KWPERMDW_512
#define KWPERMDW_512
Definition: harris.hpp:121
HARRIS_RETURN_RESULTS_FWD
#define HARRIS_RETURN_RESULTS_FWD
Definition: harris.hpp:77
HARRIS_RETURN_RESULTS
#define HARRIS_RETURN_RESULTS
Definition: harris.hpp:74
cornerHarrisAccelMem
void cornerHarrisAccelMem(membus_t *img_inp, membus_t *img_out, int rows, int cols, int threshold, int k)
Top-level accelerated function of the Harris Application with array I/F.
Definition: xf_harris_accel.cpp:216
fakeCornerHarrisAccelStream
void fakeCornerHarrisAccelStream(hls::stream< ap_axiu< 8, 0, 0, 0 > > &img_in_axi_stream, hls::stream< ap_axiu< 64, 0, 0, 0 > > &img_out_axi_stream, unsigned int min_rx_loops, unsigned int min_tx_loops)
cornerHarrisAccelStream
void cornerHarrisAccelStream(hls::stream< ap_uint< 8 >> &img_in_axi_stream, hls::stream< ap_uint< 64 >> &img_out_axi_stream, int rows, int cols, int threshold, int k)
Top-level accelerated function of the Harris Application with array I/F.
Definition: xf_harris_accel.cpp:106
MEMDW_512
#define MEMDW_512
Definition: memtest.hpp:90
Data_t_out
#define Data_t_out
Definition: memtest.cpp:30
membus_t
membus_512_t membus_t
Definition: memtest.hpp:92
PROCESSING_PACKET
#define PROCESSING_PACKET
Definition: memtest.hpp:73
WAIT_FOR_META
#define WAIT_FOR_META
Definition: memtest.hpp:71
test_harris_standalone.tmp
tmp
Definition: test_harris_standalone.py:101
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◆ pRXPath()

void pRXPath ( stream< NetworkWord > &  siSHL_This_Data,
stream< NetworkMetaStream > &  siNrc_meta,
stream< NetworkMetaStream > &  sRxtoTx_Meta,
stream< ap_uint< 8 >> &  img_in_axi_stream,
NetworkMetaStream  meta_tmp,
unsigned int *  processed_word_rx,
unsigned int *  processed_bytes_rx,
stream< bool > &  sImageLoaded 
)

Receive Path - From SHELL to THIS.

Parameters
[in]siSHL_This_Data
[in]siNrc_meta
[out]sRxtoTx_Meta
[out]img_in_axi_stream
[out]meta_tmp
[out]processed_word
[out]sImageLoaded
Returns
Nothing.

Definition at line 513 of file harris.cpp.

528 {
529  //-- DIRECTIVES FOR THIS PROCESS ------------------------------------------
530  #pragma HLS INLINE off
531  #pragma HLS pipeline II=1
532 
533  //-- LOCAL VARIABLES ------------------------------------------------------
534  static NetworkWord netWord;
535 
536  switch(enqueueFSM)
537  {
538  case WAIT_FOR_META:
539  printf("DEBUG in pRXPath: enqueueFSM - WAIT_FOR_META, *processed_word_rx=%u, *processed_bytes_rx=%u\n",
540  *processed_word_rx, *processed_bytes_rx);
541  if ( !siNrc_meta.empty() && !sRxtoTx_Meta.full() )
542  {
543  meta_tmp = siNrc_meta.read();
544  meta_tmp.tlast = 1; //just to be sure...
545  sRxtoTx_Meta.write(meta_tmp);
546  enqueueFSM = PROCESSING_PACKET;
547  }
548  break;
549 
550  case PROCESSING_PACKET:
551  printf("DEBUG in pRXPath: enqueueFSM - PROCESSING_PACKET, *processed_word_rx=%u, *processed_bytes_rx=%u\n",
552  *processed_word_rx, *processed_bytes_rx);
553  if ( !siSHL_This_Data.empty() && !img_in_axi_stream.full())
554  {
555  //-- Read incoming data chunk
556  netWord = siSHL_This_Data.read();
557  storeWordToAxiStream(netWord, img_in_axi_stream, processed_word_rx, processed_bytes_rx,
558  sImageLoaded);
559  if(netWord.tlast == 1)
560  {
561  enqueueFSM = WAIT_FOR_META;
562  }
563  }
564  break;
565  }
566 }
enqueueFSM
uint8_t enqueueFSM
Definition: harris.cpp:50
storeWordToAxiStream
void storeWordToAxiStream(NetworkWord word, stream< ap_uint< 8 >> &img_in_axi_stream, unsigned int *processed_word_rx, unsigned int *processed_bytes_rx, stream< bool > &sImageLoaded)
Store a net word to a local AXI stream.
Definition: harris.cpp:129
NetworkMetaStream::tlast
ap_uint< 1 > tlast
Definition: network.hpp:111
NetworkWord::tlast
ap_uint< 1 > tlast
Definition: network.hpp:51
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◆ pTXPath()

void pTXPath ( stream< NodeId > &  sDstNode_sig,
stream< NetworkWord > &  soTHIS_Shl_Data,
stream< NetworkMetaStream > &  soNrc_meta,
stream< NetworkWord > &  sRxpToTxp_Data,
stream< NetworkMetaStream > &  sRxtoTx_Meta,
unsigned int *  processed_word_tx,
ap_uint< 32 > *  pi_rank,
ap_uint< 32 > *  pi_size 
)

Transmit Path - From THIS to SHELL.

Parameters
[out]soTHIS_Shl_Data
[out]soNrc_meta
[in]sRxpToTxp_Data
[in]sRxtoTx_Meta
[in]pi_rank
[in]pi_size
Returns
Nothing.

Definition at line 782 of file harris.cpp.

792 {
793  //-- DIRECTIVES FOR THIS PROCESS ------------------------------------------
794  #pragma HLS INLINE off
795  #pragma HLS pipeline II=1
796 
797  //-- STATIC DATAFLOW VARIABLES ------------------------------------------
798  static NodeId dst_rank;
799 
800  //-- LOCAL VARIABLES ------------------------------------------------------
801  NetworkWord netWordTx;
802  NetworkMeta meta_in = NetworkMeta();
803  NetworkMetaStream meta_out_stream = NetworkMetaStream();
804 
805  #pragma HLS reset variable=dst_rank
806  #pragma HLS reset variable=netWordTx
807 
808  switch(dequeueFSM)
809  {
810  default:
811  case WAIT_FOR_META:
812  if(!sDstNode_sig.empty())
813  {
814  dst_rank = sDstNode_sig.read();
815  dequeueFSM = WAIT_FOR_STREAM_PAIR;
816  //Harris app needs to be reset to process new rank
817  }
818  break;
819 
820  case WAIT_FOR_STREAM_PAIR:
821  printf("DEBUG in pTXPath: dequeueFSM=%d - WAIT_FOR_STREAM_PAIR, *processed_word_tx=%u\n",
822  dequeueFSM, *processed_word_tx);
823  //-- Forward incoming chunk to SHELL
824  if (*processed_word_tx == MIN_TX_LOOPS) {
825  *processed_word_tx = 0;
826  }
827  /*
828  printf("!sRxpToTxp_Data.empty()=%d\n", !sRxpToTxp_Data.empty());
829  printf("!sRxtoTx_Meta.empty()=%d\n", !sRxtoTx_Meta.empty());
830  printf("!soTHIS_Shl_Data.full()=%d\n", !soTHIS_Shl_Data.full());
831  printf("!soNrc_meta.full()=%d\n", !soNrc_meta.full());
832  */
833 
834  if (( !sRxpToTxp_Data.empty() && !sRxtoTx_Meta.empty()
835  && !soTHIS_Shl_Data.full() && !soNrc_meta.full() ))
836  {
837  netWordTx = sRxpToTxp_Data.read();
838 
839  // in case MTU=8 ensure tlast is set in WAIT_FOR_STREAM_PAIR and don't visit PROCESSING_PACKET
840  if (PACK_SIZE == 8)
841  {
842  netWordTx.tlast = 1;
843  }
844  soTHIS_Shl_Data.write(netWordTx);
845 
846  meta_in = sRxtoTx_Meta.read().tdata;
847  //NetworkMetaStream meta_out_stream = NetworkMetaStream();
848  meta_out_stream.tlast = 1;
849  meta_out_stream.tkeep = 0xFF; //just to be sure
850 
851  meta_out_stream.tdata.dst_rank = dst_rank; //(*pi_rank + 1) % *pi_size;
852  //meta_out_stream.tdata.dst_port = DEFAULT_TX_PORT;
853  meta_out_stream.tdata.src_rank = (NodeId) *pi_rank;
854 
855  // Forcing the SHELL to wait for tlast
856  meta_out_stream.tdata.len = 0;
857 
858  //meta_out_stream.tdata.src_port = DEFAULT_RX_PORT;
859  //printf("rank: %d; size: %d; \n", (int) *pi_rank, (int) *pi_size);
860  //printf("meat_out.dst_rank: %d\n", (int) meta_out_stream.tdata.dst_rank);
861  meta_out_stream.tdata.dst_port = meta_in.src_port;
862  meta_out_stream.tdata.src_port = meta_in.dst_port;
863 
864 
865  //meta_out_stream.tdata.len = meta_in.len;
866  soNrc_meta.write(meta_out_stream);
867 
868  (*processed_word_tx)++;
869  printf("DEBUGGGG: Checking netWordTx.tlast...\n");
870  if(netWordTx.tlast != 1)
871  {
872  dequeueFSM = PROCESSING_PACKET;
873  }
874  }
875  break;
876 
877  case PROCESSING_PACKET:
878  printf("DEBUG in pTXPath: dequeueFSM=%d - PROCESSING_PACKET, *processed_word_tx=%u\n",
879  dequeueFSM, *processed_word_tx);
880  if( !sRxpToTxp_Data.empty() && !soTHIS_Shl_Data.full())
881  {
882  printf("DEBUGGGG: Reading sRxpToTxp_Data %u\n", sRxpToTxp_DataCounter++);
883  netWordTx = sRxpToTxp_Data.read();
884 
885  (*processed_word_tx)++;
886 
887  // This is a normal termination of the axi stream from vitis functions
888  if ((netWordTx.tlast == 1) || (((*processed_word_tx)*8) % PACK_SIZE == 0))
889  {
890  netWordTx.tlast = 1; // in case it is the 2nd or
891  printf("DEBUGGGG: A netWordTx.tlast=1 ... sRxpToTxp_Data.empty()==%u \n", sRxpToTxp_Data.empty());
892  dequeueFSM = WAIT_FOR_STREAM_PAIR;
893  }
894 
895  // This is our own termination based on the custom MTU we have set in PACK_SIZE.
896  // TODO: We can map PACK_SIZE to a dynamically assigned value either through MMIO or header
897  // in order to have a functional bitstream for any MTU size
898  //if (((*processed_word_tx)*8) % PACK_SIZE == 0)
899  //{
900  // printf("DEBUGGGG: B (*processed_word_tx)*8) % PACK_SIZE == 0 ...\n");
901  // netWordTx.tlast = 1;
902  // dequeueFSM = WAIT_FOR_STREAM_PAIR;
903  //}
904 
905  soTHIS_Shl_Data.write(netWordTx);
906  }
907  break;
908  }
909 }
sRxpToTxp_DataCounter
unsigned int sRxpToTxp_DataCounter
Definition: harris.cpp:768
dequeueFSM
uint8_t dequeueFSM
Definition: harris.cpp:51
WAIT_FOR_STREAM_PAIR
#define WAIT_FOR_STREAM_PAIR
Definition: memtest.hpp:72
PACK_SIZE
#define PACK_SIZE
Definition: config.h:51
NetworkMetaStream::tkeep
ap_uint< 8 > tkeep
Definition: network.hpp:110
NetworkMetaStream::tdata
NetworkMeta tdata
Definition: network.hpp:109
NetworkMeta::len
NetworkDataLength len
Definition: network.hpp:99
NetworkMeta::dst_rank
NodeId dst_rank
Definition: network.hpp:95
NetworkMeta::src_rank
NodeId src_rank
Definition: network.hpp:97
NetworkMeta::src_port
NrcPort src_port
Definition: network.hpp:98
NetworkMeta::dst_port
NrcPort dst_port
Definition: network.hpp:96
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◆ storeWordToArray()

void storeWordToArray ( uint64_t  input,
ap_uint< 8 >  img[16 *16/((64/8))],
unsigned int *  processed_word,
unsigned int *  image_loaded 
)

Store a net word to local memory.

Returns
Nothing.

Definition at line 105 of file harris.cpp.

107 {
108  #pragma HLS INLINE
109 
110  img[*processed_word] = (ap_uint<INPUT_PTR_WIDTH>) input;
111  printf("DEBUG in storeWordToArray: input = %u = 0x%16.16llX \n", input, input);
112  printf("DEBUG in storeWordToArray: img[%u]= %u = 0x%16.16llX \n", *processed_word,
113  (uint64_t)img[*processed_word], (uint64_t)img[*processed_word]);
114  if (*processed_word < IMG_PACKETS-1) {
115  *processed_word++;
116  }
117  else {
118  printf("DEBUG in storeWordToArray: WARNING - you've reached the max depth of img[%u]. Will put *processed_word = 0.\n", *processed_word);
119  *processed_word = 0;
120  *image_loaded = 1;
121  }
122 }
IMG_PACKETS
#define IMG_PACKETS
Definition: xf_gammacorrection_config.h:69
test.input
string input
Definition: test.py:9

◆ storeWordToAxiStream()

void storeWordToAxiStream ( NetworkWord  word,
stream< ap_uint< 8 >> &  img_in_axi_stream,
unsigned int *  processed_word_rx,
unsigned int *  processed_bytes_rx,
stream< bool > &  sImageLoaded 
)

Store a net word to a local AXI stream.

Returns
Nothing.

Definition at line 129 of file harris.cpp.

141 {
142  #pragma HLS INLINE
143  Data_t_in v;
144  const unsigned int loop_cnt = (BITS_PER_10GBITETHRNET_AXI_PACKET/INPUT_PTR_WIDTH);
145  const unsigned int bytes_per_loop = (BYTES_PER_10GBITETHRNET_AXI_PACKET/loop_cnt);
146  unsigned int bytes_with_keep = 0;
147  //v = word.tdata;
148  for (unsigned int i=0; i<loop_cnt; i++) {
149  //#pragma HLS PIPELINE
150  //#pragma HLS UNROLL factor=loop_cnt
151  //printf("DEBUG: Checking: word.tkeep=%u >> %u = %u\n", word.tkeep.to_int(), i, (word.tkeep.to_int() >> i));
152  if ((word.tkeep >> i) == 0) {
153  printf("WARNING: value with tkeep=0 at i=%u\n", i);
154  continue;
155  }
156  v.data = (ap_uint<INPUT_PTR_WIDTH>)(word.tdata >> i*8);
157  v.keep = word.tkeep;
158  v.last = word.tlast;
159  //printf("DEBUG in storeWordToAxiStream: word = %u = 0x%16.16llX \n", v.data, v.data);
160  img_in_axi_stream.write(v.data);
161  bytes_with_keep += bytes_per_loop;
162  }
163  /*
164  if (*processed_word_rx < IMG_PACKETS-1) {
165  (*processed_word_rx)++;
166  }
167  else {
168  printf("DEBUG in storeWordToAxiStream: WARNING - you've reached the max depth of img. Will put *processed_word_rx = 0.\n");
169  *processed_word_rx = 0;
170  }*/
171  if (*processed_bytes_rx < IMGSIZE-BYTES_PER_10GBITETHRNET_AXI_PACKET) {
172  (*processed_bytes_rx) += bytes_with_keep;
173  if (!sImageLoaded.full()) {
174  sImageLoaded.write(false);
175  }
176  }
177  else {
178  printf("DEBUG in storeWordToAxiStream: WARNING - you've reached the max depth of img. Will put *processed_bytes_rx = 0.\n");
179  *processed_bytes_rx = 0;
180  if (!sImageLoaded.full()) {
181  sImageLoaded.write(true);
182  }
183  }
184 }
IMGSIZE
#define IMGSIZE
Definition: xf_gammacorrection_config.h:67
BITS_PER_10GBITETHRNET_AXI_PACKET
#define BITS_PER_10GBITETHRNET_AXI_PACKET
Definition: mceuropeanengine.hpp:81
BYTES_PER_10GBITETHRNET_AXI_PACKET
#define BYTES_PER_10GBITETHRNET_AXI_PACKET
Definition: mceuropeanengine.hpp:82
Data_t_in
#define Data_t_in
Definition: memtest.cpp:29
NetworkWord::tdata
ap_uint< 64 > tdata
Definition: network.hpp:49
NetworkWord::tkeep
ap_uint< 8 > tkeep
Definition: network.hpp:50
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Variable Documentation

◆ dequeueFSM

uint8_t dequeueFSM = 0

Definition at line 51 of file harris.cpp.

◆ enqueueFSM

uint8_t enqueueFSM = 0

Definition at line 50 of file harris.cpp.

◆ fsmStateDDR

uint8_t fsmStateDDR = 9

Definition at line 53 of file harris.cpp.

◆ HarrisFSM

uint8_t HarrisFSM = 0

Definition at line 52 of file harris.cpp.

◆ sRxpToTxp_DataCounter

unsigned int sRxpToTxp_DataCounter = 0

Definition at line 768 of file harris.cpp.