cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
mem_test_flash.cpp File Reference
#include "mem_test_flash.hpp"
Include dependency graph for mem_test_flash.cpp:

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Functions

ap_uint< 8 > STS_to_Vector (DmSts sts)
 
void mem_test_flash_main (ap_uint< 1 > sys_reset, ap_uint< 2 > DIAG_CTRL_IN, ap_uint< 2 > *DIAG_STAT_OUT, ap_uint< 16 > *debug_out, stream< DmCmd > &soMemRdCmdP0, stream< DmSts > &siMemRdStsP0, stream< Axis< 512 > > &siMemReadP0, stream< DmCmd > &soMemWrCmdP0, stream< DmSts > &siMemWrStsP0, stream< Axis< 512 > > &soMemWriteP0)
 

Variables

ap_uint< 8 > fsmState = 0
 
bool runContiniously = false
 
ap_uint< 1 > wasError = 0
 
ap_uint< 33 > lastCheckedAddress = 0
 
ap_uint< 33 > currentPatternAdderss = 0
 
ap_uint< 64 > currentMemPattern = 0
 
ap_uint< 32 > patternWriteNum = 0
 
ap_uint< 16 > debugVec = 0
 
ap_uint< 8 > testPhase = 0
 
ap_uint< 32 > timeoutCnt = 0
 

Function Documentation

◆ mem_test_flash_main()

void mem_test_flash_main ( ap_uint< 1 >  sys_reset,
ap_uint< 2 >  DIAG_CTRL_IN,
ap_uint< 2 > *  DIAG_STAT_OUT,
ap_uint< 16 > *  debug_out,
stream< DmCmd > &  soMemRdCmdP0,
stream< DmSts > &  siMemRdStsP0,
stream< Axis< 512 > > &  siMemReadP0,
stream< DmCmd > &  soMemWrCmdP0,
stream< DmSts > &  siMemWrStsP0,
stream< Axis< 512 > > &  soMemWriteP0 
)

Definition at line 63 of file mem_test_flash.cpp.

87 {
88 
89 #pragma HLS INTERFACE ap_vld register port=sys_reset name=piSysReset
90 #pragma HLS INTERFACE ap_vld register port=DIAG_CTRL_IN name=piMMIO_diag_ctrl
91 #pragma HLS INTERFACE ap_ovld register port=DIAG_STAT_OUT name=poMMIO_diag_stat
92 #pragma HLS INTERFACE ap_ovld register port=debug_out name=poDebug
93 
94  // Bundling: SHELL / Role / Mem / Mp0 / Read Interface
95 #pragma HLS INTERFACE axis register both port=soMemRdCmdP0
96 #pragma HLS INTERFACE axis register both port=siMemRdStsP0
97 #pragma HLS INTERFACE axis register both port=siMemReadP0
98 
99 #pragma HLS DATA_PACK variable=soMemRdCmdP0 instance=soMemRdCmdP0
100 #pragma HLS DATA_PACK variable=siMemRdStsP0 instance=siMemRdStsP0
101 
102  // Bundling: SHELL / Role / Mem / Mp0 / Write Interface
103 #pragma HLS INTERFACE axis register both port=soMemWrCmdP0
104 #pragma HLS INTERFACE axis register both port=siMemWrStsP0
105 #pragma HLS INTERFACE axis register both port=soMemWriteP0
106 
107 #pragma HLS DATA_PACK variable=soMemWrCmdP0 instance=soMemWrCmdP0
108 #pragma HLS DATA_PACK variable=siMemWrStsP0 instance=siMemWrStsP0
109 
110 
111 
112  Axis<512> memP0;
113  DmSts memRdStsP0;
114  DmSts memWrStsP0;
115 
116  //initalize
117  memP0.tdata = 0;
118  memP0.tlast = 0;
119  memP0.tkeep = 0;
120 
121 
122  if(sys_reset == 1)
123  {
124  fsmState = FSM_IDLE;
125  runContiniously = false;
126  wasError = 0;
127  //lastCheckedAddress = 0;
128  lastCheckedAddress = MEM_END_ADDR + 1; //to stop the test
130  currentMemPattern = 0;
131  patternWriteNum = 0;
132  debugVec = 0;
134  timeoutCnt = 0;
135  return;
136  }
137 
138 
139  switch(fsmState) {
140 
141  case FSM_IDLE:
142  switch(DIAG_CTRL_IN) {
143  case 0x3: //reserved --> idle
144  case 0x0: //stay IDLE, stop test
145  *DIAG_STAT_OUT = (0 << 1) | wasError;
146  runContiniously = false;
148  break;
149  case 0x2:
150  runContiniously = true;
151  //NO break
152  case 0x1: //Run once
154  { // start new test
155  wasError = 0;
158  *DIAG_STAT_OUT = 0b10;
159  debugVec = 0;
161  currentMemPattern = 0;
162  } else if(lastCheckedAddress >= MEM_END_ADDR)
163  {//checked space completely once
164 
166  {
170  currentMemPattern = 0;
171  } else if(testPhase == PHASE_RAMP_READ)
172  {
176  currentMemPattern = 0;
177  } else if (runContiniously)
178  {
181  currentMemPattern = 0;
183  *DIAG_STAT_OUT = (1 << 1) | wasError;
184  } else { //stay here
185  fsmState = FSM_IDLE;
186  *DIAG_STAT_OUT = (0 << 1) | wasError;
187  }
188  } else { //continue current run
189 
191  {
193  } else {
195  }
196 
197  *DIAG_STAT_OUT = (1 << 1) | wasError;
198  if(testPhase == PHASE_STRESS)
199  {
200  currentMemPattern = 0;
201  }
202  }
203  break;
204  }
205 
206  //stop on error
207  if(wasError == 1)
208  {
209  fsmState = FSM_IDLE;
210  *DIAG_STAT_OUT = (0 << 1) | wasError;
211  }
212 
213  //set current address
215  {
217  } else {
219  }
220  break;
221 
222  case FSM_WR_PAT_CMD:
223  if (!soMemWrCmdP0.full()) {
224  //-- Post a memory write command to SHELL/Mem/Mp0
225  soMemWrCmdP0.write(DmCmd(currentPatternAdderss, CHECK_CHUNK_SIZE));
226  patternWriteNum = 0;
228  }
229  break;
230 
231  case FSM_WR_PAT_DATA:
232  if (!soMemWriteP0.full()) {
233  //-- Assemble a memory word and write it to DRAM
236  ap_uint<8> keepVal = 0xFF;
237  memP0.tkeep = (ap_uint<64>) (keepVal, keepVal, keepVal, keepVal, keepVal, keepVal, keepVal, keepVal);
238  //memP0.tkeep = (ap_uint<64>) (0xFF, 0xFF, 0xFF, 0xFF,0xFF, 0xFF, 0xFF, 0xFF);
239 
241  {
242  memP0.tlast = 1;
244  timeoutCnt = 0;
245  } else {
246  memP0.tlast = 0;
247  }
248  soMemWriteP0.write(memP0);
249  patternWriteNum++;
250  }
251  break;
252 
253  case FSM_WR_PAT_STS:
254  if (!siMemWrStsP0.empty()) {
255  //-- Get the memory write status for Mem/Mp0
256  siMemWrStsP0.read(memWrStsP0);
257  //latch errors
258  debugVec |= (ap_uint<16>) STS_to_Vector(memWrStsP0);
259 
261  {
262  fsmState = FSM_IDLE;
263  debugVec |= ((ap_uint<16>) STS_to_Vector(memRdStsP0) )<< 8;
265  } else {
267  currentMemPattern = 0;
268  }
269  } else {
270  timeoutCnt++;
272  {
273  wasError = 1;
274  fsmState = FSM_IDLE;
275  }
276  }
277 
278  break;
279 
280  case FSM_RD_PAT_CMD:
281  if (!soMemRdCmdP0.full()) {
282  //-- Post a memory read command to SHELL/Mem/Mp0
283  soMemRdCmdP0.write(DmCmd(currentPatternAdderss, CHECK_CHUNK_SIZE));
285  }
286  break;
287 
288  case FSM_RD_PAT_DATA:
289  if (!siMemReadP0.empty()) {
290  //-- Read a memory word from DRAM
291  siMemReadP0.read(memP0);
294  {
295  printf("error in pattern reading!\n");
296  wasError = 1;
297  }
298  /*if (memP0.tkeep != (0xFF, 0xFF, 0xFF, 0xFF,0xFF, 0xFF, 0xFF, 0xFF))
299  {
300  printf("error in tkeep\n");
301  }*/
302  //I trust that there will be a tlast (so no counting)
303  if (memP0.tlast == 1)
304  {
306  timeoutCnt = 0;
307  }
308  }
309  break;
310 
311  case FSM_RD_PAT_STS:
312  if (!siMemRdStsP0.empty()) {
313  //-- Get the memory read status for Mem/Mp0
314  siMemRdStsP0.read(memRdStsP0);
315  //latch errors
316  debugVec |= ((ap_uint<16>) STS_to_Vector(memRdStsP0) )<< 8;
317 
319  {
320  fsmState = FSM_IDLE;
321  debugVec |= ((ap_uint<16>) STS_to_Vector(memRdStsP0) )<< 8;
323  } else {
325  currentMemPattern = 0;
326  }
327  } else {
328  timeoutCnt++;
330  {
331  wasError = 1;
332  fsmState = FSM_IDLE;
333  }
334  }
335  break;
336 
337  case FSM_WR_ANTI_CMD:
338  if (!soMemWrCmdP0.full()) {
339  //-- Post a memory write command to SHELL/Mem/Mp0
340  soMemWrCmdP0.write(DmCmd(currentPatternAdderss, CHECK_CHUNK_SIZE));
341  currentMemPattern = 0;
342  patternWriteNum = 0;
344  }
345  break;
346 
347  case FSM_WR_ANTI_DATA:
348  if (!soMemWriteP0.full()) {
349  //-- Assemble a memory word and write it to DRAM
351  ap_uint<64> currentAntiPattern = ~currentMemPattern;
352  //debug
353  //printf("AntiPattern: 0x%llX\n", (uint64_t) currentAntiPattern);
354 
355  memP0.tdata = (currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern);
356  ap_uint<8> keepVal = 0xFF;
357  memP0.tkeep = (ap_uint<64>) (keepVal, keepVal, keepVal, keepVal, keepVal, keepVal, keepVal, keepVal);
358  //memP0.tkeep = (0xFF, 0xFF, 0xFF, 0xFF,0xFF, 0xFF, 0xFF, 0xFF);
359 
361  {
362  memP0.tlast = 1;
364  timeoutCnt = 0;
365  } else {
366  memP0.tlast = 0;
367  }
368  soMemWriteP0.write(memP0);
369  patternWriteNum++;
370  }
371  break;
372 
373  case FSM_WR_ANTI_STS:
374  if (!siMemWrStsP0.empty()) {
375  //-- Get the memory write status for Mem/Mp0
376  siMemWrStsP0.read(memWrStsP0);
377  //latch errors
378  debugVec |= (ap_uint<16>) STS_to_Vector(memWrStsP0);
380  } else {
381  timeoutCnt++;
383  {
384  wasError = 1;
385  fsmState = FSM_IDLE;
386  }
387  }
388  break;
389 
390  case FSM_RD_ANTI_CMD:
391  if (!soMemRdCmdP0.full()) {
392  //-- Post a memory read command to SHELL/Mem/Mp0
393  soMemRdCmdP0.write(DmCmd(currentPatternAdderss, CHECK_CHUNK_SIZE));
394  currentMemPattern = 0;
396  }
397  break;
398 
399  case FSM_RD_ANTI_DATA:
400  if (!siMemReadP0.empty()) {
401  //-- Read a memory word from DRAM
402  siMemReadP0.read(memP0);
404  ap_uint<64> currentAntiPattern = ~currentMemPattern;
405 
406  if (memP0.tdata != ((ap_uint<512>) (currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern)) )
407  {
408  printf("error in antipattern reading!\n");
409  wasError = 1;
410  }
411  /*if (memP0.tkeep != (0xFF, 0xFF, 0xFF, 0xFF,0xFF, 0xFF, 0xFF, 0xFF))
412  {
413  printf("error in tkeep\n");
414  }*/
415  //I trust that there will be a tlast (so no counting)
416  if (memP0.tlast == 1)
417  {
419  timeoutCnt = 0;
420  }
421  }
422  break;
423 
424  case FSM_RD_ANTI_STS:
425  if (!siMemRdStsP0.empty()) {
426  //-- Get the memory read status for Mem/Mp0
427  siMemRdStsP0.read(memRdStsP0);
428  //latch errors
429  debugVec |= ((ap_uint<16>) STS_to_Vector(memRdStsP0) )<< 8;
431  fsmState = FSM_IDLE;
432  } else {
433  timeoutCnt++;
435  {
436  wasError = 1;
437  fsmState = FSM_IDLE;
438  }
439  }
440  break;
441 
442  } // End: switch
443 
444  ap_uint<16> debug_out_BE = 0x0;
445  debug_out_BE = (ap_uint<32>) ((debugVec >> 8) & 0xFF);
446  debug_out_BE |= (ap_uint<32>) ((debugVec << 8) & 0xFF00);
447 
448  *debug_out = debug_out_BE;
449 
450  return;
451 }
ap_uint< 8 > testPhase
ap_uint< 8 > STS_to_Vector(DmSts sts)
ap_uint< 16 > debugVec
ap_uint< 1 > wasError
ap_uint< 33 > lastCheckedAddress
ap_uint< 32 > timeoutCnt
ap_uint< 32 > patternWriteNum
ap_uint< 64 > currentMemPattern
ap_uint< 8 > fsmState
ap_uint< 33 > currentPatternAdderss
bool runContiniously
#define FSM_RD_ANTI_CMD
#define FSM_RD_PAT_STS
#define PHASE_RAMP_WRITE
#define FSM_RD_ANTI_DATA
#define FSM_WR_PAT_STS
#define FSM_WR_ANTI_CMD
#define MEM_START_ADDR
#define FSM_WR_ANTI_STS
#define PHASE_RAMP_READ
#define FSM_RD_ANTI_STS
#define FSM_RD_PAT_CMD
#define PHASE_STRESS
#define PHASE_IDLE
#define FSM_RD_PAT_DATA
#define FSM_WR_ANTI_DATA
#define MEM_END_ADDR
#define CHECK_CHUNK_SIZE
This define configures tha AXI burst size of DDRM memory-mapped interfaces AXI4 allows 4KiB,...
Definition: harris.hpp:131
#define FSM_WR_PAT_CMD
Definition: harris.hpp:83
#define TRANSFERS_PER_CHUNK
Definition: harris.hpp:133
#define FSM_WR_PAT_DATA
Definition: harris.hpp:85
#define FSM_IDLE
Definition: harris.hpp:79
#define CYCLES_UNTIL_TIMEOUT
Definition: memtest.hpp:96
ap_uint<(D+7)/8 > tkeep
Definition: axi_utils.hpp:49
ap_uint< 1 > tlast
Definition: axi_utils.hpp:50
ap_uint< D > tdata
Definition: axi_utils.hpp:48
Here is the call graph for this function:

◆ STS_to_Vector()

ap_uint<8> STS_to_Vector ( DmSts  sts)

Definition at line 51 of file mem_test_flash.cpp.

52 {
53  ap_uint<8> ret = 0;
54  ret |= sts.tag;
55  ret |= ((ap_uint<8>) sts.interr) << 4;
56  ret |= ((ap_uint<8>) sts.decerr) << 5;
57  ret |= ((ap_uint<8>) sts.slverr) << 6;
58  ret |= ((ap_uint<8>) sts.okay) << 7;
59  return ret;
60 }
ap_uint< 1 > okay
ap_uint< 1 > decerr
ap_uint< 1 > slverr
ap_uint< 4 > tag
ap_uint< 1 > interr

Variable Documentation

◆ currentMemPattern

ap_uint<64> currentMemPattern = 0

Definition at line 45 of file mem_test_flash.cpp.

◆ currentPatternAdderss

ap_uint<33> currentPatternAdderss = 0

Definition at line 44 of file mem_test_flash.cpp.

◆ debugVec

ap_uint<16> debugVec = 0

Definition at line 47 of file mem_test_flash.cpp.

◆ fsmState

ap_uint<8> fsmState = 0

Definition at line 40 of file mem_test_flash.cpp.

◆ lastCheckedAddress

ap_uint<33> lastCheckedAddress = 0

Definition at line 43 of file mem_test_flash.cpp.

◆ patternWriteNum

ap_uint<32> patternWriteNum = 0

Definition at line 46 of file mem_test_flash.cpp.

◆ runContiniously

bool runContiniously = false

Definition at line 41 of file mem_test_flash.cpp.

◆ testPhase

ap_uint<8> testPhase = 0

Definition at line 48 of file mem_test_flash.cpp.

◆ timeoutCnt

ap_uint<32> timeoutCnt = 0

Definition at line 49 of file mem_test_flash.cpp.

◆ wasError

ap_uint<1> wasError = 0

Definition at line 42 of file mem_test_flash.cpp.