mem_test_flash.hpp File Reference

#include <stdint.h>
#include <stdio.h>
#include <hls_stream.h>
#include "ap_int.h"
#include "dynamic.hpp"

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Go to the source code of this file.

Classes
struct	Axis< D >
struct	DmCmd
struct	DmSts

Macros
#define	FSM_IDLE   0
#define	FSM_WR_PAT_CMD   1
#define	FSM_WR_PAT_DATA   2
#define	FSM_WR_PAT_STS   3
#define	FSM_RD_PAT_CMD   4
#define	FSM_RD_PAT_DATA   5
#define	FSM_RD_PAT_STS   6
#define	FSM_WR_ANTI_CMD   7
#define	FSM_WR_ANTI_DATA   8
#define	FSM_WR_ANTI_STS   9
#define	FSM_RD_ANTI_CMD   10
#define	FSM_RD_ANTI_DATA   11
#define	FSM_RD_ANTI_STS   12
#define	PHASE_IDLE   0
#define	PHASE_RAMP_WRITE   1
#define	PHASE_RAMP_READ   2
#define	PHASE_STRESS   3
#define	MEM_START_ADDR   0x000000000
#define	CHECK_CHUNK_SIZE   0x1000
#define	BYTE_PER_MEM_WORD   64
#define	TRANSFERS_PER_CHUNK   (CHECK_CHUNK_SIZE/BYTE_PER_MEM_WORD)
#define	CYCLES_UNTIL_TIMEOUT   0x1000

Functions
void	mem_test_flash_main (ap_uint< 1 > sys_reset, ap_uint< 2 > DIAG_CTRL_IN, ap_uint< 2 > *DIAG_STAT_OUT, ap_uint< 16 > *debug_out, stream< DmCmd > &soMemRdCmdP0, stream< DmSts > &siMemRdStsP0, stream< Axis< 512 > > &siMemReadP0, stream< DmCmd > &soMemWrCmdP0, stream< DmSts > &siMemWrStsP0, stream< Axis< 512 > > &soMemWriteP0)

Macro Definition Documentation

BYTE_PER_MEM_WORD

#define BYTE_PER_MEM_WORD   64

Definition at line 70 of file mem_test_flash.hpp.

CHECK_CHUNK_SIZE

#define CHECK_CHUNK_SIZE   0x1000

Definition at line 69 of file mem_test_flash.hpp.

CYCLES_UNTIL_TIMEOUT

#define CYCLES_UNTIL_TIMEOUT   0x1000

Definition at line 75 of file mem_test_flash.hpp.

FSM_IDLE

#define FSM_IDLE   0

Definition at line 33 of file mem_test_flash.hpp.

FSM_RD_ANTI_CMD

#define FSM_RD_ANTI_CMD   10

Definition at line 43 of file mem_test_flash.hpp.

FSM_RD_ANTI_DATA

#define FSM_RD_ANTI_DATA   11

Definition at line 44 of file mem_test_flash.hpp.

FSM_RD_ANTI_STS

#define FSM_RD_ANTI_STS   12

Definition at line 45 of file mem_test_flash.hpp.

FSM_RD_PAT_CMD

#define FSM_RD_PAT_CMD   4

Definition at line 37 of file mem_test_flash.hpp.

FSM_RD_PAT_DATA

#define FSM_RD_PAT_DATA   5

Definition at line 38 of file mem_test_flash.hpp.

FSM_RD_PAT_STS

#define FSM_RD_PAT_STS   6

Definition at line 39 of file mem_test_flash.hpp.

FSM_WR_ANTI_CMD

#define FSM_WR_ANTI_CMD   7

Definition at line 40 of file mem_test_flash.hpp.

FSM_WR_ANTI_DATA

#define FSM_WR_ANTI_DATA   8

Definition at line 41 of file mem_test_flash.hpp.

FSM_WR_ANTI_STS

#define FSM_WR_ANTI_STS   9

Definition at line 42 of file mem_test_flash.hpp.

FSM_WR_PAT_CMD

#define FSM_WR_PAT_CMD   1

Definition at line 34 of file mem_test_flash.hpp.

FSM_WR_PAT_DATA

#define FSM_WR_PAT_DATA   2

Definition at line 35 of file mem_test_flash.hpp.

FSM_WR_PAT_STS

#define FSM_WR_PAT_STS   3

Definition at line 36 of file mem_test_flash.hpp.

MEM_START_ADDR

#define MEM_START_ADDR   0x000000000

Definition at line 55 of file mem_test_flash.hpp.

PHASE_IDLE

#define PHASE_IDLE   0

Definition at line 49 of file mem_test_flash.hpp.

PHASE_RAMP_READ

#define PHASE_RAMP_READ   2

Definition at line 51 of file mem_test_flash.hpp.

PHASE_RAMP_WRITE

#define PHASE_RAMP_WRITE   1

Definition at line 50 of file mem_test_flash.hpp.

PHASE_STRESS

#define PHASE_STRESS   3

Definition at line 52 of file mem_test_flash.hpp.

TRANSFERS_PER_CHUNK

#define TRANSFERS_PER_CHUNK   (CHECK_CHUNK_SIZE/BYTE_PER_MEM_WORD)

Definition at line 71 of file mem_test_flash.hpp.

Function Documentation

mem_test_flash_main()

void mem_test_flash_main	(	ap_uint< 1 >	sys_reset,
		ap_uint< 2 >	DIAG_CTRL_IN,
		ap_uint< 2 > *	DIAG_STAT_OUT,
		ap_uint< 16 > *	debug_out,
		stream< DmCmd > &	soMemRdCmdP0,
		stream< DmSts > &	siMemRdStsP0,
		stream< Axis< 512 > > &	siMemReadP0,
		stream< DmCmd > &	soMemWrCmdP0,
		stream< DmSts > &	siMemWrStsP0,
		stream< Axis< 512 > > &	soMemWriteP0
	)

Definition at line 48 of file mem_test_flash.cpp.

{
 
#pragma HLS INTERFACE ap_vld register port=sys_reset name=piSysReset
#pragma HLS INTERFACE ap_vld register port=DIAG_CTRL_IN name=piMMIO_diag_ctrl
#pragma HLS INTERFACE ap_ovld register port=DIAG_STAT_OUT name=poMMIO_diag_stat
#pragma HLS INTERFACE ap_ovld register port=debug_out name=poDebug
 
  // Bundling: SHELL / Role / Mem / Mp0 / Read Interface
#pragma HLS INTERFACE axis register both port=soMemRdCmdP0
#pragma HLS INTERFACE axis register both port=siMemRdStsP0
#pragma HLS INTERFACE axis register both port=siMemReadP0
 
#pragma HLS DATA_PACK variable=soMemRdCmdP0 instance=soMemRdCmdP0
#pragma HLS DATA_PACK variable=siMemRdStsP0 instance=siMemRdStsP0
 
  // Bundling: SHELL / Role / Mem / Mp0 / Write Interface
#pragma HLS INTERFACE axis register both port=soMemWrCmdP0
#pragma HLS INTERFACE axis register both port=siMemWrStsP0
#pragma HLS INTERFACE axis register both port=soMemWriteP0
 
#pragma HLS DATA_PACK variable=soMemWrCmdP0 instance=soMemWrCmdP0
#pragma HLS DATA_PACK variable=siMemWrStsP0 instance=siMemWrStsP0
 
 
 
  Axis<512>     memP0;
  DmSts         memRdStsP0;
  DmSts         memWrStsP0;
 
  //initalize 
  memP0.tdata = 0;
  memP0.tlast = 0;
  memP0.tkeep = 0;
 
 
  if(sys_reset == 1)
  {
    fsmState = FSM_IDLE;
    runContiniously = false;
    wasError = 0;
    //lastCheckedAddress = 0;
    lastCheckedAddress = MEM_END_ADDR + 1; //to stop the test
    currentPatternAdderss = 0;
    currentMemPattern = 0;
    patternWriteNum = 0;
    debugVec = 0;
    testPhase = PHASE_IDLE;
    timeoutCnt = 0;
    return;
  }
 
 
  switch(fsmState) {
 
    case FSM_IDLE:
      switch(DIAG_CTRL_IN) {
        case 0x3: //reserved --> idle
        case 0x0: //stay IDLE, stop test
          *DIAG_STAT_OUT = (0 << 1) | wasError;
          runContiniously = false;
          lastCheckedAddress = MEM_START_ADDR;
          break; 
        case 0x2: 
          runContiniously = true;
          //NO break
        case 0x1: //Run once
          if (lastCheckedAddress == MEM_START_ADDR)
          { // start new test
            wasError = 0;
            lastCheckedAddress = MEM_START_ADDR;
            fsmState = FSM_WR_PAT_CMD;
            *DIAG_STAT_OUT = 0b10;
            debugVec = 0;
            testPhase = PHASE_RAMP_WRITE;
            currentMemPattern = 0;
          } else if(lastCheckedAddress >= MEM_END_ADDR)
          {//checked space completely once 
 
            if(testPhase == PHASE_RAMP_WRITE)
            {
              testPhase = PHASE_RAMP_READ;
              lastCheckedAddress = MEM_START_ADDR;
              fsmState = FSM_RD_PAT_CMD;
              currentMemPattern = 0;
            } else if(testPhase == PHASE_RAMP_READ)
            {
              testPhase = PHASE_STRESS;
              lastCheckedAddress = MEM_START_ADDR;
              fsmState = FSM_WR_PAT_CMD;
              currentMemPattern = 0;
            } else if (runContiniously)
            {
              fsmState = FSM_WR_PAT_CMD;
              lastCheckedAddress = MEM_START_ADDR;
              currentMemPattern = 0;
              testPhase = PHASE_RAMP_WRITE;
              *DIAG_STAT_OUT = (1 << 1) | wasError;
            } else { //stay here
              fsmState = FSM_IDLE;
              *DIAG_STAT_OUT = (0 << 1) | wasError;
            }
          } else { //continue current run
 
            if(testPhase == PHASE_RAMP_READ)
            {
              fsmState = FSM_RD_PAT_CMD;
            } else {
              fsmState = FSM_WR_PAT_CMD;
            }
 
            *DIAG_STAT_OUT = (1 << 1) | wasError;
            if(testPhase == PHASE_STRESS)
            {
              currentMemPattern = 0;
            }
          }
          break;
      }
 
      //stop on error
      if(wasError == 1)
      {
        fsmState = FSM_IDLE;
        *DIAG_STAT_OUT = (0 << 1) | wasError;
      }
 
      //set current address
      if(lastCheckedAddress == MEM_START_ADDR)
      {
        currentPatternAdderss = MEM_START_ADDR;
      } else {
        currentPatternAdderss = lastCheckedAddress+1;
      }
      break;
 
    case FSM_WR_PAT_CMD:
      if (!soMemWrCmdP0.full()) {
        //-- Post a memory write command to SHELL/Mem/Mp0
        soMemWrCmdP0.write(DmCmd(currentPatternAdderss, CHECK_CHUNK_SIZE));
        patternWriteNum = 0;
        fsmState = FSM_WR_PAT_DATA;
      }
      break;
 
    case FSM_WR_PAT_DATA:
      if (!soMemWriteP0.full()) {
        //-- Assemble a memory word and write it to DRAM
        currentMemPattern++;
        memP0.tdata = (ap_uint<512>) (currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern);
        ap_uint<8> keepVal = 0xFF;
        memP0.tkeep = (ap_uint<64>) (keepVal, keepVal, keepVal, keepVal, keepVal, keepVal, keepVal, keepVal);
        //memP0.tkeep = (ap_uint<64>) (0xFF, 0xFF, 0xFF, 0xFF,0xFF, 0xFF, 0xFF, 0xFF);
 
        if(patternWriteNum == TRANSFERS_PER_CHUNK -1) 
        {
          memP0.tlast = 1;
          fsmState = FSM_WR_PAT_STS;
          timeoutCnt = 0;
        } else {
          memP0.tlast = 0;
        }
        soMemWriteP0.write(memP0);
        patternWriteNum++;
      }
      break;
 
    case FSM_WR_PAT_STS:
      if (!siMemWrStsP0.empty()) {
        //-- Get the memory write status for Mem/Mp0
        siMemWrStsP0.read(memWrStsP0);
        //latch errors
        debugVec |= (ap_uint<16>) STS_to_Vector(memWrStsP0);
 
        if(testPhase == PHASE_RAMP_WRITE)
        {
          fsmState = FSM_IDLE;
          debugVec |= ((ap_uint<16>) STS_to_Vector(memRdStsP0) )<< 8;
          lastCheckedAddress = currentPatternAdderss+CHECK_CHUNK_SIZE -1;
        } else {
          fsmState = FSM_RD_PAT_CMD;
          currentMemPattern = 0;
        }
      } else { 
        timeoutCnt++;
        if (timeoutCnt >= CYCLES_UNTIL_TIMEOUT)
        {
          wasError = 1;
          fsmState = FSM_IDLE;
        }
      }
 
      break;
 
    case FSM_RD_PAT_CMD:
      if (!soMemRdCmdP0.full()) {
        //-- Post a memory read command to SHELL/Mem/Mp0
        soMemRdCmdP0.write(DmCmd(currentPatternAdderss, CHECK_CHUNK_SIZE));
        fsmState = FSM_RD_PAT_DATA;
      }
      break;
 
    case FSM_RD_PAT_DATA:
      if (!siMemReadP0.empty()) {
        //-- Read a memory word from DRAM
        siMemReadP0.read(memP0);
        currentMemPattern++;
        if (memP0.tdata != ((ap_uint<512>) (currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern,currentMemPattern)) )
        {
          printf("error in pattern reading!\n");
          wasError = 1;
        }
        /*if (memP0.tkeep != (0xFF, 0xFF, 0xFF, 0xFF,0xFF, 0xFF, 0xFF, 0xFF))
          {
          printf("error in tkeep\n");
          }*/
        //I trust that there will be a tlast (so no counting)
        if (memP0.tlast == 1)
        {
          fsmState = FSM_RD_PAT_STS;
          timeoutCnt = 0;
        }
      }
      break;
 
    case FSM_RD_PAT_STS:
      if (!siMemRdStsP0.empty()) {
        //-- Get the memory read status for Mem/Mp0
        siMemRdStsP0.read(memRdStsP0);
        //latch errors
        debugVec |= ((ap_uint<16>) STS_to_Vector(memRdStsP0) )<< 8;
 
        if(testPhase == PHASE_RAMP_READ)
        {
          fsmState = FSM_IDLE;
          debugVec |= ((ap_uint<16>) STS_to_Vector(memRdStsP0) )<< 8;
          lastCheckedAddress = currentPatternAdderss+CHECK_CHUNK_SIZE -1;
        } else {
          fsmState = FSM_WR_ANTI_CMD;
          currentMemPattern = 0;
        }
      } else { 
        timeoutCnt++;
        if (timeoutCnt >= CYCLES_UNTIL_TIMEOUT)
        {
          wasError = 1;
          fsmState = FSM_IDLE;
        }
      }
      break;
 
    case FSM_WR_ANTI_CMD:
      if (!soMemWrCmdP0.full()) {
        //-- Post a memory write command to SHELL/Mem/Mp0
        soMemWrCmdP0.write(DmCmd(currentPatternAdderss, CHECK_CHUNK_SIZE));
        currentMemPattern = 0;
        patternWriteNum = 0;
        fsmState = FSM_WR_ANTI_DATA;
      }
      break;
 
    case FSM_WR_ANTI_DATA:
      if (!soMemWriteP0.full()) {
        //-- Assemble a memory word and write it to DRAM
        currentMemPattern++;
        ap_uint<64> currentAntiPattern = ~currentMemPattern;
        //debug 
        //printf("AntiPattern: 0x%llX\n", (uint64_t) currentAntiPattern);
 
        memP0.tdata = (currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern);
        ap_uint<8> keepVal = 0xFF;
        memP0.tkeep = (ap_uint<64>) (keepVal, keepVal, keepVal, keepVal, keepVal, keepVal, keepVal, keepVal);
        //memP0.tkeep = (0xFF, 0xFF, 0xFF, 0xFF,0xFF, 0xFF, 0xFF, 0xFF);
 
        if(patternWriteNum == TRANSFERS_PER_CHUNK -1) 
        {
          memP0.tlast = 1;
          fsmState = FSM_WR_ANTI_STS;
          timeoutCnt = 0;
        } else {
          memP0.tlast = 0;
        }
        soMemWriteP0.write(memP0);
        patternWriteNum++;
      }
      break;
 
    case FSM_WR_ANTI_STS:
      if (!siMemWrStsP0.empty()) {
        //-- Get the memory write status for Mem/Mp0
        siMemWrStsP0.read(memWrStsP0);
        //latch errors
        debugVec |= (ap_uint<16>) STS_to_Vector(memWrStsP0);
        fsmState = FSM_RD_ANTI_CMD;
      } else { 
        timeoutCnt++;
        if (timeoutCnt >= CYCLES_UNTIL_TIMEOUT)
        {
          wasError = 1;
          fsmState = FSM_IDLE;
        }
      }
      break;
 
    case FSM_RD_ANTI_CMD:
      if (!soMemRdCmdP0.full()) {
        //-- Post a memory read command to SHELL/Mem/Mp0
        soMemRdCmdP0.write(DmCmd(currentPatternAdderss, CHECK_CHUNK_SIZE));
        currentMemPattern = 0;
        fsmState = FSM_RD_ANTI_DATA;
      }
      break;
 
    case FSM_RD_ANTI_DATA:
      if (!siMemReadP0.empty()) {
        //-- Read a memory word from DRAM
        siMemReadP0.read(memP0);
        currentMemPattern++;
        ap_uint<64> currentAntiPattern = ~currentMemPattern;
 
        if (memP0.tdata != ((ap_uint<512>) (currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern,currentAntiPattern)) )
        {
          printf("error in antipattern reading!\n");
          wasError = 1;
        }
        /*if (memP0.tkeep != (0xFF, 0xFF, 0xFF, 0xFF,0xFF, 0xFF, 0xFF, 0xFF))
          {
          printf("error in tkeep\n");
          }*/
        //I trust that there will be a tlast (so no counting)
        if (memP0.tlast == 1)
        {
          fsmState = FSM_RD_ANTI_STS;
          timeoutCnt = 0;
        }
      }
      break;
 
    case FSM_RD_ANTI_STS:
      if (!siMemRdStsP0.empty()) {
        //-- Get the memory read status for Mem/Mp0
        siMemRdStsP0.read(memRdStsP0);
        //latch errors
        debugVec |= ((ap_uint<16>) STS_to_Vector(memRdStsP0) )<< 8;
        lastCheckedAddress = currentPatternAdderss+CHECK_CHUNK_SIZE -1;
        fsmState = FSM_IDLE;
      } else { 
        timeoutCnt++;
        if (timeoutCnt >= CYCLES_UNTIL_TIMEOUT)
        {
          wasError = 1;
          fsmState = FSM_IDLE;
        }
      }
      break;
 
  }  // End: switch
 
  *debug_out = debugVec;
 
  return;
}