cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
Role.vhdl
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1 -- *
2 -- * cloudFPGA
3 -- * Copyright IBM Research, All Rights Reserved
4 -- * =============================================
5 -- * Created: Apr 2019
6 -- * Authors: FAB, WEI, NGL
7 -- *
8 -- * Description:
9 -- * ROLE template for Themisto SRA
10 -- *
11 
12 --******************************************************************************
13 --** CONTEXT CLAUSE ** FMKU60 ROLE(Flash)
14 --******************************************************************************
15 library IEEE;
16 use IEEE.std_logic_1164.all;
17 use IEEE.numeric_std.all;
18 
19 library UNISIM;
20 use UNISIM.vcomponents.all;
21 
22 -- library XIL_DEFAULTLIB;
23 -- use XIL_DEFAULTLIB.all;
24 
25 
26 --******************************************************************************
27 --** ENTITY ** FMKU60 ROLE
28 --******************************************************************************
29 
30 entity Role_Themisto is
31  generic (
32  gAxiIdWidth : integer := 8
33  );
34  port (
35 
36  --------------------------------------------------------
37  -- SHELL / Global Input Clock and Reset Interface
38  --------------------------------------------------------
39  piSHL_156_25Clk : in std_ulogic;
40  piSHL_156_25Rst : in std_ulogic;
41  -- LY7 Enable and Reset
42  piMMIO_Ly7_Rst : in std_ulogic;
43  piMMIO_Ly7_En : in std_ulogic;
44 
45  ------------------------------------------------------
46  -- SHELL / Role / Nts0 / Udp Interface
47  ------------------------------------------------------
48  ---- Input AXI-Write Stream Interface ----------
49  siNRC_Udp_Data_tdata : in std_ulogic_vector( 63 downto 0);
50  siNRC_Udp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
51  siNRC_Udp_Data_tvalid : in std_ulogic;
52  siNRC_Udp_Data_tlast : in std_ulogic;
53  siNRC_Udp_Data_tready : out std_ulogic;
54  ---- Output AXI-Write Stream Interface ---------
55  soNRC_Udp_Data_tdata : out std_ulogic_vector( 63 downto 0);
56  soNRC_Udp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
57  soNRC_Udp_Data_tvalid : out std_ulogic;
58  soNRC_Udp_Data_tlast : out std_ulogic;
59  soNRC_Udp_Data_tready : in std_ulogic;
60  -- Open Port vector
61  poROL_Nrc_Udp_Rx_ports : out std_ulogic_vector( 31 downto 0);
62  -- ROLE <-> NRC Meta Interface
63  soROLE_Nrc_Udp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
64  soROLE_Nrc_Udp_Meta_TVALID : out std_ulogic;
65  soROLE_Nrc_Udp_Meta_TREADY : in std_ulogic;
66  soROLE_Nrc_Udp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
67  soROLE_Nrc_Udp_Meta_TLAST : out std_ulogic;
68  siNRC_Role_Udp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
69  siNRC_Role_Udp_Meta_TVALID : in std_ulogic;
70  siNRC_Role_Udp_Meta_TREADY : out std_ulogic;
71  siNRC_Role_Udp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
72  siNRC_Role_Udp_Meta_TLAST : in std_ulogic;
73 
74  ------------------------------------------------------
75  -- SHELL / Role / Nts0 / Tcp Interface
76  ------------------------------------------------------
77  ---- Input AXI-Write Stream Interface ----------
78  siNRC_Tcp_Data_tdata : in std_ulogic_vector( 63 downto 0);
79  siNRC_Tcp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
80  siNRC_Tcp_Data_tvalid : in std_ulogic;
81  siNRC_Tcp_Data_tlast : in std_ulogic;
82  siNRC_Tcp_Data_tready : out std_ulogic;
83  ---- Output AXI-Write Stream Interface ---------
84  soNRC_Tcp_Data_tdata : out std_ulogic_vector( 63 downto 0);
85  soNRC_Tcp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
86  soNRC_Tcp_Data_tvalid : out std_ulogic;
87  soNRC_Tcp_Data_tlast : out std_ulogic;
88  soNRC_Tcp_Data_tready : in std_ulogic;
89  -- Open Port vector
90  poROL_Nrc_Tcp_Rx_ports : out std_ulogic_vector( 31 downto 0);
91  -- ROLE <-> NRC Meta Interface
92  soROLE_Nrc_Tcp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
93  soROLE_Nrc_Tcp_Meta_TVALID : out std_ulogic;
94  soROLE_Nrc_Tcp_Meta_TREADY : in std_ulogic;
95  soROLE_Nrc_Tcp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
96  soROLE_Nrc_Tcp_Meta_TLAST : out std_ulogic;
97  siNRC_Role_Tcp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
98  siNRC_Role_Tcp_Meta_TVALID : in std_ulogic;
99  siNRC_Role_Tcp_Meta_TREADY : out std_ulogic;
100  siNRC_Role_Tcp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
101  siNRC_Role_Tcp_Meta_TLAST : in std_ulogic;
102 
103 
104  --------------------------------------------------------
105  -- SHELL / Mem / Mp0 Interface
106  --------------------------------------------------------
107  ---- Memory Port #0 / S2MM-AXIS ----------------
108  ------ Stream Read Command ---------
109  soMEM_Mp0_RdCmd_tdata : out std_ulogic_vector( 79 downto 0);
110  soMEM_Mp0_RdCmd_tvalid : out std_ulogic;
111  soMEM_Mp0_RdCmd_tready : in std_ulogic;
112  ------ Stream Read Status ----------
113  siMEM_Mp0_RdSts_tdata : in std_ulogic_vector( 7 downto 0);
114  siMEM_Mp0_RdSts_tvalid : in std_ulogic;
115  siMEM_Mp0_RdSts_tready : out std_ulogic;
116  ------ Stream Data Input Channel ---
117  siMEM_Mp0_Read_tdata : in std_ulogic_vector(511 downto 0);
118  siMEM_Mp0_Read_tkeep : in std_ulogic_vector( 63 downto 0);
119  siMEM_Mp0_Read_tlast : in std_ulogic;
120  siMEM_Mp0_Read_tvalid : in std_ulogic;
121  siMEM_Mp0_Read_tready : out std_ulogic;
122  ------ Stream Write Command --------
123  soMEM_Mp0_WrCmd_tdata : out std_ulogic_vector( 79 downto 0);
124  soMEM_Mp0_WrCmd_tvalid : out std_ulogic;
125  soMEM_Mp0_WrCmd_tready : in std_ulogic;
126  ------ Stream Write Status ---------
127  siMEM_Mp0_WrSts_tdata : in std_ulogic_vector( 7 downto 0);
128  siMEM_Mp0_WrSts_tvalid : in std_ulogic;
129  siMEM_Mp0_WrSts_tready : out std_ulogic;
130  ------ Stream Data Output Channel --
131  soMEM_Mp0_Write_tdata : out std_ulogic_vector(511 downto 0);
132  soMEM_Mp0_Write_tkeep : out std_ulogic_vector( 63 downto 0);
133  soMEM_Mp0_Write_tlast : out std_ulogic;
134  soMEM_Mp0_Write_tvalid : out std_ulogic;
135  soMEM_Mp0_Write_tready : in std_ulogic;
136 
137 -- --------------------------------------------------------
138 -- -- SHELL / Mem / Mp0 Interface
139 -- --------------------------------------------------------
140 -- moMEM_Mp0_AWID : out std_ulogic_vector(3 downto 0);
141 -- moMEM_Mp0_AWADDR : out std_ulogic_vector(32 downto 0);
142 -- moMEM_Mp0_AWLEN : out std_ulogic_vector(7 downto 0);
143 -- moMEM_Mp0_AWSIZE : out std_ulogic_vector(2 downto 0);
144 -- moMEM_Mp0_AWBURST : out std_ulogic_vector(1 downto 0);
145 -- moMEM_Mp0_AWVALID : out std_ulogic;
146 -- moMEM_Mp0_AWREADY : in std_ulogic;
147 -- moMEM_Mp0_WDATA : out std_ulogic_vector(511 downto 0);
148 -- moMEM_Mp0_WSTRB : out std_ulogic_vector(63 downto 0);
149 -- moMEM_Mp0_WLAST : out std_ulogic;
150 -- moMEM_Mp0_WVALID : out std_ulogic;
151 -- moMEM_Mp0_WREADY : in std_ulogic;
152 -- moMEM_Mp0_BID : in std_ulogic_vector(3 downto 0);
153 -- moMEM_Mp0_BRESP : in std_ulogic_vector(1 downto 0);
154 -- moMEM_Mp0_BVALID : in std_ulogic;
155 -- moMEM_Mp0_BREADY : out std_ulogic;
156 -- moMEM_Mp0_ARID : out std_ulogic_vector(3 downto 0);
157 -- moMEM_Mp0_ARADDR : out std_ulogic_vector(32 downto 0);
158 -- moMEM_Mp0_ARLEN : out std_ulogic_vector(7 downto 0);
159 -- moMEM_Mp0_ARSIZE : out std_ulogic_vector(2 downto 0);
160 -- moMEM_Mp0_ARBURST : out std_ulogic_vector(1 downto 0);
161 -- moMEM_Mp0_ARVALID : out std_ulogic;
162 -- moMEM_Mp0_ARREADY : in std_ulogic;
163 -- moMEM_Mp0_RID : in std_ulogic_vector(3 downto 0);
164 -- moMEM_Mp0_RDATA : in std_ulogic_vector(511 downto 0);
165 -- moMEM_Mp0_RRESP : in std_ulogic_vector(1 downto 0);
166 -- moMEM_Mp0_RLAST : in std_ulogic;
167 -- moMEM_Mp0_RVALID : in std_ulogic;
168 -- moMEM_Mp0_RREADY : out std_ulogic;
169 
170 
171  --------------------------------------------------------
172  -- SHELL / Mem / Mp1 Interface
173  --------------------------------------------------------
174  moMEM_Mp1_AWID : out std_ulogic_vector(gAxiIdWidth-1 downto 0);
175  moMEM_Mp1_AWADDR : out std_ulogic_vector(32 downto 0);
176  moMEM_Mp1_AWLEN : out std_ulogic_vector(7 downto 0);
177  moMEM_Mp1_AWSIZE : out std_ulogic_vector(2 downto 0);
178  moMEM_Mp1_AWBURST : out std_ulogic_vector(1 downto 0);
179  --moMEM_Mp1_AWLOCK : out std_ulogic_vector(1 downto 0);
180  --moMEM_Mp1_AWREGION : out std_ulogic_vector(3 downto 0);
181  --moMEM_Mp1_AWCACHE : out std_ulogic_vector(3 downto 0);
182  --moMEM_Mp1_AWPROT : out std_ulogic_vector(2 downto 0);
183  --moMEM_Mp1_AWQOS : out std_ulogic_vector(3 downto 0);
184  moMEM_Mp1_AWVALID : out std_ulogic;
185  moMEM_Mp1_AWREADY : in std_ulogic;
186  moMEM_Mp1_WDATA : out std_ulogic_vector(511 downto 0);
187  moMEM_Mp1_WSTRB : out std_ulogic_vector(63 downto 0);
188  moMEM_Mp1_WLAST : out std_ulogic;
189  moMEM_Mp1_WID : out std_ulogic_vector(3 downto 0);
190  moMEM_Mp1_WVALID : out std_ulogic;
191  moMEM_Mp1_WREADY : in std_ulogic;
192  moMEM_Mp1_BID : in std_ulogic_vector(gAxiIdWidth-1 downto 0);
193  moMEM_Mp1_BRESP : in std_ulogic_vector(1 downto 0);
194  moMEM_Mp1_BVALID : in std_ulogic;
195  moMEM_Mp1_BREADY : out std_ulogic;
196  moMEM_Mp1_ARID : out std_ulogic_vector(gAxiIdWidth-1 downto 0);
197  moMEM_Mp1_ARADDR : out std_ulogic_vector(32 downto 0);
198  moMEM_Mp1_ARLEN : out std_ulogic_vector(7 downto 0);
199  moMEM_Mp1_ARSIZE : out std_ulogic_vector(2 downto 0);
200  moMEM_Mp1_ARBURST : out std_ulogic_vector(1 downto 0);
201  --moMEM_Mp1_ARLOCK : out std_ulogic_vector(1 downto 0);
202  --moMEM_Mp1_ARREGION : out std_ulogic_vector(3 downto 0);
203  --moMEM_Mp1_ARCACHE : out std_ulogic_vector(3 downto 0);
204  --moMEM_Mp1_ARPROT : out std_ulogic_vector(2 downto 0);
205  --moMEM_Mp1_ARQOS : out std_ulogic_vector(3 downto 0);
206  moMEM_Mp1_ARVALID : out std_ulogic;
207  moMEM_Mp1_ARREADY : in std_ulogic;
208  moMEM_Mp1_RID : in std_ulogic_vector(gAxiIdWidth-1 downto 0);
209  moMEM_Mp1_RDATA : in std_ulogic_vector(511 downto 0);
210  moMEM_Mp1_RRESP : in std_ulogic_vector(1 downto 0);
211  moMEM_Mp1_RLAST : in std_ulogic;
212  moMEM_Mp1_RVALID : in std_ulogic;
213  moMEM_Mp1_RREADY : out std_ulogic;
214 
215  ---- [APP_RDROL] -------------------
216  -- to be use as ROLE VERSION IDENTIFICATION --
217  poSHL_Mmio_RdReg : out std_ulogic_vector( 15 downto 0);
218 
219  --------------------------------------------------------
220  -- TOP : Secondary Clock (Asynchronous)
221  --------------------------------------------------------
222  piTOP_250_00Clk : in std_ulogic; -- Freerunning
223 
224  ------------------------------------------------
225  -- SMC Interface
226  ------------------------------------------------
227  piFMC_ROLE_rank : in std_logic_vector(31 downto 0);
228  piFMC_ROLE_size : in std_logic_vector(31 downto 0);
229 
230  poVoid : out std_ulogic
231 
232  );
233 
234 end Role_Themisto;
235 
236 
237 -- *****************************************************************************
238 -- ** ARCHITECTURE ** FLASH of ROLE
239 -- *****************************************************************************
240 
241 architecture Flash of Role_Themisto is
242 
243  constant cUSE_DEPRECATED_DIRECTIVES : boolean := false;
244 
245  --============================================================================
246  -- SIGNAL DECLARATIONS
247  --============================================================================
248 
249 
250  -- signal EMIF_inv : std_logic_vector(7 downto 0);
251 
252  -- I hate Vivado HLS
253  signal sReadTlastAsVector : std_logic_vector(0 downto 0);
254  signal sWriteTlastAsVector : std_logic_vector(0 downto 0);
255  signal sResetAsVector : std_logic_vector(0 downto 0);
256 
257  signal sMetaOutTlastAsVector_Udp : std_logic_vector(0 downto 0);
258  signal sMetaInTlastAsVector_Udp : std_logic_vector(0 downto 0);
259  signal sMetaOutTlastAsVector_Tcp : std_logic_vector(0 downto 0);
260  signal sMetaInTlastAsVector_Tcp : std_logic_vector(0 downto 0);
261 
262  signal sUdpPostCnt : std_ulogic_vector(9 downto 0);
263  signal sTcpPostCnt : std_ulogic_vector(9 downto 0);
264 
265  --signal sMemTestDebugOut : std_logic_vector(15 downto 0);
266 
267  --============================================================================
268  -- VARIABLE DECLARATIONS
269  --============================================================================
270 
271  --===========================================================================
272  --== COMPONENT DECLARATIONS
273  --===========================================================================
274  component Median_BlurApplication is
275  port (
276  ------------------------------------------------------
277  -- From SHELL / Clock and Reset
278  ------------------------------------------------------
279  ap_clk : in std_logic;
280  ap_rst_n : in std_logic;
281  ap_start : in std_logic;
282 
283  -- rank and size
284  piFMC_ROL_rank_V : in std_logic_vector (31 downto 0);
285  --piSMC_ROL_rank_V_ap_vld : in std_logic;
286  piFMC_ROL_size_V : in std_logic_vector (31 downto 0);
287  --piSMC_ROL_size_V_ap_vld : in std_logic;
288  --------------------------------------------------------
289  -- From SHELL / Udp-Tcp Data Interfaces
290  --------------------------------------------------------
291  siSHL_This_Data_tdata : in std_logic_vector( 63 downto 0);
292  siSHL_This_Data_tkeep : in std_logic_vector( 7 downto 0);
293  siSHL_This_Data_tlast : in std_logic;
294  siSHL_This_Data_tvalid : in std_logic;
295  siSHL_This_Data_tready : out std_logic;
296  --------------------------------------------------------
297  -- To SHELL / Udp-Tcp Data Interfaces
298  --------------------------------------------------------
299  soTHIS_Shl_Data_tdata : out std_logic_vector( 63 downto 0);
300  soTHIS_Shl_Data_tkeep : out std_logic_vector( 7 downto 0);
301  soTHIS_Shl_Data_tlast : out std_logic;
302  soTHIS_Shl_Data_tvalid : out std_logic;
303  soTHIS_Shl_Data_tready : in std_logic;
304  -- NRC Meta and Ports
305  siNrc_meta_TDATA : in std_logic_vector (63 downto 0);
306  siNrc_meta_TVALID : in std_logic;
307  siNrc_meta_TREADY : out std_logic;
308  siNrc_meta_TKEEP : in std_logic_vector (7 downto 0);
309  siNrc_meta_TLAST : in std_logic_vector (0 downto 0);
310 
311  soNrc_meta_TDATA : out std_logic_vector (63 downto 0);
312  soNrc_meta_TVALID : out std_logic;
313  soNrc_meta_TREADY : in std_logic;
314  soNrc_meta_TKEEP : out std_logic_vector (7 downto 0);
315  soNrc_meta_TLAST : out std_logic_vector (0 downto 0);
316 
317  poROL_NRC_Rx_ports_V : out std_logic_vector (31 downto 0);
318  poROL_NRC_Rx_ports_V_ap_vld : out std_logic
319 
320 
321 
322 
323 
324  --------------------------------------------------------
325  -- SHELL / Mem / Mp0 Interface / Start Component
326  --------------------------------------------------------
327  ; -- semicolumn for syntax correctness when Mp1 is instantiated
328 -- moMEM_Mp0_AWID : out std_ulogic_vector(3 downto 0);
329 -- moMEM_Mp0_AWADDR : out std_ulogic_vector(32 downto 0);
330 -- moMEM_Mp0_AWLEN : out std_ulogic_vector(7 downto 0);
331 -- moMEM_Mp0_AWSIZE : out std_ulogic_vector(2 downto 0);
332 -- moMEM_Mp0_AWBURST : out std_ulogic_vector(1 downto 0);
333 -- moMEM_Mp0_AWVALID : out std_ulogic;
334 -- moMEM_Mp0_AWREADY : in std_ulogic;
335 -- moMEM_Mp0_WDATA : out std_ulogic_vector(511 downto 0);
336 -- moMEM_Mp0_WSTRB : out std_ulogic_vector(63 downto 0);
337 -- moMEM_Mp0_WLAST : out std_ulogic;
338 -- moMEM_Mp0_WVALID : out std_ulogic;
339 -- moMEM_Mp0_WREADY : in std_ulogic;
340 -- moMEM_Mp0_BID : in std_ulogic_vector(3 downto 0);
341 -- moMEM_Mp0_BRESP : in std_ulogic_vector(1 downto 0);
342 -- moMEM_Mp0_BVALID : in std_ulogic;
343 -- moMEM_Mp0_BREADY : out std_ulogic;
344 -- moMEM_Mp0_ARID : out std_ulogic_vector(3 downto 0);
345 -- moMEM_Mp0_ARADDR : out std_ulogic_vector(32 downto 0);
346 -- moMEM_Mp0_ARLEN : out std_ulogic_vector(7 downto 0);
347 -- moMEM_Mp0_ARSIZE : out std_ulogic_vector(2 downto 0);
348 -- moMEM_Mp0_ARBURST : out std_ulogic_vector(1 downto 0);
349 -- moMEM_Mp0_ARVALID : out std_ulogic;
350 -- moMEM_Mp0_ARREADY : in std_ulogic;
351 -- moMEM_Mp0_RID : in std_ulogic_vector(3 downto 0);
352 -- moMEM_Mp0_RDATA : in std_ulogic_vector(511 downto 0);
353 -- moMEM_Mp0_RRESP : in std_ulogic_vector(1 downto 0);
354 -- moMEM_Mp0_RLAST : in std_ulogic;
355 -- moMEM_Mp0_RVALID : in std_ulogic;
356 -- moMEM_Mp0_RREADY : out std_ulogic;
357 
358 -- ---- Axi4-Stream Read Command -----
359 -- soMemRdCmdP0_TDATA : out std_logic_vector( 79 downto 0);
360 -- soMemRdCmdP0_TVALID : out std_logic;
361 -- soMemRdCmdP0_TREADY : in std_logic;
362 -- ---- Axi4-Stream Read Status ------
363 -- siMemRdStsP0_TDATA : in std_logic_vector( 7 downto 0);
364 -- siMemRdStsP0_TVALID : in std_logic;
365 -- siMemRdStsP0_TREADY : out std_logic;
366 -- ---- Axi4-Stream Data Output Channel
367 -- siMemReadP0_TDATA : in std_logic_vector(511 downto 0);
368 -- siMemReadP0_TKEEP : in std_logic_vector( 63 downto 0);
369 -- siMemReadP0_TLAST : in std_logic_vector( 0 downto 0);
370 -- siMemReadP0_TVALID : in std_logic;
371 -- siMemReadP0_TREADY : out std_logic;
372  ---- Axi4-Stream Write Command ----
373  soMemWrCmdP0_TDATA : out std_logic_vector( 79 downto 0);
374  soMemWrCmdP0_TVALID : out std_logic;
375  soMemWrCmdP0_TREADY : in std_logic;
376  ---- Axi4-Stream Write Status -----
377  siMemWrStsP0_TDATA : in std_logic_vector( 7 downto 0);
378  siMemWrStsP0_TVALID : in std_logic;
379  siMemWrStsP0_TREADY : out std_logic;
380  ---- Axi4-Stream Write Command ----
381  soMemWriteP0_TDATA : out std_logic_vector(511 downto 0);
382  soMemWriteP0_TKEEP : out std_logic_vector( 63 downto 0);
383  soMemWriteP0_TLAST : out std_logic;
384  soMemWriteP0_TVALID : out std_logic;
385  soMemWriteP0_TREADY : in std_logic;
386 
387 
388 
389  --------------------------------------------------------
390  -- SHELL / Mem / Mp1 Interface / Start Component
391  --------------------------------------------------------
392  --m_axi_moMEM_Mp1_AWID : out std_ulogic_vector(gAxiIdWidth-1 downto 0);
393  m_axi_moMEM_Mp1_AWADDR : out std_ulogic_vector(63 downto 0);
394  m_axi_moMEM_Mp1_AWLEN : out std_ulogic_vector(7 downto 0);
395  m_axi_moMEM_Mp1_AWSIZE : out std_ulogic_vector(2 downto 0);
396  m_axi_moMEM_Mp1_AWBURST : out std_ulogic_vector(1 downto 0);
397  m_axi_moMEM_Mp1_AWLOCK : out std_ulogic_vector(1 downto 0);
398  m_axi_moMEM_Mp1_AWREGION : out std_ulogic_vector(3 downto 0);
399  --m_axi_moMEM_Mp1_AWUSER : out std_ulogic_vector(0 downto 0);
400  m_axi_moMEM_Mp1_AWCACHE : out std_ulogic_vector(3 downto 0);
401  m_axi_moMEM_Mp1_AWPROT : out std_ulogic_vector(2 downto 0);
402  m_axi_moMEM_Mp1_AWQOS : out std_ulogic_vector(3 downto 0);
403  m_axi_moMEM_Mp1_AWVALID : out std_ulogic;
404  m_axi_moMEM_Mp1_AWREADY : in std_ulogic;
405  m_axi_moMEM_Mp1_WDATA : out std_ulogic_vector(511 downto 0);
406  m_axi_moMEM_Mp1_WSTRB : out std_ulogic_vector(63 downto 0);
407  m_axi_moMEM_Mp1_WLAST : out std_ulogic;
408  --m_axi_moMEM_Mp1_WID : out std_ulogic_vector(gAxiIdWidth-1 downto 0);
409  --m_axi_moMEM_Mp1_WUSER : out std_ulogic_vector(0 downto 0);
410  m_axi_moMEM_Mp1_WVALID : out std_ulogic;
411  m_axi_moMEM_Mp1_WREADY : in std_ulogic;
412  --m_axi_moMEM_Mp1_BID : in std_ulogic_vector(gAxiIdWidth-1 downto 0);
413  --m_axi_moMEM_Mp1_BUSER : in std_ulogic_vector(0 downto 0);
414  m_axi_moMEM_Mp1_BRESP : in std_ulogic_vector(1 downto 0);
415  m_axi_moMEM_Mp1_BVALID : in std_ulogic;
416  m_axi_moMEM_Mp1_BREADY : out std_ulogic;
417  --m_axi_moMEM_Mp1_ARID : out std_ulogic_vector(gAxiIdWidth-1 downto 0);
418  m_axi_moMEM_Mp1_ARADDR : out std_ulogic_vector(63 downto 0);
419  m_axi_moMEM_Mp1_ARLEN : out std_ulogic_vector(7 downto 0);
420  m_axi_moMEM_Mp1_ARSIZE : out std_ulogic_vector(2 downto 0);
421  m_axi_moMEM_Mp1_ARBURST : out std_ulogic_vector(1 downto 0);
422  m_axi_moMEM_Mp1_ARLOCK : out std_ulogic_vector(1 downto 0);
423  m_axi_moMEM_mp1_ARREGION : out std_ulogic_vector(3 downto 0);
424  --m_axi_moMEM_mp1_ARUSER : out std_ulogic_vector(0 downto 0);
425  m_axi_moMEM_mp1_ARCACHE : out std_ulogic_vector(3 downto 0);
426  m_axi_moMEM_mp1_ARPROT : out std_ulogic_vector(2 downto 0);
427  m_axi_moMEM_mp1_ARQOS : out std_ulogic_vector(3 downto 0);
428  m_axi_moMEM_Mp1_ARVALID : out std_ulogic;
429  m_axi_moMEM_Mp1_ARREADY : in std_ulogic;
430  --m_axi_moMEM_Mp1_RID : in std_ulogic_vector(gAxiIdWidth-1 downto 0);
431  --m_axi_moMEM_Mp1_RUSER : in std_ulogic_vector(0 downto 0);
432  m_axi_moMEM_Mp1_RDATA : in std_ulogic_vector(511 downto 0);
433  m_axi_moMEM_Mp1_RRESP : in std_ulogic_vector(1 downto 0);
434  m_axi_moMEM_Mp1_RLAST : in std_ulogic;
435  m_axi_moMEM_Mp1_RVALID : in std_ulogic;
436  m_axi_moMEM_Mp1_RREADY : out std_ulogic;
437  lcl_mem0_v : in std_ulogic_vector(63 downto 0);
438  lcl_mem1_v : in std_ulogic_vector(63 downto 0)
439  --------------------------------------------------------
440  -- SHELL / Mem / Mp1 Interface / End Component
441  --------------------------------------------------------
442 
443  );
444  end component Median_BlurApplication;
445 
446 
447 
448  --===========================================================================
449  --== FUNCTION DECLARATIONS [TODO-Move to a package]
450  --===========================================================================
451  function fVectorize(s: std_logic) return std_logic_vector is
452  variable v: std_logic_vector(0 downto 0);
453  begin
454  v(0) := s;
455  return v;
456  end fVectorize;
457 
458  function fScalarize(v: in std_logic_vector) return std_ulogic is
459  begin
460  assert v'length = 1
461  report "scalarize: output port must be single bit!"
462  severity FAILURE;
463  return v(v'LEFT);
464  end;
465 
466 
467 --################################################################################
468 --# #
469 --# ##### #### #### # # #
470 --# # # # # # # # # #
471 --# # # # # # # ### #
472 --# ##### # # # # # #
473 --# # # # # # # # #
474 --# # # # # # # # #
475 --# ##### #### #### # #
476 --# #
477 --################################################################################
478 
479 begin
480 
481  --poSHL_Mmio_RdReg <= sMemTestDebugOut when (unsigned(piSHL_Mmio_WrReg) /= 0) else
482  -- x"BEEF";
483  -- to be use as ROLE VERSION IDENTIFICATION --
484  poSHL_Mmio_RdReg <= x"BEEF";
485 
486 
487  --################################################################################
488  --# #
489  --# # # ##### ###### ##### #
490  --# # # # # # # # # ##### ##### #
491  --# # # # # # # # # # # # # #
492  --# # # # # ###### ####### ##### ##### #
493  --# # # # # # # # # # #
494  --# ####### ##### # # # # # #
495  --# #
496  --################################################################################
497 
498  -- gUdpAppFlashDepre : if cUSE_DEPRECATED_DIRECTIVES generate --TODO
499 
500  -- begin
501 
502  sMetaInTlastAsVector_Udp(0) <= siNRC_Role_Udp_Meta_TLAST;
503  soROLE_Nrc_Udp_Meta_TLAST <= sMetaOutTlastAsVector_Udp(0);
504 
505  UAF: Median_BlurApplication
506  port map (
507 
508  ------------------------------------------------------
509  -- From SHELL / Clock and Reset
510  ------------------------------------------------------
511  ap_clk => piSHL_156_25Clk,
512  ap_rst_n => (not piMMIO_Ly7_Rst),
513  ap_start => piMMIO_Ly7_En,
514 
515  piFMC_ROL_rank_V => piFMC_ROLE_rank,
516  --piFMC_ROL_rank_V_ap_vld => '1',
517  piFMC_ROL_size_V => piFMC_ROLE_size,
518  --piFMC_ROL_size_V_ap_vld => '1',
519  --------------------------------------------------------
520  -- From SHELL / Udp Data Interfaces
521  --------------------------------------------------------
522  siSHL_This_Data_tdata => siNRC_Udp_Data_tdata,
523  siSHL_This_Data_tkeep => siNRC_Udp_Data_tkeep,
524  siSHL_This_Data_tlast => siNRC_Udp_Data_tlast,
525  siSHL_This_Data_tvalid => siNRC_Udp_Data_tvalid,
526  siSHL_This_Data_tready => siNRC_Udp_Data_tready,
527  --------------------------------------------------------
528  -- To SHELL / Udp Data Interfaces
529  --------------------------------------------------------
530  soTHIS_Shl_Data_tdata => soNRC_Udp_Data_tdata,
531  soTHIS_Shl_Data_tkeep => soNRC_Udp_Data_tkeep,
532  soTHIS_Shl_Data_tlast => soNRC_Udp_Data_tlast,
533  soTHIS_Shl_Data_tvalid => soNRC_Udp_Data_tvalid,
534  soTHIS_Shl_Data_tready => soNRC_Udp_Data_tready,
535 
536  siNrc_meta_TDATA => siNRC_Role_Udp_Meta_TDATA,
537  siNrc_meta_TVALID => siNRC_Role_Udp_Meta_TVALID,
538  siNrc_meta_TREADY => siNRC_Role_Udp_Meta_TREADY,
539  siNrc_meta_TKEEP => siNRC_Role_Udp_Meta_TKEEP,
540  siNrc_meta_TLAST => sMetaInTlastAsVector_Udp,
541 
542  soNrc_meta_TDATA => soROLE_Nrc_Udp_Meta_TDATA,
543  soNrc_meta_TVALID => soROLE_Nrc_Udp_Meta_TVALID,
544  soNrc_meta_TREADY => soROLE_Nrc_Udp_Meta_TREADY,
545  soNrc_meta_TKEEP => soROLE_Nrc_Udp_Meta_TKEEP,
546  soNrc_meta_TLAST => sMetaOutTlastAsVector_Udp,
547 
548  poROL_NRC_Rx_ports_V => poROL_Nrc_Udp_Rx_ports
549  --poROL_NRC_Udp_Rx_ports_V_ap_vld => '1'
550 
551  --------------------------------------------------------
552  -- SHELL / Mem / Mp0 Interface / Start in UAF
553  --------------------------------------------------------
554  , -- comma for syntax correctness when Mp1 is instantiated
555 -- m_axi_card_mem0_araddr => moMEM_Mp0_ARADDR,
556 -- m_axi_card_mem0_arburst => moMEM_Mp0_ARBURST,
557 -- m_axi_card_mem0_arcache => open, -- m_axi_card_mem0_arcache,
558 -- m_axi_card_mem0_arid => moMEM_Mp0_ARID( 0 DOWNTO 0),--SR# 10394170 : out std_ulogic_vector(3 downto 0);
559 -- m_axi_card_mem0_arlen => moMEM_Mp0_ARLEN,
560 -- m_axi_card_mem0_arlock => open, -- m_axi_card_mem0_arlock,
561 -- m_axi_card_mem0_arprot => open, -- m_axi_card_mem0_arprot,
562 -- m_axi_card_mem0_arqos => open, -- m_axi_card_mem0_arqos,
563 -- m_axi_card_mem0_arready => moMEM_Mp0_ARREADY,
564 -- m_axi_card_mem0_arregion => open, -- m_axi_card_mem0_arregion,
565 -- m_axi_card_mem0_arsize => moMEM_Mp0_ARSIZE,
566 -- m_axi_card_mem0_aruser => open, -- m_axi_card_mem0_aruser,
567 -- m_axi_card_mem0_arvalid => moMEM_Mp0_ARVALID,
568 -- m_axi_card_mem0_awaddr => moMEM_Mp0_AWADDR,
569 -- m_axi_card_mem0_awburst => moMEM_Mp0_AWBURST,
570 -- m_axi_card_mem0_awcache => open, -- m_axi_card_mem0_awcache,
571 -- m_axi_card_mem0_awid => moMEM_Mp0_AWID(0 DOWNTO 0),--SR# 10394170 : out std_ulogic_vector(3 downto 0);
572 -- m_axi_card_mem0_awlen => moMEM_Mp0_AWLEN,
573 -- m_axi_card_mem0_awlock => open, -- m_axi_card_mem0_awlock,
574 -- m_axi_card_mem0_awprot => open, -- m_axi_card_mem0_awprot,
575 -- m_axi_card_mem0_awqos => open, -- m_axi_card_mem0_awqos,
576 -- m_axi_card_mem0_awready => moMEM_Mp0_AWREADY,
577 -- m_axi_card_mem0_awregion => open, -- m_axi_card_mem0_awregion,
578 -- m_axi_card_mem0_awsize => moMEM_Mp0_AWSIZE,
579 -- m_axi_card_mem0_awuser => open, -- m_axi_card_mem0_awuser,
580 -- m_axi_card_mem0_awvalid => moMEM_Mp0_AWVALID,
581 -- m_axi_card_mem0_bid => moMEM_Mp0_BID(0 DOWNTO 0),--SR# 10394170 : in std_ulogic_vector(3 downto 0);
582 -- m_axi_card_mem0_bready => moMEM_Mp0_BREADY,
583 -- m_axi_card_mem0_bresp => moMEM_Mp0_BRESP,
584 -- m_axi_card_mem0_buser =>open, -- m_axi_card_mem0_buser,
585 -- m_axi_card_mem0_bvalid => moMEM_Mp0_BVALID,
586 -- m_axi_card_mem0_rdata => moMEM_Mp0_RDATA,
587 -- m_axi_card_mem0_rid => moMEM_Mp0_RID(0 DOWNTO 0),--SR# 10394170 : in std_ulogic_vector(3 downto 0);
588 -- m_axi_card_mem0_rlast => moMEM_Mp0_RLAST,
589 -- m_axi_card_mem0_rready => moMEM_Mp0_RREADY,
590 -- m_axi_card_mem0_rresp => moMEM_Mp0_RRESP,
591 -- m_axi_card_mem0_ruser => open, -- m_axi_card_mem0_ruser,
592 -- m_axi_card_mem0_rvalid => moMEM_Mp0_RVALID,
593 -- m_axi_card_mem0_wdata => moMEM_Mp0_WDATA,
594 -- m_axi_card_mem0_wid => open,
595 -- m_axi_card_mem0_wlast => moMEM_Mp0_WLAST,
596 -- m_axi_card_mem0_wready => moMEM_Mp0_WREADY,
597 -- m_axi_card_mem0_wstrb => moMEM_Mp0_WSTRB,
598 -- m_axi_card_mem0_wuser => open, -- m_axi_card_mem0_wuser,
599 -- m_axi_card_mem0_wvalid => moMEM_Mp0_WVALID,
600 
601 -- ---- Stream Read Command ---------
602 -- soMemRdCmdP0_TDATA => soMem_Mp0_RdCmd_tdata,
603 -- soMemRdCmdP0_TVALID => soMem_Mp0_RdCmd_tvalid,
604 -- soMemRdCmdP0_TREADY => soMem_Mp0_RdCmd_tready,
605 -- ---- Stream Read Status ----------
606 -- siMemRdStsP0_TDATA => siMem_Mp0_RdSts_tdata,
607 -- siMemRdStsP0_TVALID => siMem_Mp0_RdSts_tvalid,
608 -- siMemRdStsP0_TREADY => siMem_Mp0_RdSts_tready,
609 -- ---- Stream Read Data ------------
610 -- siMemReadP0_TDATA => siMem_Mp0_Read_tdata,
611 -- siMemReadP0_TVALID => siMem_Mp0_Read_tvalid,
612 -- siMemReadP0_TREADY => siMem_Mp0_Read_tready,
613 -- siMemReadP0_TKEEP => siMem_Mp0_Read_tkeep,
614 -- siMemReadP0_TLAST => fVectorize(siMem_Mp0_Read_tlast),
615  ---- Stream Write Command --------
616  soMemWrCmdP0_TDATA => soMem_Mp0_WrCmd_tdata,
617  soMemWrCmdP0_TVALID => soMem_Mp0_WrCmd_tvalid,
618  soMemWrCmdP0_TREADY => soMem_Mp0_WrCmd_tready,
619  ---- Stream Write Status ---------
620  siMemWrStsP0_TDATA => siMem_Mp0_WrSts_tdata,
621  siMemWrStsP0_TVALID => siMem_Mp0_WrSts_tvalid,
622  siMemWrStsP0_TREADY => siMem_Mp0_WrSts_tready,
623  ---- Stream Write Data ---------
624  soMemWriteP0_TDATA => soMem_Mp0_Write_tdata,
625  soMemWriteP0_TVALID => soMem_Mp0_Write_tvalid,
626  soMemWriteP0_TREADY => soMem_Mp0_Write_tready,
627  soMemWriteP0_TKEEP => soMem_Mp0_Write_tkeep,
628  soMemWriteP0_TLAST => soMem_Mp0_Write_tlast,
629 
630 
631 
632  --------------------------------------------------------
633  -- SHELL / Mem / Mp1 Interface / Start in UAF
634  --------------------------------------------------------
635  m_axi_moMEM_Mp1_ARADDR(32 DOWNTO 0) => moMEM_Mp1_ARADDR,
636  m_axi_moMEM_Mp1_ARADDR(63 DOWNTO 33) => open,
637  m_axi_moMEM_Mp1_ARBURST => moMEM_Mp1_ARBURST,
638  m_axi_moMEM_Mp1_ARCACHE => open, -- m_axi_card_mem0_arcache,
639  --m_axi_moMEM_Mp1_ARID => moMEM_Mp1_ARID( 0 DOWNTO 0),--SR# 10394170 : out std_ulogic_vector(gAxiIdWidth-1 downto 0);
640  m_axi_moMEM_Mp1_ARLEN => moMEM_Mp1_ARLEN,
641  m_axi_moMEM_Mp1_ARLOCK => open, -- m_axi_card_mem0_arlock,
642  m_axi_moMEM_Mp1_ARPROT => open, -- m_axi_card_mem0_arprot,
643  m_axi_moMEM_Mp1_ARQOS => open, -- m_axi_card_mem0_arqos,
644  m_axi_moMEM_Mp1_ARREADY => moMEM_Mp1_ARREADY,
645  m_axi_moMEM_Mp1_ARREGION => open, -- m_axi_card_mem0_arregion,
646  m_axi_moMEM_Mp1_ARSIZE => moMEM_Mp1_ARSIZE,
647  --m_axi_moMEM_Mp1_ARUSER => open, -- m_axi_card_mem0_aruser,
648  m_axi_moMEM_Mp1_ARVALID => moMEM_Mp1_ARVALID,
649  m_axi_moMEM_Mp1_AWADDR(32 DOWNTO 0) => moMEM_Mp1_AWADDR,
650  m_axi_moMEM_Mp1_AWADDR(63 DOWNTO 33) => open,
651  m_axi_moMEM_Mp1_AWBURST => moMEM_Mp1_AWBURST,
652  m_axi_moMEM_Mp1_AWCACHE => open, -- m_axi_card_mem0_awcache,
653  --m_axi_moMEM_Mp1_AWID => moMEM_Mp1_AWID(0 DOWNTO 0),--SR# 10394170 : out std_ulogic_vector(gAxiIdWidth-1 downto 0);
654  m_axi_moMEM_Mp1_AWLEN => moMEM_Mp1_AWLEN,
655  m_axi_moMEM_Mp1_AWLOCK => open, -- m_axi_card_mem0_awlock,
656  m_axi_moMEM_Mp1_AWPROT => open, -- m_axi_card_mem0_awprot,
657  m_axi_moMEM_Mp1_AWQOS => open, -- m_axi_card_mem0_awqos,
658  m_axi_moMEM_Mp1_AWREADY => moMEM_Mp1_AWREADY,
659  m_axi_moMEM_Mp1_AWREGION => open, -- m_axi_card_mem0_awregion,
660  m_axi_moMEM_Mp1_AWSIZE => moMEM_Mp1_AWSIZE,
661  --m_axi_moMEM_Mp1_AWUSER => open, -- m_axi_card_mem0_awuser,
662  m_axi_moMEM_Mp1_AWVALID => moMEM_Mp1_AWVALID,
663  --m_axi_moMEM_Mp1_BID => moMEM_Mp1_BID(0 DOWNTO 0),--SR# 10394170 : in std_ulogic_vector(gAxiIdWidth-1 downto 0);
664  m_axi_moMEM_Mp1_BREADY => moMEM_Mp1_BREADY,
665  m_axi_moMEM_Mp1_BRESP => moMEM_Mp1_BRESP,
666  --m_axi_moMEM_Mp1_BUSER m_axi_card_mem0_buser,
667  m_axi_moMEM_Mp1_BVALID => moMEM_Mp1_BVALID,
668  m_axi_moMEM_Mp1_RDATA => moMEM_Mp1_RDATA,
669  --m_axi_moMEM_Mp1_RID => moMEM_Mp1_RID(0 DOWNTO 0),--SR# 10394170 : in std_ulogic_vector(gAxiIdWidth-1 downto 0);
670  m_axi_moMEM_Mp1_RLAST => moMEM_Mp1_RLAST,
671  m_axi_moMEM_Mp1_RREADY => moMEM_Mp1_RREADY,
672  m_axi_moMEM_Mp1_RRESP => moMEM_Mp1_RRESP,
673  --m_axi_moMEM_Mp1_RUSER => open, -- m_axi_card_mem0_ruser,
674  m_axi_moMEM_Mp1_RVALID => moMEM_Mp1_RVALID,
675  m_axi_moMEM_Mp1_WDATA => moMEM_Mp1_WDATA,
676  --m_axi_moMEM_Mp1_WID => moMEM_Mp1_WID(0 DOWNTO 0),--SR# 10394170 : in std_ulogic_vector(gAxiIdWidth-1 downto 0);
677  m_axi_moMEM_Mp1_WLAST => moMEM_Mp1_WLAST,
678  m_axi_moMEM_Mp1_WREADY => moMEM_Mp1_WREADY,
679  m_axi_moMEM_Mp1_WSTRB => moMEM_Mp1_WSTRB,
680  --m_axi_moMEM_Mp1_WUSER => open, -- m_axi_card_mem0_wuser,
681  m_axi_moMEM_Mp1_WVALID => moMEM_Mp1_WVALID,
682 
683  lcl_mem0_v => x"0000000000000000",
684  lcl_mem1_v => x"8000000000000000"
685  --------------------------------------------------------
686  -- SHELL / Mem / Mp1 Interface / End in UAF
687  --------------------------------------------------------
688 
689  );
690 
691  --end generate;
692 
693 
694  --################################################################################
695  --# #
696  --# ####### #### ###### ##### #
697  --# # # # # # # ##### ##### #
698  --# # # # # # # # # # # #
699  --# # # ###### ####### ##### ##### #
700  --# # # # # # # # #
701  --# # #### # # # # # #
702  --# #
703  --################################################################################
704 
705  -- gUdpAppFlashDepre : if cUSE_DEPRECATED_DIRECTIVES generate --TODO
706 
707  -- begin
708 
709  sMetaInTlastAsVector_Tcp(0) <= siNRC_Role_Tcp_Meta_TLAST;
710  soROLE_Nrc_Tcp_Meta_TLAST <= sMetaOutTlastAsVector_Tcp(0);
711 
712 -- auto excluding TAF TAF: Median_BlurApplication
713 -- auto excluding TAF port map (
714 -- auto excluding TAF
715 -- auto excluding TAF ------------------------------------------------------
716 -- auto excluding TAF -- From SHELL / Clock and Reset
717 -- auto excluding TAF ------------------------------------------------------
718 -- auto excluding TAF ap_clk => piSHL_156_25Clk,
719 -- auto excluding TAF ap_rst_n => (not piMMIO_Ly7_Rst),
720 -- auto excluding TAF ap_start => piMMIO_Ly7_En,
721 -- auto excluding TAF
722 -- auto excluding TAF piFMC_ROL_rank_V => piFMC_ROLE_rank,
723 -- auto excluding TAF --piFMC_ROL_rank_V_ap_vld => '1',
724 -- auto excluding TAF piFMC_ROL_size_V => piFMC_ROLE_size,
725 -- auto excluding TAF --piFMC_ROL_size_V_ap_vld => '1',
726 -- auto excluding TAF --------------------------------------------------------
727 -- auto excluding TAF -- From SHELL / Tcp Data Interfaces
728 -- auto excluding TAF --------------------------------------------------------
729 -- auto excluding TAF siSHL_This_Data_tdata => siNRC_Tcp_Data_tdata,
730 -- auto excluding TAF siSHL_This_Data_tkeep => siNRC_Tcp_Data_tkeep,
731 -- auto excluding TAF siSHL_This_Data_tlast => siNRC_Tcp_Data_tlast,
732 -- auto excluding TAF siSHL_This_Data_tvalid => siNRC_Tcp_Data_tvalid,
733 -- auto excluding TAF siSHL_This_Data_tready => siNRC_Tcp_Data_tready,
734 -- auto excluding TAF --------------------------------------------------------
735 -- auto excluding TAF -- To SHELL / Tcp Data Interfaces
736 -- auto excluding TAF --------------------------------------------------------
737 -- auto excluding TAF soTHIS_Shl_Data_tdata => soNRC_Tcp_Data_tdata,
738 -- auto excluding TAF soTHIS_Shl_Data_tkeep => soNRC_Tcp_Data_tkeep,
739 -- auto excluding TAF soTHIS_Shl_Data_tlast => soNRC_Tcp_Data_tlast,
740 -- auto excluding TAF soTHIS_Shl_Data_tvalid => soNRC_Tcp_Data_tvalid,
741 -- auto excluding TAF soTHIS_Shl_Data_tready => soNRC_Tcp_Data_tready,
742 -- auto excluding TAF
743 -- auto excluding TAF siNrc_meta_TDATA => siNRC_Role_Tcp_Meta_TDATA ,
744 -- auto excluding TAF siNrc_meta_TVALID => siNRC_Role_Tcp_Meta_TVALID ,
745 -- auto excluding TAF siNrc_meta_TREADY => siNRC_Role_Tcp_Meta_TREADY ,
746 -- auto excluding TAF siNrc_meta_TKEEP => siNRC_Role_Tcp_Meta_TKEEP ,
747 -- auto excluding TAF siNrc_meta_TLAST => sMetaInTlastAsVector_Tcp,
748 -- auto excluding TAF
749 -- auto excluding TAF soNrc_meta_TDATA => soROLE_Nrc_Tcp_Meta_TDATA ,
750 -- auto excluding TAF soNrc_meta_TVALID => soROLE_Nrc_Tcp_Meta_TVALID ,
751 -- auto excluding TAF soNrc_meta_TREADY => soROLE_Nrc_Tcp_Meta_TREADY ,
752 -- auto excluding TAF soNrc_meta_TKEEP => soROLE_Nrc_Tcp_Meta_TKEEP ,
753 -- auto excluding TAF soNrc_meta_TLAST => sMetaOutTlastAsVector_Tcp,
754 -- auto excluding TAF
755 -- auto excluding TAF poROL_NRC_Rx_ports_V => poROL_Nrc_Tcp_Rx_ports
756 -- auto excluding TAF --poROL_NRC_Tcp_Rx_ports_V_ap_vld => '1'
757 -- auto excluding TAF
758 -- auto excluding TAF
759 -- auto excluding TAF --------------------------------------------------------
760 -- auto excluding TAF -- SHELL / Mem / Mp0 Interface / Start in UAF
761 -- auto excluding TAF --------------------------------------------------------
762 -- auto excluding TAF , -- comma for syntax correctness when Mp1 is instantiated
763 -- auto excluding TAF
764 -- auto excluding TAF -- ---- Stream Read Command ---------
765 -- auto excluding TAF -- soMemRdCmdP0_TDATA => soMem_Mp0_RdCmd_tdata,
766 -- auto excluding TAF -- soMemRdCmdP0_TVALID => soMem_Mp0_RdCmd_tvalid,
767 -- auto excluding TAF -- soMemRdCmdP0_TREADY => soMem_Mp0_RdCmd_tready,
768 -- auto excluding TAF -- ---- Stream Read Status ----------
769 -- auto excluding TAF -- siMemRdStsP0_TDATA => siMem_Mp0_RdSts_tdata,
770 -- auto excluding TAF -- siMemRdStsP0_TVALID => siMem_Mp0_RdSts_tvalid,
771 -- auto excluding TAF -- siMemRdStsP0_TREADY => siMem_Mp0_RdSts_tready,
772 -- auto excluding TAF -- ---- Stream Read Data ------------
773 -- auto excluding TAF -- siMemReadP0_TDATA => siMem_Mp0_Read_tdata,
774 -- auto excluding TAF -- siMemReadP0_TVALID => siMem_Mp0_Read_tvalid,
775 -- auto excluding TAF -- siMemReadP0_TREADY => siMem_Mp0_Read_tready,
776 -- auto excluding TAF -- siMemReadP0_TKEEP => siMem_Mp0_Read_tkeep,
777 -- auto excluding TAF -- siMemReadP0_TLAST => fVectorize(siMem_Mp0_Read_tlast),
778 -- auto excluding TAF ---- Stream Write Command --------
779 -- auto excluding TAF soMemWrCmdP0_TDATA => soMem_Mp0_WrCmd_tdata,
780 -- auto excluding TAF soMemWrCmdP0_TVALID => soMem_Mp0_WrCmd_tvalid,
781 -- auto excluding TAF soMemWrCmdP0_TREADY => soMem_Mp0_WrCmd_tready,
782 -- auto excluding TAF ---- Stream Write Status ---------
783 -- auto excluding TAF siMemWrStsP0_TDATA => siMem_Mp0_WrSts_tdata,
784 -- auto excluding TAF siMemWrStsP0_TVALID => siMem_Mp0_WrSts_tvalid,
785 -- auto excluding TAF siMemWrStsP0_TREADY => siMem_Mp0_WrSts_tready,
786 -- auto excluding TAF ---- Stream Write Data ---------
787 -- auto excluding TAF soMemWriteP0_TDATA => soMem_Mp0_Write_tdata,
788 -- auto excluding TAF soMemWriteP0_TVALID => soMem_Mp0_Write_tvalid,
789 -- auto excluding TAF soMemWriteP0_TREADY => soMem_Mp0_Write_tready,
790 -- auto excluding TAF soMemWriteP0_TKEEP => soMem_Mp0_Write_tkeep,
791 -- auto excluding TAF soMemWriteP0_TLAST => soMem_Mp0_Write_tlast,
792 -- auto excluding TAF
793 -- auto excluding TAF --------------------------------------------------------
794 -- auto excluding TAF -- SHELL / Mem / Mp1 Interface / Start in TAF
795 -- auto excluding TAF --------------------------------------------------------
796 -- auto excluding TAF m_axi_moMEM_Mp1_ARADDR(32 DOWNTO 0) => moMEM_Mp1_ARADDR,
797 -- auto excluding TAF m_axi_moMEM_Mp1_ARADDR(63 DOWNTO 33) => open,
798 -- auto excluding TAF m_axi_moMEM_Mp1_ARBURST => moMEM_Mp1_ARBURST,
799 -- auto excluding TAF m_axi_moMEM_Mp1_ARCACHE => open, -- m_axi_card_mem0_arcache,
800 -- auto excluding TAF --m_axi_moMEM_Mp1_ARID => moMEM_Mp1_ARID( 0 DOWNTO 0),--SR# 10394170 : out std_ulogic_vector(gAxiIdWidth-1 downto 0);
801 -- auto excluding TAF m_axi_moMEM_Mp1_ARLEN => moMEM_Mp1_ARLEN,
802 -- auto excluding TAF m_axi_moMEM_Mp1_ARLOCK => open, -- m_axi_card_mem0_arlock,
803 -- auto excluding TAF m_axi_moMEM_Mp1_ARPROT => open, -- m_axi_card_mem0_arprot,
804 -- auto excluding TAF m_axi_moMEM_Mp1_ARQOS => open, -- m_axi_card_mem0_arqos,
805 -- auto excluding TAF m_axi_moMEM_Mp1_ARREADY => moMEM_Mp1_ARREADY,
806 -- auto excluding TAF m_axi_moMEM_Mp1_ARREGION => open, -- m_axi_card_mem0_arregion,
807 -- auto excluding TAF m_axi_moMEM_Mp1_ARSIZE => moMEM_Mp1_ARSIZE,
808 -- auto excluding TAF --m_axi_moMEM_Mp1_ARUSER => open, -- m_axi_card_mem0_aruser,
809 -- auto excluding TAF m_axi_moMEM_Mp1_ARVALID => moMEM_Mp1_ARVALID,
810 -- auto excluding TAF m_axi_moMEM_Mp1_AWADDR(32 DOWNTO 0) => moMEM_Mp1_AWADDR,
811 -- auto excluding TAF m_axi_moMEM_Mp1_AWADDR(63 DOWNTO 33) => open,
812 -- auto excluding TAF m_axi_moMEM_Mp1_AWBURST => moMEM_Mp1_AWBURST,
813 -- auto excluding TAF m_axi_moMEM_Mp1_AWCACHE => open, -- m_axi_card_mem0_awcache,
814 -- auto excluding TAF --m_axi_moMEM_Mp1_AWID => moMEM_Mp1_AWID(0 DOWNTO 0),--SR# 10394170 : out std_ulogic_vector(gAxiIdWidth-1 downto 0);
815 -- auto excluding TAF m_axi_moMEM_Mp1_AWLEN => moMEM_Mp1_AWLEN,
816 -- auto excluding TAF m_axi_moMEM_Mp1_AWLOCK => open, -- m_axi_card_mem0_awlock,
817 -- auto excluding TAF m_axi_moMEM_Mp1_AWPROT => open, -- m_axi_card_mem0_awprot,
818 -- auto excluding TAF m_axi_moMEM_Mp1_AWQOS => open, -- m_axi_card_mem0_awqos,
819 -- auto excluding TAF m_axi_moMEM_Mp1_AWREADY => moMEM_Mp1_AWREADY,
820 -- auto excluding TAF m_axi_moMEM_Mp1_AWREGION => open, -- m_axi_card_mem0_awregion,
821 -- auto excluding TAF m_axi_moMEM_Mp1_AWSIZE => moMEM_Mp1_AWSIZE,
822 -- auto excluding TAF --m_axi_moMEM_Mp1_AWUSER => open, -- m_axi_card_mem0_awuser,
823 -- auto excluding TAF m_axi_moMEM_Mp1_AWVALID => moMEM_Mp1_AWVALID,
824 -- auto excluding TAF --m_axi_moMEM_Mp1_BID => moMEM_Mp1_BID(0 DOWNTO 0),--SR# 10394170 : in std_ulogic_vector(gAxiIdWidth-1 downto 0);
825 -- auto excluding TAF m_axi_moMEM_Mp1_BREADY => moMEM_Mp1_BREADY,
826 -- auto excluding TAF m_axi_moMEM_Mp1_BRESP => moMEM_Mp1_BRESP,
827 -- auto excluding TAF --m_axi_moMEM_Mp1_BUSER m_axi_card_mem0_buser,
828 -- auto excluding TAF m_axi_moMEM_Mp1_BVALID => moMEM_Mp1_BVALID,
829 -- auto excluding TAF m_axi_moMEM_Mp1_RDATA => moMEM_Mp1_RDATA,
830 -- auto excluding TAF --m_axi_moMEM_Mp1_RID => moMEM_Mp1_RID(0 DOWNTO 0),--SR# 10394170 : in std_ulogic_vector(gAxiIdWidth-1 downto 0);
831 -- auto excluding TAF m_axi_moMEM_Mp1_RLAST => moMEM_Mp1_RLAST,
832 -- auto excluding TAF m_axi_moMEM_Mp1_RREADY => moMEM_Mp1_RREADY,
833 -- auto excluding TAF m_axi_moMEM_Mp1_RRESP => moMEM_Mp1_RRESP,
834 -- auto excluding TAF --m_axi_moMEM_Mp1_RUSER => open, -- m_axi_card_mem0_ruser,
835 -- auto excluding TAF m_axi_moMEM_Mp1_RVALID => moMEM_Mp1_RVALID,
836 -- auto excluding TAF m_axi_moMEM_Mp1_WDATA => moMEM_Mp1_WDATA,
837 -- auto excluding TAF --m_axi_moMEM_Mp1_WID => open,
838 -- auto excluding TAF m_axi_moMEM_Mp1_WLAST => moMEM_Mp1_WLAST,
839 -- auto excluding TAF m_axi_moMEM_Mp1_WREADY => moMEM_Mp1_WREADY,
840 -- auto excluding TAF m_axi_moMEM_Mp1_WSTRB => moMEM_Mp1_WSTRB,
841 -- auto excluding TAF --m_axi_moMEM_Mp1_WUSER => open, -- m_axi_card_mem0_wuser,
842 -- auto excluding TAF m_axi_moMEM_Mp1_WVALID => moMEM_Mp1_WVALID,
843 -- auto excluding TAF
844 -- auto excluding TAF lcl_mem0_v => x"0000000000000000",
845 -- auto excluding TAF lcl_mem1_v => x"8000000000000000"
846 -- auto excluding TAF --------------------------------------------------------
847 -- auto excluding TAF -- SHELL / Mem / Mp1 Interface / End in TAF
848 -- auto excluding TAF --------------------------------------------------------
849 -- auto excluding TAF
850 -- auto excluding TAF );
851 
852  --end generate;
853 
854  --DEBUGING:
855  --poROL_Nrc_Tcp_Rx_ports <= (others => '0');
856 
857  --################################################################################
858  -- 1st Memory Port dummy connections Start
859  --################################################################################
860  soMEM_Mp0_RdCmd_tdata <= (others => '0');
861  soMEM_Mp0_RdCmd_tvalid <= '0';
862  siMEM_Mp0_RdSts_tready <= '0';
863  siMEM_Mp0_Read_tready <= '0';
864  -- soMEM_Mp0_WrCmd_tdata <= (others => '0');
865  -- soMEM_Mp0_WrCmd_tvalid <= '0';
866  -- siMEM_Mp0_WrSts_tready <= '0';
867  -- soMEM_Mp0_Write_tdata <= (others => '0');
868  -- soMEM_Mp0_Write_tkeep <= (others => '0');
869  -- soMEM_Mp0_Write_tlast <= '0';
870  -- soMEM_Mp0_Write_tvalid <= '0';
871  --################################################################################
872  -- 1st Memory Port dummy connections End
873  --################################################################################
874 
875  --################################################################################
876 -- auto excluding Mp2 open connections -- 2nd Memory Port dummy connections Start
877 -- auto excluding Mp2 open connections --################################################################################
878 -- auto excluding Mp2 open connections moMEM_Mp1_AWVALID <= '0';
879 -- auto excluding Mp2 open connections moMEM_Mp1_WVALID <= '0';
880 -- auto excluding Mp2 open connections moMEM_Mp1_BREADY <= '0';
881 -- auto excluding Mp2 open connections moMEM_Mp1_ARVALID <= '0';
882 -- auto excluding Mp2 open connections moMEM_Mp1_RREADY <= '0';
883 -- auto excluding Mp2 open connections --################################################################################
884 -- auto excluding Mp2 open connections -- 2nd Memory Port dummy connections End
885  --################################################################################
886 
887 end architecture Flash;
888 
Role_Themisto
Definition: Role.vhdl:43
Role_Themisto.soNRC_Tcp_Data_tready
in soNRC_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:98
Role_Themisto.moMEM_Mp1_ARSIZE
out moMEM_Mp1_ARSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:169
Role_Themisto.moMEM_Mp1_AWADDR
out moMEM_Mp1_AWADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:151
Role_Themisto.soNRC_Udp_Data_tdata
out soNRC_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:65
Role_Themisto.soROLE_Nrc_Udp_Meta_TREADY
in soROLE_Nrc_Udp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:75
Role_Themisto.piSHL_156_25Clk
in piSHL_156_25Clkstd_ulogic
Definition: Role.vhdl:49
Role_Themisto.moMEM_Mp1_RREADY
out moMEM_Mp1_RREADYstd_ulogic
Definition: Role.vhdl:178
Role_Themisto.soROLE_Nrc_Udp_Meta_TKEEP
out soROLE_Nrc_Udp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:76
Role_Themisto.piSHL_156_25Rst
in piSHL_156_25Rststd_ulogic
Definition: Role.vhdl:50
Role_Themisto.moMEM_Mp1_RLAST
in moMEM_Mp1_RLASTstd_ulogic
Definition: Role.vhdl:176
Role_Themisto.siNRC_Udp_Data_tlast
in siNRC_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:62
Role_Themisto.siMEM_Mp0_Read_tready
out siMEM_Mp0_Read_treadystd_ulogic
Definition: Role.vhdl:131
Role_Themisto.siNRC_Role_Udp_Meta_TKEEP
in siNRC_Role_Udp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:81
Role_Themisto.moMEM_Mp1_WID
out moMEM_Mp1_WIDstd_ulogic_vector(3 downto 0)
Definition: Role.vhdl:189
Role_Themisto.siMEM_Mp0_Read_tkeep
in siMEM_Mp0_Read_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:128
Role_Themisto.soNRC_Tcp_Data_tdata
out soNRC_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:94
Role_Themisto.soROLE_Nrc_Tcp_Meta_TREADY
in soROLE_Nrc_Tcp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:104
Role_Themisto.siNRC_Role_Tcp_Meta_TLAST
in siNRC_Role_Tcp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:111
Role_Themisto.siMEM_Mp0_WrSts_tdata
in siMEM_Mp0_WrSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:137
Role_Themisto.soMEM_Mp0_Write_tkeep
out soMEM_Mp0_Write_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:142
Role_Themisto.siNRC_Tcp_Data_tready
out siNRC_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:92
Role_Themisto.siNRC_Role_Udp_Meta_TDATA
in siNRC_Role_Udp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:78
Role_Themisto.moMEM_Mp1_AWVALID
out moMEM_Mp1_AWVALIDstd_ulogic
Definition: Role.vhdl:155
Role_Themisto.siNRC_Role_Tcp_Meta_TVALID
in siNRC_Role_Tcp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:108
Role_Themisto.siNRC_Role_Tcp_Meta_TDATA
in siNRC_Role_Tcp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:107
Role_Themisto.moMEM_Mp1_BVALID
in moMEM_Mp1_BVALIDstd_ulogic
Definition: Role.vhdl:164
Role_Themisto.moMEM_Mp1_WSTRB
out moMEM_Mp1_WSTRBstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:158
Role_Themisto.moMEM_Mp1_BREADY
out moMEM_Mp1_BREADYstd_ulogic
Definition: Role.vhdl:165
Role_Themisto.moMEM_Mp1_AWID
out moMEM_Mp1_AWIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:150
Role_Themisto.moMEM_Mp1_RVALID
in moMEM_Mp1_RVALIDstd_ulogic
Definition: Role.vhdl:177
Role_Themisto.soNRC_Udp_Data_tready
in soNRC_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:69
Role_Themisto.soMEM_Mp0_WrCmd_tready
in soMEM_Mp0_WrCmd_treadystd_ulogic
Definition: Role.vhdl:135
Role_Themisto.siNRC_Udp_Data_tvalid
in siNRC_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:61
Role_Themisto.piMMIO_Ly7_En
in piMMIO_Ly7_Enstd_ulogic
Definition: Role.vhdl:53
Role_Themisto.soMEM_Mp0_Write_tready
in soMEM_Mp0_Write_treadystd_ulogic
Definition: Role.vhdl:145
Role_Themisto.soNRC_Udp_Data_tlast
out soNRC_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:68
Role_Themisto.soROLE_Nrc_Udp_Meta_TVALID
out soROLE_Nrc_Udp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:74
Role_Themisto.soROLE_Nrc_Tcp_Meta_TVALID
out soROLE_Nrc_Tcp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:103
Role_Themisto.moMEM_Mp1_WLAST
out moMEM_Mp1_WLASTstd_ulogic
Definition: Role.vhdl:159
Role_Themisto.soNRC_Udp_Data_tvalid
out soNRC_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:67
Role_Themisto.moMEM_Mp1_WDATA
out moMEM_Mp1_WDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:157
Role_Themisto.siNRC_Tcp_Data_tdata
in siNRC_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:88
Role_Themisto.soMEM_Mp0_RdCmd_tdata
out soMEM_Mp0_RdCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:119
Role_Themisto.gAxiIdWidth
gAxiIdWidthinteger :=8
Definition: Role.vhdl:33
Role_Themisto.siMEM_Mp0_Read_tdata
in siMEM_Mp0_Read_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:127
Role_Themisto.soMEM_Mp0_Write_tdata
out soMEM_Mp0_Write_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:141
Role_Themisto.siMEM_Mp0_RdSts_tready
out siMEM_Mp0_RdSts_treadystd_ulogic
Definition: Role.vhdl:125
Role_Themisto.moMEM_Mp1_ARBURST
out moMEM_Mp1_ARBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:170
Role_Themisto.siNRC_Role_Tcp_Meta_TKEEP
in siNRC_Role_Tcp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:110
Role_Themisto.siMEM_Mp0_RdSts_tdata
in siMEM_Mp0_RdSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:123
Role_Themisto.poROL_Nrc_Tcp_Rx_ports
out poROL_Nrc_Tcp_Rx_portsstd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:100
Role_Themisto.siNRC_Tcp_Data_tvalid
in siNRC_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:90
Role_Themisto.siNRC_Role_Udp_Meta_TLAST
in siNRC_Role_Udp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:82
Role_Themisto.moMEM_Mp1_ARREADY
in moMEM_Mp1_ARREADYstd_ulogic
Definition: Role.vhdl:172
Role_Themisto.siNRC_Udp_Data_tready
out siNRC_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:63
Role_Themisto.moMEM_Mp1_RRESP
in moMEM_Mp1_RRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:175
Role_Themisto.soMEM_Mp0_Write_tlast
out soMEM_Mp0_Write_tlaststd_ulogic
Definition: Role.vhdl:143
Role_Themisto.moMEM_Mp1_ARID
out moMEM_Mp1_ARIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:166
Role_Themisto.soMEM_Mp0_WrCmd_tvalid
out soMEM_Mp0_WrCmd_tvalidstd_ulogic
Definition: Role.vhdl:134
Role_Themisto.moMEM_Mp1_ARVALID
out moMEM_Mp1_ARVALIDstd_ulogic
Definition: Role.vhdl:171
Role_Themisto.soROLE_Nrc_Tcp_Meta_TDATA
out soROLE_Nrc_Tcp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:102
Role_Themisto.moMEM_Mp1_AWBURST
out moMEM_Mp1_AWBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:154
Role_Themisto.siNRC_Udp_Data_tkeep
in siNRC_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:60
Role_Themisto.soMEM_Mp0_RdCmd_tvalid
out soMEM_Mp0_RdCmd_tvalidstd_ulogic
Definition: Role.vhdl:120
Role_Themisto.soNRC_Tcp_Data_tkeep
out soNRC_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:95
Role_Themisto.siMEM_Mp0_Read_tvalid
in siMEM_Mp0_Read_tvalidstd_ulogic
Definition: Role.vhdl:130
Role_Themisto.moMEM_Mp1_RID
in moMEM_Mp1_RIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:173
Role_Themisto.soROLE_Nrc_Udp_Meta_TDATA
out soROLE_Nrc_Udp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:73
Role_Themisto.piFMC_ROLE_rank
in piFMC_ROLE_rankstd_logic_vector(31 downto 0)
Definition: Role.vhdl:192
Role_Themisto.soROLE_Nrc_Tcp_Meta_TKEEP
out soROLE_Nrc_Tcp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:105
Role_Themisto.piTOP_250_00Clk
in piTOP_250_00Clkstd_ulogic
Definition: Role.vhdl:187
Role_Themisto.moMEM_Mp1_AWLEN
out moMEM_Mp1_AWLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:152
Role_Themisto.piFMC_ROLE_size
in piFMC_ROLE_sizestd_logic_vector(31 downto 0)
Definition: Role.vhdl:193
Role_Themisto.siNRC_Tcp_Data_tkeep
in siNRC_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:89
Role_Themisto.soMEM_Mp0_RdCmd_tready
in soMEM_Mp0_RdCmd_treadystd_ulogic
Definition: Role.vhdl:121
Role_Themisto.moMEM_Mp1_WREADY
in moMEM_Mp1_WREADYstd_ulogic
Definition: Role.vhdl:161
Role_Themisto.siNRC_Role_Udp_Meta_TREADY
out siNRC_Role_Udp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:80
Role_Themisto.soNRC_Tcp_Data_tlast
out soNRC_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:97
Role_Themisto.siMEM_Mp0_RdSts_tvalid
in siMEM_Mp0_RdSts_tvalidstd_ulogic
Definition: Role.vhdl:124
Role_Themisto.soROLE_Nrc_Udp_Meta_TLAST
out soROLE_Nrc_Udp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:77
Role_Themisto.moMEM_Mp1_AWSIZE
out moMEM_Mp1_AWSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:153
Role_Themisto.moMEM_Mp1_RDATA
in moMEM_Mp1_RDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:174
Role_Themisto.moMEM_Mp1_BID
in moMEM_Mp1_BIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:162
Role_Themisto.soMEM_Mp0_WrCmd_tdata
out soMEM_Mp0_WrCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:133
Role_Themisto.piMMIO_Ly7_Rst
in piMMIO_Ly7_Rststd_ulogic
Definition: Role.vhdl:52
Role_Themisto.poSHL_Mmio_RdReg
out poSHL_Mmio_RdRegstd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:182
Role_Themisto.siNRC_Role_Tcp_Meta_TREADY
out siNRC_Role_Tcp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:109
Role_Themisto.siNRC_Role_Udp_Meta_TVALID
in siNRC_Role_Udp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:79
Role_Themisto.moMEM_Mp1_BRESP
in moMEM_Mp1_BRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:163
Role_Themisto.moMEM_Mp1_WVALID
out moMEM_Mp1_WVALIDstd_ulogic
Definition: Role.vhdl:160
Role_Themisto.siNRC_Udp_Data_tdata
in siNRC_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:59
Role_Themisto.moMEM_Mp1_ARLEN
out moMEM_Mp1_ARLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:168
Role_Themisto.soROLE_Nrc_Tcp_Meta_TLAST
out soROLE_Nrc_Tcp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:106
Role_Themisto.soNRC_Udp_Data_tkeep
out soNRC_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:66
Role_Themisto.siNRC_Tcp_Data_tlast
in siNRC_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:91
Role_Themisto.siMEM_Mp0_WrSts_tready
out siMEM_Mp0_WrSts_treadystd_ulogic
Definition: Role.vhdl:139
Role_Themisto.siMEM_Mp0_WrSts_tvalid
in siMEM_Mp0_WrSts_tvalidstd_ulogic
Definition: Role.vhdl:138
Role_Themisto.soMEM_Mp0_Write_tvalid
out soMEM_Mp0_Write_tvalidstd_ulogic
Definition: Role.vhdl:144
Role_Themisto.moMEM_Mp1_ARADDR
out moMEM_Mp1_ARADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:167
Role_Themisto.poVoid
out poVoidstd_ulogic
Definition: Role.vhdl:213
Role_Themisto.moMEM_Mp1_AWREADY
in moMEM_Mp1_AWREADYstd_ulogic
Definition: Role.vhdl:156
Role_Themisto.poROL_Nrc_Udp_Rx_ports
out poROL_Nrc_Udp_Rx_portsstd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:71
Role_Themisto.siMEM_Mp0_Read_tlast
in siMEM_Mp0_Read_tlaststd_ulogic
Definition: Role.vhdl:129
Role_Themisto.soNRC_Tcp_Data_tvalid
out soNRC_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:96