cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
top.vhdl
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3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
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10  * Unless required by applicable law or agreed to in writing, software
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12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
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16 
17 -- *
18 -- * cloudFPGA
19 -- * =============================================
20 -- * Created: Apr 2019
21 -- * Authors: FAB, WEI, NGL
22 -- *
23 -- * Description:
24 -- * TOP for Themisto SRA
25 -- *
26 
27 --******************************************************************************
28 --** CONTEXT CLAUSE ** FMKU60 FLASH
29 --******************************************************************************
30 library IEEE;
31 use IEEE.std_logic_1164.all;
32 use IEEE.numeric_std.all;
33 
34 library UNISIM;
35 use UNISIM.vcomponents.all;
36 
37 --library WORK;
38 --use WORK.topFlash_pkg.all; -- Not used
39 
40 library XIL_DEFAULTLIB;
41 use XIL_DEFAULTLIB.topFMKU_pkg.all;
42 
43 
44 --******************************************************************************
45 --** ENTITY ** FMKU60 FLASH
46 --******************************************************************************
47 
48 entity topFMKU60 is
49  generic (
50  -- Synthesis parameters ----------------------
51  gBitstreamUsage : string := "flash"; -- "user" or "flash"
52  gSecurityPriviledges : string := "super"; -- "user" or "super"
53  -- Build date --------------------------------
54  gTopDateYear : stDate := 8d"00"; -- Not used w/ Xilinx parts (see USR_ACCESSE2)
55  gTopDateMonth : stDate := 8d"00"; -- Not used w/ Xilinx parts (see USR_ACCESSE2)
56  gTopDateDay : stDate := 8d"00"; -- Not used w/ Xilinx parts (see USR_ACCESSE2)
57  -- External Memory Interface (EMIF) ----------
58  gEmifAddrWidth : integer := 8;
59  gEmifDataWidth : integer := 8
60  );
61  port (
62  ------------------------------------------------------
63  -- PSOC / FPGA Configuration Interface (Fcfg)
64  -- System reset controlled by the PSoC.
65  ------------------------------------------------------
66  piPSOC_Fcfg_Rst_n : in std_ulogic;
67 
68  ------------------------------------------------------
69  -- CLKT / DRAM clocks 0 and 1 (Mem. Channels 0 and 1)
70  ------------------------------------------------------
71  piCLKT_Mem0Clk_n : in std_ulogic;
72  piCLKT_Mem0Clk_p : in std_ulogic;
73  piCLKT_Mem1Clk_n : in std_ulogic;
74  piCLKT_Mem1Clk_p : in std_ulogic;
75 
76  ------------------------------------------------------
77  -- CLKT / GTH clocks (10Ge, Sata, Gtio Interfaces)
78  ------------------------------------------------------
79  piCLKT_10GeClk_n : in std_ulogic;
80  piCLKT_10GeClk_p : in std_ulogic;
81 
82  ------------------------------------------------------
83  -- CLKT / User clocks 0 and 1 (156.25MHz, 250MHz)
84  ------------------------------------------------------
85  piCLKT_Usr0Clk_n : in std_ulogic;
86  piCLKT_Usr0Clk_p : in std_ulogic;
87  piCLKT_Usr1Clk_n : in std_ulogic;
88  piCLKT_Usr1Clk_p : in std_ulogic;
89 
90  ------------------------------------------------------
91  -- PSOC / External Memory Interface (Emif)
92  ------------------------------------------------------
93  piPSOC_Emif_Clk : in std_ulogic;
94  piPSOC_Emif_Cs_n : in std_ulogic;
95  piPSOC_Emif_We_n : in std_ulogic;
96  piPSOC_Emif_Oe_n : in std_ulogic;
97  piPSOC_Emif_AdS_n : in std_ulogic;
98  piPSOC_Emif_Addr : in std_ulogic_vector(gEmifAddrWidth-1 downto 0);
99  pioPSOC_Emif_Data : inout std_ulogic_vector(gEmifDataWidth-1 downto 0);
100 
101  ------------------------------------------------------
102  -- LED / Heart Beat Interface (Yellow LED)
103  ------------------------------------------------------
104  poLED_HeartBeat_n : out std_ulogic;
105 
106  ------------------------------------------------------
107  -- -- DDR(4) / Memory Channel 0 Interface (Mc0)
108  ------------------------------------------------------
109  pioDDR4_Mem_Mc0_DmDbi_n : inout std_ulogic_vector( 8 downto 0);
110  pioDDR4_Mem_Mc0_Dq : inout std_ulogic_vector(71 downto 0);
111  pioDDR4_Mem_Mc0_Dqs_p : inout std_ulogic_vector( 8 downto 0);
112  pioDDR4_Mem_Mc0_Dqs_n : inout std_ulogic_vector( 8 downto 0);
113  poDDR4_Mem_Mc0_Act_n : out std_ulogic;
114  poDDR4_Mem_Mc0_Adr : out std_ulogic_vector(16 downto 0);
115  poDDR4_Mem_Mc0_Ba : out std_ulogic_vector( 1 downto 0);
116  poDDR4_Mem_Mc0_Bg : out std_ulogic_vector( 1 downto 0);
117  poDDR4_Mem_Mc0_Cke : out std_ulogic;
118  poDDR4_Mem_Mc0_Odt : out std_ulogic;
119  poDDR4_Mem_Mc0_Cs_n : out std_ulogic;
120  poDDR4_Mem_Mc0_Ck_p : out std_ulogic;
121  poDDR4_Mem_Mc0_Ck_n : out std_ulogic;
122  poDDR4_Mem_Mc0_Reset_n : out std_ulogic;
123 
124  ------------------------------------------------------
125  -- DDR(4) / Memory Channel 1 Interface (Mc1)
126  ------------------------------------------------------
127  pioDDR4_Mem_Mc1_DmDbi_n : inout std_ulogic_vector( 8 downto 0);
128  pioDDR4_Mem_Mc1_Dq : inout std_ulogic_vector(71 downto 0);
129  pioDDR4_Mem_Mc1_Dqs_p : inout std_ulogic_vector( 8 downto 0);
130  pioDDR4_Mem_Mc1_Dqs_n : inout std_ulogic_vector( 8 downto 0);
131  poDDR4_Mem_Mc1_Act_n : out std_ulogic;
132  poDDR4_Mem_Mc1_Adr : out std_ulogic_vector(16 downto 0);
133  poDDR4_Mem_Mc1_Ba : out std_ulogic_vector( 1 downto 0);
134  poDDR4_Mem_Mc1_Bg : out std_ulogic_vector( 1 downto 0);
135  poDDR4_Mem_Mc1_Cke : out std_ulogic;
136  poDDR4_Mem_Mc1_Odt : out std_ulogic;
137  poDDR4_Mem_Mc1_Cs_n : out std_ulogic;
138  poDDR4_Mem_Mc1_Ck_p : out std_ulogic;
139  poDDR4_Mem_Mc1_Ck_n : out std_ulogic;
140  poDDR4_Mem_Mc1_Reset_n : out std_ulogic;
141 
142  ------------------------------------------------------
143  -- ECON / Edge Connector Interface (SPD08-200)
144  ------------------------------------------------------
145  piECON_Eth_10Ge0_n : in std_ulogic;
146  piECON_Eth_10Ge0_p : in std_ulogic;
147  poECON_Eth_10Ge0_n : out std_ulogic;
148  poECON_Eth_10Ge0_p : out std_ulogic
149 
150  );
151 
152 end topFMKU60;
153 
154 
155 --*****************************************************************************
156 --** ARCHITECTURE ** FMKU60 FLASH
157 --*****************************************************************************
158 architecture structural of topFMKU60 is
159 
160  --------------------------------------------------------n
161  -- [TOP] SIGNAL DECLARATIONS
162  --------------------------------------------------------
163 
164  -- Global User Clocks ----------------------------------
165  signal sTOP_156_25Clk : std_ulogic;
166  signal sTOP_250_00Clk : std_ulogic;
167 
168  -- Global Reset ----------------------------------------
169  signal sTOP_156_25Rst_n : std_ulogic;
170  signal sTOP_156_25Rst : std_ulogic;
171 
172  -- Global Source Synchronous Clock and Reset -----------
173  signal sSHL_156_25Clk : std_ulogic;
174  signal sSHL_156_25Rst : std_ulogic;
175 
176  -- Bitstream Identification Value ----------------------
177  signal sTOP_Timestamp : stTimeStamp;
178 
179  --------------------------------------------------------
180  -- SIGNAL DECLARATIONS : [SHELL/Nts] <--> [ROLE/Nts]
181  --------------------------------------------------------
182  ---- UDP Interface ---------------------------
183  ------ Input AXI-Write Stream Interface ------
184  signal sROL_Shl_Nts0_Udp_Axis_tdata : std_ulogic_vector( 63 downto 0);
185  signal sROL_Shl_Nts0_Udp_Axis_tkeep : std_ulogic_vector( 7 downto 0);
186  signal sROL_Shl_Nts0_Udp_Axis_tlast : std_ulogic;
187  signal sROL_Shl_Nts0_Udp_Axis_tvalid : std_ulogic;
188  signal sSHL_Rol_Nts0_Udp_Axis_tready : std_ulogic;
189  ------ Output AXI-Write Stream Interface -----
190  signal sROL_Shl_Nts0_Udp_Axis_tready : std_ulogic;
191  signal sSHL_Rol_Nts0_Udp_Axis_tdata : std_ulogic_vector( 63 downto 0);
192  signal sSHL_Rol_Nts0_Udp_Axis_tkeep : std_ulogic_vector( 7 downto 0);
193  signal sSHL_Rol_Nts0_Udp_Axis_tlast : std_ulogic;
194  signal sSHL_Rol_Nts0_Udp_Axis_tvalid : std_ulogic;
195  -- Open Port vector
196  signal sROL_Nrc_Udp_Rx_ports : std_ulogic_vector( 31 downto 0);
197  -- ROLE <-> NRC Meta Interface
198  signal sROLE_Nrc_Udp_Meta_TDATA : std_ulogic_vector( 63 downto 0);
199  signal sROLE_Nrc_Udp_Meta_TVALID : std_ulogic;
200  signal sROLE_Nrc_Udp_Meta_TREADY : std_ulogic;
201  signal sROLE_Nrc_Udp_Meta_TKEEP : std_ulogic_vector( 7 downto 0);
202  signal sROLE_Nrc_Udp_Meta_TLAST : std_ulogic;
203  signal sNRC_Role_Udp_Meta_TDATA : std_ulogic_vector( 63 downto 0);
204  signal sNRC_Role_Udp_Meta_TVALID : std_ulogic;
205  signal sNRC_Role_Udp_Meta_TREADY : std_ulogic;
206  signal sNRC_Role_Udp_Meta_TKEEP : std_ulogic_vector( 7 downto 0);
207  signal sNRC_Role_Udp_Meta_TLAST : std_ulogic;
208 
209  ---- TCP Interface ---------------------------
210  ------ Input AXI-Write Stream Interface ------
211  signal sROL_Shl_Nts0_Tcp_Axis_tdata : std_ulogic_vector( 63 downto 0);
212  signal sROL_Shl_Nts0_Tcp_Axis_tkeep : std_ulogic_vector( 7 downto 0);
213  signal sROL_Shl_Nts0_Tcp_Axis_tlast : std_ulogic;
214  signal sROL_Shl_Nts0_Tcp_Axis_tvalid : std_ulogic;
215  signal sSHL_Rol_Nts0_Tcp_Axis_tready : std_ulogic;
216  ------ Output AXI-Write Stream Interface -----
217  signal sROL_Shl_Nts0_Tcp_Axis_tready : std_ulogic;
218  signal sSHL_Rol_Nts0_Tcp_Axis_tdata : std_ulogic_vector( 63 downto 0);
219  signal sSHL_Rol_Nts0_Tcp_Axis_tkeep : std_ulogic_vector( 7 downto 0);
220  signal sSHL_Rol_Nts0_Tcp_Axis_tlast : std_ulogic;
221  signal sSHL_Rol_Nts0_Tcp_Axis_tvalid : std_ulogic;
222  -- Open Port vector
223  signal sROL_Nrc_Tcp_Rx_ports : std_ulogic_vector( 31 downto 0);
224  -- ROLE <-> NRC Meta Interface
225  signal sROLE_Nrc_Tcp_Meta_TDATA : std_ulogic_vector( 63 downto 0);
226  signal sROLE_Nrc_Tcp_Meta_TVALID : std_ulogic;
227  signal sROLE_Nrc_Tcp_Meta_TREADY : std_ulogic;
228  signal sROLE_Nrc_Tcp_Meta_TKEEP : std_ulogic_vector( 7 downto 0);
229  signal sROLE_Nrc_Tcp_Meta_TLAST : std_ulogic;
230  signal sNRC_Role_Tcp_Meta_TDATA : std_ulogic_vector( 63 downto 0);
231  signal sNRC_Role_Tcp_Meta_TVALID : std_ulogic;
232  signal sNRC_Role_Tcp_Meta_TREADY : std_ulogic;
233  signal sNRC_Role_Tcp_Meta_TKEEP : std_ulogic_vector( 7 downto 0);
234  signal sNRC_Role_Tcp_Meta_TLAST : std_ulogic;
235 
236 
237 
238  --------------------------------------------------------
239  -- SIGNAL DECLARATIONS : [SHELL/Mem] <--> [ROLE/Mem]
240  --------------------------------------------------------
241  -- Memory Port #0 ------------------------------
242  ------ Stream Read Command --------------
243  signal ssROL_SHL_Mem_Mp0_RdCmd_tdata : std_ulogic_vector( 79 downto 0);
244  signal ssROL_SHL_Mem_Mp0_RdCmd_tvalid : std_ulogic;
245  signal ssROL_SHL_Mem_Mp0_RdCmd_tready : std_ulogic;
246  ------ Stream Read Status ----------------
247  signal ssSHL_ROL_Mem_Mp0_RdSts_tdata : std_ulogic_vector( 7 downto 0);
248  signal ssSHL_ROL_Mem_Mp0_RdSts_tvalid : std_ulogic;
249  signal ssSHL_ROL_Mem_Mp0_RdSts_tready : std_ulogic;
250  ------ Stream Data Output Channel --------
251  signal ssSHL_ROL_Mem_Mp0_Read_tdata : std_ulogic_vector(511 downto 0);
252  signal ssSHL_ROL_Mem_Mp0_Read_tkeep : std_ulogic_vector( 63 downto 0);
253  signal ssSHL_ROL_Mem_Mp0_Read_tlast : std_ulogic;
254  signal ssSHL_ROL_Mem_Mp0_Read_tvalid : std_ulogic;
255  signal ssSHL_ROL_Mem_Mp0_Read_tready : std_ulogic;
256  ------ Stream Write Command --------------
257  signal ssROL_SHL_Mem_Mp0_WrCmd_tdata : std_ulogic_vector( 79 downto 0);
258  signal ssROL_SHL_Mem_Mp0_WrCmd_tvalid : std_ulogic;
259  signal ssROL_SHL_Mem_Mp0_WrCmd_tready : std_ulogic;
260  ------ Stream Write Status ---------------
261  signal ssSHL_ROL_Mem_Mp0_WrSts_tdata : std_ulogic_vector( 7 downto 0);
262  signal ssSHL_ROL_Mem_Mp0_WrSts_tvalid : std_ulogic;
263  signal ssSHL_ROL_Mem_Mp0_WrSts_tready : std_ulogic;
264  ------ Stream Data Input Channel ---------
265  signal ssROL_SHL_Mem_Mp0_Write_tdata : std_ulogic_vector(511 downto 0);
266  signal ssROL_SHL_Mem_Mp0_Write_tkeep : std_ulogic_vector( 63 downto 0);
267  signal ssROL_SHL_Mem_Mp0_Write_tlast : std_ulogic;
268  signal ssROL_SHL_Mem_Mp0_Write_tvalid : std_ulogic;
269  signal ssROL_SHL_Mem_Mp0_Write_tready : std_ulogic;
270  -- Memory Port #1 ------------------------------
271  signal smROL_SHL_Mem_Mp1_AWID : std_ulogic_vector(7 downto 0);
272  signal smROL_SHL_Mem_Mp1_AWADDR : std_ulogic_vector(32 downto 0);
273  signal smROL_SHL_Mem_Mp1_AWLEN : std_ulogic_vector(7 downto 0);
274  signal smROL_SHL_Mem_Mp1_AWSIZE : std_ulogic_vector(2 downto 0);
275  signal smROL_SHL_Mem_Mp1_AWBURST : std_ulogic_vector(1 downto 0);
276  signal smROL_SHL_Mem_Mp1_AWVALID : std_ulogic;
277  signal smROL_SHL_Mem_Mp1_AWREADY : std_ulogic;
278  signal smROL_SHL_Mem_Mp1_WDATA : std_ulogic_vector(511 downto 0);
279  signal smROL_SHL_Mem_Mp1_WSTRB : std_ulogic_vector(63 downto 0);
280  signal smROL_SHL_Mem_Mp1_WLAST : std_ulogic;
281  signal smROL_SHL_Mem_Mp1_WVALID : std_ulogic;
282  signal smROL_SHL_Mem_Mp1_WREADY : std_ulogic;
283  signal smROL_SHL_Mem_Mp1_BID : std_ulogic_vector(7 downto 0);
284  signal smROL_SHL_Mem_Mp1_BRESP : std_ulogic_vector(1 downto 0);
285  signal smROL_SHL_Mem_Mp1_BVALID : std_ulogic;
286  signal smROL_SHL_Mem_Mp1_BREADY : std_ulogic;
287  signal smROL_SHL_Mem_Mp1_ARID : std_ulogic_vector(7 downto 0);
288  signal smROL_SHL_Mem_Mp1_ARADDR : std_ulogic_vector(32 downto 0);
289  signal smROL_SHL_Mem_Mp1_ARLEN : std_ulogic_vector(7 downto 0);
290  signal smROL_SHL_Mem_Mp1_ARSIZE : std_ulogic_vector(2 downto 0);
291  signal smROL_SHL_Mem_Mp1_ARBURST : std_ulogic_vector(1 downto 0);
292  signal smROL_SHL_Mem_Mp1_ARVALID : std_ulogic;
293  signal smROL_SHL_Mem_Mp1_ARREADY : std_ulogic;
294  signal smROL_SHL_Mem_Mp1_RID : std_ulogic_vector(7 downto 0);
295  signal smROL_SHL_Mem_Mp1_RDATA : std_ulogic_vector(511 downto 0);
296  signal smROL_SHL_Mem_Mp1_RRESP : std_ulogic_vector(1 downto 0);
297  signal smROL_SHL_Mem_Mp1_RLAST : std_ulogic;
298  signal smROL_SHL_Mem_Mp1_RVALID : std_ulogic;
299  signal smROL_SHL_Mem_Mp1_RREADY : std_ulogic;
300 
301 
302  --------------------------------------------------------
303  -- SIGNAL DECLARATIONS : [MMIO] <--> [ROLE]
304  --------------------------------------------------------
305  ---- [PHY_RESET] -------------------------
306  signal sSHL_ROL_Mmio_Ly7Rst : std_ulogic;
307  ---- [PHY_ENABLE] ------------------------
308  signal sSHL_ROL_Mmio_Ly7En : std_ulogic;
309  ---- DIAG_CTRL_1 -------------------------
310  signal sSHL_ROL_Mmio_Mc1_MemTestCtrl : std_ulogic_vector( 1 downto 0);
311  ---- DIAG_STAT_1 -------------------------
312  signal sROL_SHL_Mmio_Mc1_MemTestStat : std_ulogic_vector( 1 downto 0);
313  ---- CTRL_2 Register ---------------------
314  signal sSHL_ROL_Mmio_UdpEchoCtrl : std_ulogic_vector( 1 downto 0);
315  signal sSHL_ROL_Mmio_UdpPostDgmEn : std_ulogic;
316  signal sSHL_ROL_Mmio_UdpCaptDgmEn : std_ulogic;
317  signal sSHL_ROL_Mmio_TcpEchoCtrl : std_ulogic_vector( 1 downto 0);
318  signal sSHL_ROL_Mmio_TcpPostSegEn : std_ulogic;
319  signal sSHL_ROL_Mmio_TcpCaptSegEn : std_ulogic;
320  ---- APP_RDROL[0:1] ---------------------
321  signal sROL_SHL_Mmio_RdReg : std_ulogic_vector( 15 downto 0);
322  ---- APP_WRROL[0:1] ---------------------
323  signal sSHL_ROL_Mmio_WrReg : std_ulogic_vector( 15 downto 0);
324 
325  --------------------------------------------------------
326  -- SIGNAL DECLARATION : [FMC] <--> [ROLE]
327  --------------------------------------------------------
328  signal sSHL_ROL_Fmc_Rank : std_ulogic_vector( 31 downto 0);
329  signal sSHL_ROL_Fmc_Size : std_ulogic_vector( 31 downto 0);
330 
331  signal sROL_reset_combinded : std_ulogic;
332 
333  --===========================================================================
334  --== COMPONENT DECLARATIONS
335  --===========================================================================
336 
337  -- [INFO] The SHELL component is declared in the corresponding TOP package.
338  -- not this time
339  -- to declare the component in the pkg seems not to work for Verilog or .dcp modules
340  component Shell_Themisto
341  generic (
342  gSecurityPriviledges : string := "super"; -- Can be "user" or "super"
343  gBitstreamUsage : string := "flash"; -- Can be "user" or "flash"
344  gMmioAddrWidth : integer := 8; -- Default is 8-bits
345  gMmioDataWidth : integer := 8 -- Default is 8-bits
346  );
347  port (
348  ------------------------------------------------------
349  -- TOP / Input Clocks and Resets from topFMKU60
350  ------------------------------------------------------
351  piTOP_156_25Rst : in std_ulogic;
352  piTOP_156_25Clk : in std_ulogic;
353 
354  ------------------------------------------------------
355  -- TOP / Bitstream Identification
356  ------------------------------------------------------
357  piTOP_Timestamp : in std_ulogic_vector( 31 downto 0);
358 
359  ------------------------------------------------------
360  -- CLKT / Clock Tree Interface
361  ------------------------------------------------------
362  piCLKT_Mem0Clk_n : in std_ulogic;
363  piCLKT_Mem0Clk_p : in std_ulogic;
364  piCLKT_Mem1Clk_n : in std_ulogic;
365  piCLKT_Mem1Clk_p : in std_ulogic;
366  piCLKT_10GeClk_n : in std_ulogic;
367  piCLKT_10GeClk_p : in std_ulogic;
368 
369  ------------------------------------------------------
370  -- PSOC / External Memory Interface (Emif)
371  ------------------------------------------------------
372  piPSOC_Emif_Clk : in std_ulogic;
373  piPSOC_Emif_Cs_n : in std_ulogic;
374  piPSOC_Emif_We_n : in std_ulogic;
375  piPSOC_Emif_Oe_n : in std_ulogic;
376  piPSOC_Emif_AdS_n : in std_ulogic;
377  piPSOC_Emif_Addr : in std_ulogic_vector(gMmioAddrWidth-1 downto 0);
378  pioPSOC_Emif_Data : inout std_ulogic_vector(gMmioDataWidth-1 downto 0);
379 
380  ------------------------------------------------------
381  -- LED / Heart Beat Interface (Yellow LED)
382  ------------------------------------------------------
383  poLED_HeartBeat_n : out std_ulogic;
384 
385  ------------------------------------------------------
386  -- DDR4 / Memory Channel 0 Interface (Mc0)
387  ------------------------------------------------------
388  pioDDR4_Mem_Mc0_DmDbi_n : inout std_ulogic_vector( 8 downto 0);
389  pioDDR4_Mem_Mc0_Dq : inout std_ulogic_vector( 71 downto 0);
390  pioDDR4_Mem_Mc0_Dqs_n : inout std_ulogic_vector( 8 downto 0);
391  pioDDR4_Mem_Mc0_Dqs_p : inout std_ulogic_vector( 8 downto 0);
392  poDDR4_Mem_Mc0_Act_n : out std_ulogic;
393  poDDR4_Mem_Mc0_Adr : out std_ulogic_vector( 16 downto 0);
394  poDDR4_Mem_Mc0_Ba : out std_ulogic_vector( 1 downto 0);
395  poDDR4_Mem_Mc0_Bg : out std_ulogic_vector( 1 downto 0);
396  poDDR4_Mem_Mc0_Cke : out std_ulogic;
397  poDDR4_Mem_Mc0_Odt : out std_ulogic;
398  poDDR4_Mem_Mc0_Cs_n : out std_ulogic;
399  poDDR4_Mem_Mc0_Ck_n : out std_ulogic;
400  poDDR4_Mem_Mc0_Ck_p : out std_ulogic;
401  poDDR4_Mem_Mc0_Reset_n : out std_ulogic;
402 
403  ------------------------------------------------------
404  -- DDR4 / Memory Channel 1 Interface (Mc1)
405  ------------------------------------------------------
406  pioDDR4_Mem_Mc1_DmDbi_n : inout std_ulogic_vector( 8 downto 0);
407  pioDDR4_Mem_Mc1_Dq : inout std_ulogic_vector( 71 downto 0);
408  pioDDR4_Mem_Mc1_Dqs_n : inout std_ulogic_vector( 8 downto 0);
409  pioDDR4_Mem_Mc1_Dqs_p : inout std_ulogic_vector( 8 downto 0);
410  poDDR4_Mem_Mc1_Act_n : out std_ulogic;
411  poDDR4_Mem_Mc1_Adr : out std_ulogic_vector( 16 downto 0);
412  poDDR4_Mem_Mc1_Ba : out std_ulogic_vector( 1 downto 0);
413  poDDR4_Mem_Mc1_Bg : out std_ulogic_vector( 1 downto 0);
414  poDDR4_Mem_Mc1_Cke : out std_ulogic;
415  poDDR4_Mem_Mc1_Odt : out std_ulogic;
416  poDDR4_Mem_Mc1_Cs_n : out std_ulogic;
417  poDDR4_Mem_Mc1_Ck_n : out std_ulogic;
418  poDDR4_Mem_Mc1_Ck_p : out std_ulogic;
419  poDDR4_Mem_Mc1_Reset_n : out std_ulogic;
420 
421  ------------------------------------------------------
422  -- ECON / Edge Connector Interface (SPD08-200)
423  ------------------------------------------------------
424  piECON_Eth_10Ge0_n : in std_ulogic;
425  piECON_Eth_10Ge0_p : in std_ulogic;
426  poECON_Eth_10Ge0_n : out std_ulogic;
427  poECON_Eth_10Ge0_p : out std_ulogic;
428 
429  ------------------------------------------------------
430  -- ROLE / Output Clock and Reset Interfaces
431  ------------------------------------------------------
432  poROL_156_25Clk : out std_ulogic;
433  poROL_156_25Rst : out std_ulogic;
434 
435  ------------------------------------------------------
436  -- ROLE / Nts / Udp Interface
437  ------------------------------------------------------
438  -- Input AXI-Write Stream Interface ----------
439  siROL_Nts_Udp_Data_tdata : in std_ulogic_vector( 63 downto 0);
440  siROL_Nts_Udp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
441  siROL_Nts_Udp_Data_tlast : in std_ulogic;
442  siROL_Nts_Udp_Data_tvalid : in std_ulogic;
443  siROL_Nts_Udp_Data_tready : out std_ulogic;
444  -- Output AXI-Write Stream Interface ---------
445  soROL_Nts_Udp_Data_tdata : out std_ulogic_vector( 63 downto 0);
446  soROL_Nts_Udp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
447  soROL_Nts_Udp_Data_tlast : out std_ulogic;
448  soROL_Nts_Udp_Data_tvalid : out std_ulogic;
449  soROL_Nts_Udp_Data_tready : in std_ulogic;
450  -- Open Port vector
451  piROL_Nrc_Udp_Rx_ports : in std_ulogic_vector( 31 downto 0);
452  -- ROLE <-> NRC Meta Interface
453  siROLE_Nrc_Udp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
454  siROLE_Nrc_Udp_Meta_TVALID : in std_ulogic;
455  siROLE_Nrc_Udp_Meta_TREADY : out std_ulogic;
456  siROLE_Nrc_Udp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
457  siROLE_Nrc_Udp_Meta_TLAST : in std_ulogic;
458  soNRC_Role_Udp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
459  soNRC_Role_Udp_Meta_TVALID : out std_ulogic;
460  soNRC_Role_Udp_Meta_TREADY : in std_ulogic;
461  soNRC_Role_Udp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
462  soNRC_Role_Udp_Meta_TLAST : out std_ulogic;
463 
464  ------------------------------------------------------
465  -- ROLE / Shl / Nts0 / Tcp Interfaces
466  ------------------------------------------------------
467  -- Input AXI-Write Stream Interface ----------
468  siROL_Nts_Tcp_Data_tdata : in std_ulogic_vector( 63 downto 0);
469  siROL_Nts_Tcp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
470  siROL_Nts_Tcp_Data_tlast : in std_ulogic;
471  siROL_Nts_Tcp_Data_tvalid : in std_ulogic;
472  siROL_Nts_Tcp_Data_tready : out std_ulogic;
473  -- Output AXI-Write Stream Interface ---------
474  soROL_Nts_Tcp_Data_tdata : out std_ulogic_vector( 63 downto 0);
475  soROL_Nts_Tcp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
476  soROL_Nts_Tcp_Data_tlast : out std_ulogic;
477  soROL_Nts_Tcp_Data_tvalid : out std_ulogic;
478  soROL_Nts_Tcp_Data_tready : in std_ulogic;
479  -- Open Port vector
480  piROL_Nrc_Tcp_Rx_ports : in std_ulogic_vector( 31 downto 0);
481  -- ROLE <-> NRC Meta Interface
482  siROLE_Nrc_Tcp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
483  siROLE_Nrc_Tcp_Meta_TVALID : in std_ulogic;
484  siROLE_Nrc_Tcp_Meta_TREADY : out std_ulogic;
485  siROLE_Nrc_Tcp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
486  siROLE_Nrc_Tcp_Meta_TLAST : in std_ulogic;
487  soNRC_Role_Tcp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
488  soNRC_Role_Tcp_Meta_TVALID : out std_ulogic;
489  soNRC_Role_Tcp_Meta_TREADY : in std_ulogic;
490  soNRC_Role_Tcp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
491  soNRC_Role_Tcp_Meta_TLAST : out std_ulogic;
492 
493  ------------------------------------------------------
494  -- ROLE / Mem / Mp0 Interface
495  ------------------------------------------------------
496  -- Memory Port #0 / S2MM-AXIS ------------------
497  ---- Stream Read Command -----------------
498  siROL_Mem_Mp0_RdCmd_tdata : in std_ulogic_vector( 79 downto 0);
499  siROL_Mem_Mp0_RdCmd_tvalid : in std_ulogic;
500  siROL_Mem_Mp0_RdCmd_tready : out std_ulogic;
501  ---- Stream Read Status ------------------
502  soROL_Mem_Mp0_RdSts_tdata : out std_ulogic_vector( 7 downto 0);
503  soROL_Mem_Mp0_RdSts_tvalid : out std_ulogic;
504  soROL_Mem_Mp0_RdSts_tready : in std_ulogic;
505  ---- Stream Data Output Channel ----------
506  soROL_Mem_Mp0_Read_tdata : out std_ulogic_vector(511 downto 0);
507  soROL_Mem_Mp0_Read_tkeep : out std_ulogic_vector( 63 downto 0);
508  soROL_Mem_Mp0_Read_tlast : out std_ulogic;
509  soROL_Mem_Mp0_Read_tvalid : out std_ulogic;
510  soROL_Mem_Mp0_Read_tready : in std_ulogic;
511  ---- Stream Write Command ----------------
512  siROL_Mem_Mp0_WrCmd_tdata : in std_ulogic_vector( 79 downto 0);
513  siROL_Mem_Mp0_WrCmd_tvalid : in std_ulogic;
514  siROL_Mem_Mp0_WrCmd_tready : out std_ulogic;
515  ---- Stream Write Status -----------------
516  soROL_Mem_Mp0_WrSts_tvalid : out std_ulogic;
517  soROL_Mem_Mp0_WrSts_tdata : out std_ulogic_vector( 7 downto 0);
518  soROL_Mem_Mp0_WrSts_tready : in std_ulogic;
519  ---- Stream Data Input Channel -----------
520  siROL_Mem_Mp0_Write_tdata : in std_ulogic_vector(511 downto 0);
521  siROL_Mem_Mp0_Write_tkeep : in std_ulogic_vector( 63 downto 0);
522  siROL_Mem_Mp0_Write_tlast : in std_ulogic;
523  siROL_Mem_Mp0_Write_tvalid : in std_ulogic;
524  siROL_Mem_Mp0_Write_tready : out std_ulogic;
525 
526  ------------------------------------------------------
527  -- ROLE / Mem / Mp1 Interface
528  ------------------------------------------------------
529  miROL_Mem_Mp1_AWID : in std_ulogic_vector(7 downto 0);
530  miROL_Mem_Mp1_AWADDR : in std_ulogic_vector(32 downto 0);
531  miROL_Mem_Mp1_AWLEN : in std_ulogic_vector(7 downto 0);
532  miROL_Mem_Mp1_AWSIZE : in std_ulogic_vector(2 downto 0);
533  miROL_Mem_Mp1_AWBURST : in std_ulogic_vector(1 downto 0);
534  miROL_Mem_Mp1_AWVALID : in std_ulogic;
535  miROL_Mem_Mp1_AWREADY : out std_ulogic;
536  miROL_Mem_Mp1_WDATA : in std_ulogic_vector(511 downto 0);
537  miROL_Mem_Mp1_WSTRB : in std_ulogic_vector(63 downto 0);
538  miROL_Mem_Mp1_WLAST : in std_ulogic;
539  miROL_Mem_Mp1_WVALID : in std_ulogic;
540  miROL_Mem_Mp1_WREADY : out std_ulogic;
541  miROL_Mem_Mp1_BID : out std_ulogic_vector(7 downto 0);
542  miROL_Mem_Mp1_BRESP : out std_ulogic_vector(1 downto 0);
543  miROL_Mem_Mp1_BVALID : out std_ulogic;
544  miROL_Mem_Mp1_BREADY : in std_ulogic;
545  miROL_Mem_Mp1_ARID : in std_ulogic_vector(7 downto 0);
546  miROL_Mem_Mp1_ARADDR : in std_ulogic_vector(32 downto 0);
547  miROL_Mem_Mp1_ARLEN : in std_ulogic_vector(7 downto 0);
548  miROL_Mem_Mp1_ARSIZE : in std_ulogic_vector(2 downto 0);
549  miROL_Mem_Mp1_ARBURST : in std_ulogic_vector(1 downto 0);
550  miROL_Mem_Mp1_ARVALID : in std_ulogic;
551  miROL_Mem_Mp1_ARREADY : out std_ulogic;
552  miROL_Mem_Mp1_RID : out std_ulogic_vector(7 downto 0);
553  miROL_Mem_Mp1_RDATA : out std_ulogic_vector(511 downto 0);
554  miROL_Mem_Mp1_RRESP : out std_ulogic_vector(1 downto 0);
555  miROL_Mem_Mp1_RLAST : out std_ulogic;
556  miROL_Mem_Mp1_RVALID : out std_ulogic;
557  miROL_Mem_Mp1_RREADY : in std_ulogic;
558 
559  --------------------------------------------------------
560  -- ROLE / Mmio / AppFlash Interface
561  --------------------------------------------------------
562  ---- PHY_RESET --------------------
563  poROL_Mmio_Ly7Rst : out std_ulogic;
564  ---- PHY_ENABLE -------------------
565  poROL_Mmio_Ly7En : out std_ulogic;
566  ---- DIAG_CTRL_1 ------------------
567  poROL_Mmio_Mc1_MemTestCtrl : out std_ulogic_vector( 1 downto 0);
568  ---- DIAG_STAT_1 -----------------
569  piROL_Mmio_Mc1_MemTestStat : in std_ulogic_vector( 1 downto 0); -- [FIXME: Why 7:0 and not 7:6 ? ]
570  ---- DIAG_CTRL_2 ------------------
571  poROL_Mmio_UdpEchoCtrl : out std_ulogic_vector( 1 downto 0);
572  poROL_Mmio_UdpPostDgmEn : out std_ulogic;
573  poROL_Mmio_UdpCaptDgmEn : out std_ulogic;
574  poROL_Mmio_TcpEchoCtrl : out std_ulogic_vector( 1 downto 0);
575  poROL_Mmio_TcpPostSegEn : out std_ulogic;
576  poROL_Mmio_TcpCaptSegEn : out std_ulogic;
577  ---- APP_RDROL --------------------
578  piROL_Mmio_RdReg : in std_ulogic_vector( 15 downto 0);
579  ---- APP_WRROL --------------------
580  poROL_Mmio_WrReg : out std_ulogic_vector( 15 downto 0);
581 
582  --------------------------------------------------------
583  -- ROLE / Fmc / Management Interface
584  --------------------------------------------------------
585  poROL_Fmc_Rank : out std_logic_vector(31 downto 0);
586  poROL_Fmc_Size : out std_logic_vector(31 downto 0);
587 
588  poVoid : out std_ulogic
589 
590  );
591  end component Shell_Themisto;
592 
593 
594  -- [INFO] The ROLE component is declared in the corresponding TOP package.
595  -- not this time
596  -- to declare the component in the pkg seems not to work for Verilog or .dcp modules
597  component Role_Themisto
598  port (
599 
600  ------------------------------------------------------
601  -- TOP / Global Input Clock and Reset Interface
602  ------------------------------------------------------
603  piSHL_156_25Clk : in std_ulogic;
604  piSHL_156_25Rst : in std_ulogic;
605  -- LY7 Enable and Reset
606  piMMIO_Ly7_Rst : in std_ulogic;
607  piMMIO_Ly7_En : in std_ulogic;
608 
609  ------------------------------------------------------
610  -- SHELL / Role / Nts0 / Udp Interface
611  ------------------------------------------------------
612  ---- Input AXI-Write Stream Interface ----------
613  siNRC_Udp_Data_tdata : in std_ulogic_vector( 63 downto 0);
614  siNRC_Udp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
615  siNRC_Udp_Data_tvalid : in std_ulogic;
616  siNRC_Udp_Data_tlast : in std_ulogic;
617  siNRC_Udp_Data_tready : out std_ulogic;
618  ---- Output AXI-Write Stream Interface ---------
619  soNRC_Udp_Data_tdata : out std_ulogic_vector( 63 downto 0);
620  soNRC_Udp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
621  soNRC_Udp_Data_tvalid : out std_ulogic;
622  soNRC_Udp_Data_tlast : out std_ulogic;
623  soNRC_Udp_Data_tready : in std_ulogic;
624  -- Open Port vector
625  poROL_Nrc_Udp_Rx_ports : out std_ulogic_vector( 31 downto 0);
626  -- ROLE <-> NRC Meta Interface
627  soROLE_Nrc_Udp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
628  soROLE_Nrc_Udp_Meta_TVALID : out std_ulogic;
629  soROLE_Nrc_Udp_Meta_TREADY : in std_ulogic;
630  soROLE_Nrc_Udp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
631  soROLE_Nrc_Udp_Meta_TLAST : out std_ulogic;
632  siNRC_Role_Udp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
633  siNRC_Role_Udp_Meta_TVALID : in std_ulogic;
634  siNRC_Role_Udp_Meta_TREADY : out std_ulogic;
635  siNRC_Role_Udp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
636  siNRC_Role_Udp_Meta_TLAST : in std_ulogic;
637 
638  ------------------------------------------------------
639  -- SHELL / Role / Nts0 / Tcp Interface
640  ------------------------------------------------------
641  ---- Input AXI-Write Stream Interface ----------
642  siNRC_Tcp_Data_tdata : in std_ulogic_vector( 63 downto 0);
643  siNRC_Tcp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
644  siNRC_Tcp_Data_tvalid : in std_ulogic;
645  siNRC_Tcp_Data_tlast : in std_ulogic;
646  siNRC_Tcp_Data_tready : out std_ulogic;
647  ---- Output AXI-Write Stream Interface ---------
648  soNRC_Tcp_Data_tdata : out std_ulogic_vector( 63 downto 0);
649  soNRC_Tcp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
650  soNRC_Tcp_Data_tvalid : out std_ulogic;
651  soNRC_Tcp_Data_tlast : out std_ulogic;
652  soNRC_Tcp_Data_tready : in std_ulogic;
653  -- Open Port vector
654  poROL_Nrc_Tcp_Rx_ports : out std_ulogic_vector( 31 downto 0);
655  -- ROLE <-> NRC Meta Interface
656  soROLE_Nrc_Tcp_Meta_TDATA : out std_ulogic_vector( 63 downto 0);
657  soROLE_Nrc_Tcp_Meta_TVALID : out std_ulogic;
658  soROLE_Nrc_Tcp_Meta_TREADY : in std_ulogic;
659  soROLE_Nrc_Tcp_Meta_TKEEP : out std_ulogic_vector( 7 downto 0);
660  soROLE_Nrc_Tcp_Meta_TLAST : out std_ulogic;
661  siNRC_Role_Tcp_Meta_TDATA : in std_ulogic_vector( 63 downto 0);
662  siNRC_Role_Tcp_Meta_TVALID : in std_ulogic;
663  siNRC_Role_Tcp_Meta_TREADY : out std_ulogic;
664  siNRC_Role_Tcp_Meta_TKEEP : in std_ulogic_vector( 7 downto 0);
665  siNRC_Role_Tcp_Meta_TLAST : in std_ulogic;
666 
667 
668  ------------------------------------------------------
669  -- SHELL / Mem / Mp0 Interface
670  ------------------------------------------------------
671  ---- Memory Port #0 / S2MM-AXIS -------------
672  ------ Stream Read Command ---------
673  soMEM_Mp0_RdCmd_tdata : out std_ulogic_vector( 79 downto 0);
674  soMEM_Mp0_RdCmd_tvalid : out std_ulogic;
675  soMEM_Mp0_RdCmd_tready : in std_ulogic;
676  ------ Stream Read Status ----------
677  siMEM_Mp0_RdSts_tdata : in std_ulogic_vector( 7 downto 0);
678  siMEM_Mp0_RdSts_tvalid : in std_ulogic;
679  siMEM_Mp0_RdSts_tready : out std_ulogic;
680  ------ Stream Data Input Channel ---
681  siMEM_Mp0_Read_tdata : in std_ulogic_vector(511 downto 0);
682  siMEM_Mp0_Read_tkeep : in std_ulogic_vector( 63 downto 0);
683  siMEM_Mp0_Read_tlast : in std_ulogic;
684  siMEM_Mp0_Read_tvalid : in std_ulogic;
685  siMEM_Mp0_Read_tready : out std_ulogic;
686  ------ Stream Write Command --------
687  soMEM_Mp0_WrCmd_tdata : out std_ulogic_vector( 79 downto 0);
688  soMEM_Mp0_WrCmd_tvalid : out std_ulogic;
689  soMEM_Mp0_WrCmd_tready : in std_ulogic;
690  ------ Stream Write Status ---------
691  siMEM_Mp0_WrSts_tvalid : in std_ulogic;
692  siMEM_Mp0_WrSts_tdata : in std_ulogic_vector( 7 downto 0);
693  siMEM_Mp0_WrSts_tready : out std_ulogic;
694  ------ Stream Data Output Channel --
695  soMEM_Mp0_Write_tdata : out std_ulogic_vector(511 downto 0);
696  soMEM_Mp0_Write_tkeep : out std_ulogic_vector( 63 downto 0);
697  soMEM_Mp0_Write_tlast : out std_ulogic;
698  soMEM_Mp0_Write_tvalid : out std_ulogic;
699  soMEM_Mp0_Write_tready : in std_ulogic;
700 
701  ------------------------------------------------------
702  -- SHELL / Mem / Mp1 Interface
703  ------------------------------------------------------
704  moMEM_Mp1_AWID : out std_ulogic_vector(7 downto 0);
705  moMEM_Mp1_AWADDR : out std_ulogic_vector(32 downto 0);
706  moMEM_Mp1_AWLEN : out std_ulogic_vector(7 downto 0);
707  moMEM_Mp1_AWSIZE : out std_ulogic_vector(2 downto 0);
708  moMEM_Mp1_AWBURST : out std_ulogic_vector(1 downto 0);
709  moMEM_Mp1_AWVALID : out std_ulogic;
710  moMEM_Mp1_AWREADY : in std_ulogic;
711  moMEM_Mp1_WDATA : out std_ulogic_vector(511 downto 0);
712  moMEM_Mp1_WSTRB : out std_ulogic_vector(63 downto 0);
713  moMEM_Mp1_WLAST : out std_ulogic;
714  moMEM_Mp1_WVALID : out std_ulogic;
715  moMEM_Mp1_WREADY : in std_ulogic;
716  moMEM_Mp1_BID : in std_ulogic_vector(7 downto 0);
717  moMEM_Mp1_BRESP : in std_ulogic_vector(1 downto 0);
718  moMEM_Mp1_BVALID : in std_ulogic;
719  moMEM_Mp1_BREADY : out std_ulogic;
720  moMEM_Mp1_ARID : out std_ulogic_vector(7 downto 0);
721  moMEM_Mp1_ARADDR : out std_ulogic_vector(32 downto 0);
722  moMEM_Mp1_ARLEN : out std_ulogic_vector(7 downto 0);
723  moMEM_Mp1_ARSIZE : out std_ulogic_vector(2 downto 0);
724  moMEM_Mp1_ARBURST : out std_ulogic_vector(1 downto 0);
725  moMEM_Mp1_ARVALID : out std_ulogic;
726  moMEM_Mp1_ARREADY : in std_ulogic;
727  moMEM_Mp1_RID : in std_ulogic_vector(7 downto 0);
728  moMEM_Mp1_RDATA : in std_ulogic_vector(511 downto 0);
729  moMEM_Mp1_RRESP : in std_ulogic_vector(1 downto 0);
730  moMEM_Mp1_RLAST : in std_ulogic;
731  moMEM_Mp1_RVALID : in std_ulogic;
732  moMEM_Mp1_RREADY : out std_ulogic;
733 
734  -- leave declarations here for higher privileged Roles?
735  ----------------------------------------------------------
736  ---- SHELL / Mmio / AppFlash Interface
737  ----------------------------------------------------------
738  ------ [DIAG_CTRL_1] -----------------
739  --piSHL_Mmio_Mc1_MemTestCtrl : in std_ulogic_vector( 1 downto 0);
740  ------ [DIAG_STAT_1] -----------------
741  --poSHL_Mmio_Mc1_MemTestStat : out std_ulogic_vector( 1 downto 0);
742  ------ [DIAG_CTRL_2] -----------------
743  --piSHL_Mmio_UdpEchoCtrl : in std_ulogic_vector( 1 downto 0);
744  --piSHL_Mmio_UdpPostDgmEn : in std_ulogic;
745  --piSHL_Mmio_UdpCaptDgmEn : in std_ulogic;
746  --piSHL_Mmio_TcpEchoCtrl : in std_ulogic_vector( 1 downto 0);
747  --piSHL_Mmio_TcpPostSegEn : in std_ulogic;
748  --piSHL_Mmio_TcpCaptSegEn : in std_ulogic;
749  ---- [APP_RDROL] -------------------
750  poSHL_Mmio_RdReg : out std_ulogic_vector( 15 downto 0);
751  ----- [APP_WRROL] --------------------
752  --piSHL_Mmio_WrReg : in std_ulogic_vector( 15 downto 0);
753 
754  --------------------------------------------------------
755  -- TOP : Secondary Clock (Asynchronous)
756  --------------------------------------------------------
757  piTOP_250_00Clk : in std_ulogic; -- Freerunning
758 
759  ------------------------------------------------
760  -- FMC Interface
761  ------------------------------------------------
762  piFMC_ROLE_rank : in std_logic_vector(31 downto 0);
763  piFMC_ROLE_size : in std_logic_vector(31 downto 0);
764 
765  poVoid : out std_ulogic
766  );
767  end component Role_Themisto;
768 
769 begin
770 
771  --===========================================================================
772  --== INST: INPUT USER CLOCK BUFFERS
773  --===========================================================================
774  CLKBUF0 : IBUFDS
775  generic map (
776  DQS_BIAS => "FALSE" -- (FALSE, TRUE)
777  )
778  port map (
779  O => sTOP_156_25Clk,
780  I => piCLKT_Usr0Clk_p,
781  IB => piCLKT_Usr0Clk_n
782  );
783 
784  CLKBUF1 : IBUFDS
785  generic map (
786  DQS_BIAS => "FALSE" -- (FALSE, TRUE)
787  )
788  port map (
789  O => sTOP_250_00Clk,
790  I => piCLKT_Usr1Clk_p,
791  IB => piCLKT_Usr1Clk_n
792  );
793 
794  --===========================================================================
795  --== INST: METASTABILITY HARDENED BLOCK FOR THE SYSTEM RESET (Active high)
796  --== [INFO] Note that we instantiate 2 or 3 library primitives rather than
797  --== a VHDL process because it makes it easier to apply the "ASYNC_REG"
798  --== property to those instances.
799  --===========================================================================
800  TOP_META_RST : HARD_SYNC
801  generic map (
802  INIT => '0', -- Initial values, '0', '1'
803  IS_CLK_INVERTED => '0', -- Programmable inversion on CLK input
804  LATENCY => 2 -- 2-3
805  )
806  port map (
807  CLK => sTOP_156_25Clk,
808  DIN => piPSOC_Fcfg_Rst_n,
809  DOUT => sTOP_156_25Rst_n
810  );
811  sTOP_156_25Rst <= not sTOP_156_25Rst_n;
812 
813  --===========================================================================
814  --== INST: BITSTREAM IDENTIFICATION BLOCK with USR_ACCESSE2 PRIMITIVE
815  --== [INFO] This component provides direct FPGA logic access to the 32-bit
816  --== value stored by the FPGA bitstream. We use this register to retrieve
817  --== an accurate timestamp corresponding to the date of the bitstream
818  --== generation (note that we don't track the sminiutes and seconds).
819  --============================================================================
820  TOP_TIMESTAMP : USR_ACCESSE2
821  port map (
822  CFGCLK => open, -- Not used in the static mode
823  DATA => sTOP_Timestamp, -- 32-bit configuration data
824  DATAVALID => open -- Not used in the static mode
825  );
826 
827  --==========================================================================
828  --== INST: SHELL FOR FMKU60
829  --== This version of the SHELL has the following user interfaces:
830  --== - one UDP, one TCP, and two MemoryPort interfaces.
831  --==========================================================================
832  SHELL : Shell_Themisto
833  generic map (
834  gSecurityPriviledges => "super",
835  gBitstreamUsage => "flash",
836  gMmioAddrWidth => gEmifAddrWidth,
837  gMmioDataWidth => gEmifDataWidth
838  )
839  port map (
840  ------------------------------------------------------
841  -- TOP / Input Clocks and Resets from topFMKU60
842  ------------------------------------------------------
843  piTOP_156_25Rst => sTOP_156_25Rst,
844  piTOP_156_25Clk => sTOP_156_25Clk,
845 
846  ------------------------------------------------------
847  -- TOP / Bitstream Identification
848  ------------------------------------------------------
849  piTOP_Timestamp => sTOP_Timestamp,
850 
851  ------------------------------------------------------
852  -- CLKT / Clock Tree Interface
853  ------------------------------------------------------
854  piCLKT_Mem0Clk_n => piCLKT_Mem0Clk_n,
855  piCLKT_Mem0Clk_p => piCLKT_Mem0Clk_p,
856  piCLKT_Mem1Clk_n => piCLKT_Mem1Clk_n,
857  piCLKT_Mem1Clk_p => piCLKT_Mem1Clk_p,
858  piCLKT_10GeClk_n => piCLKT_10GeClk_n,
859  piCLKT_10GeClk_p => piCLKT_10GeClk_p,
860 
861  ------------------------------------------------------
862  -- PSOC / External Memory Interface => Emif)
863  ------------------------------------------------------
864  piPSOC_Emif_Clk => piPSOC_Emif_Clk,
865  piPSOC_Emif_Cs_n => piPSOC_Emif_Cs_n,
866  piPSOC_Emif_We_n => piPSOC_Emif_We_n,
867  piPSOC_Emif_Oe_n => piPSOC_Emif_Oe_n,
868  piPSOC_Emif_AdS_n => piPSOC_Emif_AdS_n,
869  piPSOC_Emif_Addr => piPSOC_Emif_Addr,
870  pioPSOC_Emif_Data => pioPSOC_Emif_Data,
871 
872  ------------------------------------------------------
873  -- LED / Shl / Heart Beat Interface => Yellow LED)
874  ------------------------------------------------------
875  poLED_HeartBeat_n => poLED_HeartBeat_n,
876 
877  ------------------------------------------------------
878  -- DDR4 / Memory Channel 0 Interface => (Mc0)
879  ------------------------------------------------------
880  pioDDR4_Mem_Mc0_DmDbi_n => pioDDR4_Mem_Mc0_DmDbi_n,
881  pioDDR4_Mem_Mc0_Dq => pioDDR4_Mem_Mc0_Dq,
882  pioDDR4_Mem_Mc0_Dqs_n => pioDDR4_Mem_Mc0_Dqs_n,
883  pioDDR4_Mem_Mc0_Dqs_p => pioDDR4_Mem_Mc0_Dqs_p,
884  poDDR4_Mem_Mc0_Act_n => poDDR4_Mem_Mc0_Act_n,
885  poDDR4_Mem_Mc0_Adr => poDDR4_Mem_Mc0_Adr,
886  poDDR4_Mem_Mc0_Ba => poDDR4_Mem_Mc0_Ba,
887  poDDR4_Mem_Mc0_Bg => poDDR4_Mem_Mc0_Bg,
888  poDDR4_Mem_Mc0_Cke => poDDR4_Mem_Mc0_Cke,
889  poDDR4_Mem_Mc0_Odt => poDDR4_Mem_Mc0_Odt,
890  poDDR4_Mem_Mc0_Cs_n => poDDR4_Mem_Mc0_Cs_n,
891  poDDR4_Mem_Mc0_Ck_n => poDDR4_Mem_Mc0_Ck_n,
892  poDDR4_Mem_Mc0_Ck_p => poDDR4_Mem_Mc0_Ck_p,
893  poDDR4_Mem_Mc0_Reset_n => poDDR4_Mem_Mc0_Reset_n,
894 
895  ------------------------------------------------------
896  -- DDR4 / Shl / Memory Channel 1 Interface (Mc1)
897  ------------------------------------------------------
898  pioDDR4_Mem_Mc1_DmDbi_n => pioDDR4_Mem_Mc1_DmDbi_n,
899  pioDDR4_Mem_Mc1_Dq => pioDDR4_Mem_Mc1_Dq,
900  pioDDR4_Mem_Mc1_Dqs_n => pioDDR4_Mem_Mc1_Dqs_n,
901  pioDDR4_Mem_Mc1_Dqs_p => pioDDR4_Mem_Mc1_Dqs_p,
902  poDDR4_Mem_Mc1_Act_n => poDDR4_Mem_Mc1_Act_n,
903  poDDR4_Mem_Mc1_Adr => poDDR4_Mem_Mc1_Adr,
904  poDDR4_Mem_Mc1_Ba => poDDR4_Mem_Mc1_Ba,
905  poDDR4_Mem_Mc1_Bg => poDDR4_Mem_Mc1_Bg,
906  poDDR4_Mem_Mc1_Cke => poDDR4_Mem_Mc1_Cke,
907  poDDR4_Mem_Mc1_Odt => poDDR4_Mem_Mc1_Odt,
908  poDDR4_Mem_Mc1_Cs_n => poDDR4_Mem_Mc1_Cs_n,
909  poDDR4_Mem_Mc1_Ck_n => poDDR4_Mem_Mc1_Ck_n,
910  poDDR4_Mem_Mc1_Ck_p => poDDR4_Mem_Mc1_Ck_p,
911  poDDR4_Mem_Mc1_Reset_n => poDDR4_Mem_Mc1_Reset_n,
912 
913  ------------------------------------------------------
914  -- ECON / Edge / Connector Interface (SPD08-200)
915  ------------------------------------------------------
916  piECON_Eth_10Ge0_n => piECON_Eth_10Ge0_n,
917  piECON_Eth_10Ge0_p => piECON_Eth_10Ge0_p,
918  poECON_Eth_10Ge0_n => poECON_Eth_10Ge0_n,
919  poECON_Eth_10Ge0_p => poECON_Eth_10Ge0_p,
920 
921  ------------------------------------------------------
922  -- ROLE / Reset and Clock Interfaces
923  ------------------------------------------------------
924  poROL_156_25Clk => sSHL_156_25Clk,
925  poROL_156_25Rst => sSHL_156_25Rst,
926 
927  ------------------------------------------------------
928  -- ROLE / Shl / Nts0 / Udp Interface
929  ------------------------------------------------------
930  -- Input AXI-Write Stream Interface ----------
931  siROL_Nts_Udp_Data_tdata => sROL_Shl_Nts0_Udp_Axis_tdata,
932  siROL_Nts_Udp_Data_tkeep => sROL_Shl_Nts0_Udp_Axis_tkeep,
933  siROL_Nts_Udp_Data_tlast => sROL_Shl_Nts0_Udp_Axis_tlast,
934  siROL_Nts_Udp_Data_tvalid => sROL_Shl_Nts0_Udp_Axis_tvalid,
935  siROL_Nts_Udp_Data_tready => sSHL_Rol_Nts0_Udp_Axis_tready,
936  -- Output AXI-Write Stream Interface ---------
937  soROL_Nts_Udp_Data_tdata => sSHL_Rol_Nts0_Udp_Axis_tdata ,
938  soROL_Nts_Udp_Data_tkeep => sSHL_Rol_Nts0_Udp_Axis_tkeep,
939  soROL_Nts_Udp_Data_tlast => sSHL_Rol_Nts0_Udp_Axis_tlast ,
940  soROL_Nts_Udp_Data_tvalid => sSHL_Rol_Nts0_Udp_Axis_tvalid,
941  soROL_Nts_Udp_Data_tready => sROL_Shl_Nts0_Udp_Axis_tready,
942  -- Open Port vector
943  piROL_Nrc_Udp_Rx_ports => sROL_Nrc_Udp_Rx_ports ,
944  -- ROLE <-> NRC Meta Interface
945  siROLE_Nrc_Udp_Meta_TDATA => sROLE_Nrc_Udp_Meta_TDATA ,
946  siROLE_Nrc_Udp_Meta_TVALID => sROLE_Nrc_Udp_Meta_TVALID ,
947  siROLE_Nrc_Udp_Meta_TREADY => sROLE_Nrc_Udp_Meta_TREADY ,
948  siROLE_Nrc_Udp_Meta_TKEEP => sROLE_Nrc_Udp_Meta_TKEEP ,
949  siROLE_Nrc_Udp_Meta_TLAST => sROLE_Nrc_Udp_Meta_TLAST ,
950  soNRC_Role_Udp_Meta_TDATA => sNRC_Role_Udp_Meta_TDATA ,
951  soNRC_Role_Udp_Meta_TVALID => sNRC_Role_Udp_Meta_TVALID ,
952  soNRC_Role_Udp_Meta_TREADY => sNRC_Role_Udp_Meta_TREADY ,
953  soNRC_Role_Udp_Meta_TKEEP => sNRC_Role_Udp_Meta_TKEEP ,
954  soNRC_Role_Udp_Meta_TLAST => sNRC_Role_Udp_Meta_TLAST ,
955 
956  ------------------------------------------------------
957  -- ROLE / Shl /Nts0 / Tcp Interfaces
958  ------------------------------------------------------
959  -- Input AXI-Write Stream Interface ----------
960  siROL_Nts_Tcp_Data_tdata => sROL_Shl_Nts0_Tcp_Axis_tdata,
961  siROL_Nts_Tcp_Data_tkeep => sROL_Shl_Nts0_Tcp_Axis_tkeep,
962  siROL_Nts_Tcp_Data_tlast => sROL_Shl_Nts0_Tcp_Axis_tlast,
963  siROL_Nts_Tcp_Data_tvalid => sROL_Shl_Nts0_Tcp_Axis_tvalid,
964  siROL_Nts_Tcp_Data_tready => sSHL_Rol_Nts0_Tcp_Axis_tready,
965  -- Output AXI-Write Stream Interface ---------
966  soROL_Nts_Tcp_Data_tdata => sSHL_Rol_Nts0_Tcp_Axis_tdata ,
967  soROL_Nts_Tcp_Data_tkeep => sSHL_Rol_Nts0_Tcp_Axis_tkeep,
968  soROL_Nts_Tcp_Data_tlast => sSHL_Rol_Nts0_Tcp_Axis_tlast ,
969  soROL_Nts_Tcp_Data_tvalid => sSHL_Rol_Nts0_Tcp_Axis_tvalid,
970  soROL_Nts_Tcp_Data_tready => sROL_Shl_Nts0_Tcp_Axis_tready,
971  -- Open Port vector
972  piROL_Nrc_Tcp_Rx_ports => sROL_Nrc_Tcp_Rx_ports ,
973  -- ROLE <-> NRC Meta Interface
974  siROLE_Nrc_Tcp_Meta_TDATA => sROLE_Nrc_Tcp_Meta_TDATA ,
975  siROLE_Nrc_Tcp_Meta_TVALID => sROLE_Nrc_Tcp_Meta_TVALID ,
976  siROLE_Nrc_Tcp_Meta_TREADY => sROLE_Nrc_Tcp_Meta_TREADY ,
977  siROLE_Nrc_Tcp_Meta_TKEEP => sROLE_Nrc_Tcp_Meta_TKEEP ,
978  siROLE_Nrc_Tcp_Meta_TLAST => sROLE_Nrc_Tcp_Meta_TLAST ,
979  soNRC_Role_Tcp_Meta_TDATA => sNRC_Role_Tcp_Meta_TDATA ,
980  soNRC_Role_Tcp_Meta_TVALID => sNRC_Role_Tcp_Meta_TVALID ,
981  soNRC_Role_Tcp_Meta_TREADY => sNRC_Role_Tcp_Meta_TREADY ,
982  soNRC_Role_Tcp_Meta_TKEEP => sNRC_Role_Tcp_Meta_TKEEP ,
983  soNRC_Role_Tcp_Meta_TLAST => sNRC_Role_Tcp_Meta_TLAST ,
984 
985  ------------------------------------------------------
986  -- ROLE / Mem / Mp0 Interface
987  ------------------------------------------------------
988  -- Memory Port #0 / S2MM-AXIS ------------------
989  ---- Stream Read Command ---------
990  siROL_Mem_Mp0_RdCmd_tdata => ssROL_SHL_Mem_Mp0_RdCmd_tdata,
991  siROL_Mem_Mp0_RdCmd_tvalid => ssROL_SHL_Mem_Mp0_RdCmd_tvalid,
992  siROL_Mem_Mp0_RdCmd_tready => ssROL_SHL_Mem_Mp0_RdCmd_tready,
993  ---- Stream Read Status ----------
994  soROL_Mem_Mp0_RdSts_tdata => ssSHL_ROL_Mem_Mp0_RdSts_tdata,
995  soROL_Mem_Mp0_RdSts_tvalid => ssSHL_ROL_Mem_Mp0_RdSts_tvalid,
996  soROL_Mem_Mp0_RdSts_tready => ssSHL_ROL_Mem_Mp0_RdSts_tready,
997  ---- Stream Data Output Channel --
998  soROL_Mem_Mp0_Read_tdata => ssSHL_ROL_Mem_Mp0_Read_tdata,
999  soROL_Mem_Mp0_Read_tkeep => ssSHL_ROL_Mem_Mp0_Read_tkeep,
1000  soROL_Mem_Mp0_Read_tlast => ssSHL_ROL_Mem_Mp0_Read_tlast,
1001  soROL_Mem_Mp0_Read_tvalid => ssSHL_ROL_Mem_Mp0_Read_tvalid,
1002  soROL_Mem_Mp0_Read_tready => ssSHL_ROL_Mem_Mp0_Read_tready,
1003  ---- Stream Write Command --------
1004  siROL_Mem_Mp0_WrCmd_tdata => ssROL_SHL_Mem_Mp0_WrCmd_tdata,
1005  siROL_Mem_Mp0_WrCmd_tvalid => ssROL_SHL_Mem_Mp0_WrCmd_tvalid,
1006  siROL_Mem_Mp0_WrCmd_tready => ssROL_SHL_Mem_Mp0_WrCmd_tready,
1007  ---- Stream Write Status ---------
1008  soROL_Mem_Mp0_WrSts_tvalid => ssSHL_ROL_Mem_Mp0_WrSts_tvalid,
1009  soROL_Mem_Mp0_WrSts_tdata => ssSHL_ROL_Mem_Mp0_WrSts_tdata,
1010  soROL_Mem_Mp0_WrSts_tready => ssSHL_ROL_Mem_Mp0_WrSts_tready,
1011  ---- Stream Data Input Channel ---
1012  siROL_Mem_Mp0_Write_tdata => ssROL_SHL_Mem_Mp0_Write_tdata,
1013  siROL_Mem_Mp0_Write_tkeep => ssROL_SHL_Mem_Mp0_Write_tkeep,
1014  siROL_Mem_Mp0_Write_tlast => ssROL_SHL_Mem_Mp0_Write_tlast,
1015  siROL_Mem_Mp0_Write_tvalid => ssROL_SHL_Mem_Mp0_Write_tvalid,
1016  siROL_Mem_Mp0_Write_tready => ssROL_SHL_Mem_Mp0_Write_tready,
1017 
1018  ------------------------------------------------------
1019  -- ROLE / Mem / Mp1 Interface
1020  ------------------------------------------------------
1021  miROL_Mem_Mp1_AWID => smROL_SHL_Mem_Mp1_AWID ,
1022  miROL_Mem_Mp1_AWADDR => smROL_SHL_Mem_Mp1_AWADDR ,
1023  miROL_Mem_Mp1_AWLEN => smROL_SHL_Mem_Mp1_AWLEN ,
1024  miROL_Mem_Mp1_AWSIZE => smROL_SHL_Mem_Mp1_AWSIZE ,
1025  miROL_Mem_Mp1_AWBURST => smROL_SHL_Mem_Mp1_AWBURST ,
1026  miROL_Mem_Mp1_AWVALID => smROL_SHL_Mem_Mp1_AWVALID ,
1027  miROL_Mem_Mp1_AWREADY => smROL_SHL_Mem_Mp1_AWREADY ,
1028  miROL_Mem_Mp1_WDATA => smROL_SHL_Mem_Mp1_WDATA ,
1029  miROL_Mem_Mp1_WSTRB => smROL_SHL_Mem_Mp1_WSTRB ,
1030  miROL_Mem_Mp1_WLAST => smROL_SHL_Mem_Mp1_WLAST ,
1031  miROL_Mem_Mp1_WVALID => smROL_SHL_Mem_Mp1_WVALID ,
1032  miROL_Mem_Mp1_WREADY => smROL_SHL_Mem_Mp1_WREADY ,
1033  miROL_Mem_Mp1_BID => smROL_SHL_Mem_Mp1_BID ,
1034  miROL_Mem_Mp1_BRESP => smROL_SHL_Mem_Mp1_BRESP ,
1035  miROL_Mem_Mp1_BVALID => smROL_SHL_Mem_Mp1_BVALID ,
1036  miROL_Mem_Mp1_BREADY => smROL_SHL_Mem_Mp1_BREADY ,
1037  miROL_Mem_Mp1_ARID => smROL_SHL_Mem_Mp1_ARID ,
1038  miROL_Mem_Mp1_ARADDR => smROL_SHL_Mem_Mp1_ARADDR ,
1039  miROL_Mem_Mp1_ARLEN => smROL_SHL_Mem_Mp1_ARLEN ,
1040  miROL_Mem_Mp1_ARSIZE => smROL_SHL_Mem_Mp1_ARSIZE ,
1041  miROL_Mem_Mp1_ARBURST => smROL_SHL_Mem_Mp1_ARBURST ,
1042  miROL_Mem_Mp1_ARVALID => smROL_SHL_Mem_Mp1_ARVALID ,
1043  miROL_Mem_Mp1_ARREADY => smROL_SHL_Mem_Mp1_ARREADY ,
1044  miROL_Mem_Mp1_RID => smROL_SHL_Mem_Mp1_RID ,
1045  miROL_Mem_Mp1_RDATA => smROL_SHL_Mem_Mp1_RDATA ,
1046  miROL_Mem_Mp1_RRESP => smROL_SHL_Mem_Mp1_RRESP ,
1047  miROL_Mem_Mp1_RLAST => smROL_SHL_Mem_Mp1_RLAST ,
1048  miROL_Mem_Mp1_RVALID => smROL_SHL_Mem_Mp1_RVALID ,
1049  miROL_Mem_Mp1_RREADY => smROL_SHL_Mem_Mp1_RREADY ,
1050 
1051  ------------------------------------------------------
1052  -- ROLE / Mmio / AppFlash Interface
1053  ------------------------------------------------------
1054  ---- [PHY_RESET] -----------------
1055  poROL_Mmio_Ly7Rst => (sSHL_ROL_Mmio_Ly7Rst),
1056  ---- [PHY_ENABLE] --------------
1057  poROL_Mmio_Ly7En => (sSHL_ROL_Mmio_Ly7En),
1058  ---- [DIAG_CTRL_1] ---------------
1059  poROL_Mmio_Mc1_MemTestCtrl => sSHL_ROL_Mmio_Mc1_MemTestCtrl,
1060  ---- [DIAG_STAT_1] ---------------
1061  piROL_Mmio_Mc1_MemTestStat => sROL_SHL_Mmio_Mc1_MemTestStat,
1062  ---- [DIAG_CTRL_2] ---------------
1063  poROL_Mmio_UdpEchoCtrl => sSHL_ROL_Mmio_UdpEchoCtrl,
1064  poROL_Mmio_UdpPostDgmEn => sSHL_ROL_Mmio_UdpPostDgmEn,
1065  poROL_Mmio_UdpCaptDgmEn => sSHL_ROL_Mmio_UdpCaptDgmEn,
1066  poROL_Mmio_TcpEchoCtrl => sSHL_ROL_Mmio_TcpEchoCtrl,
1067  poROL_Mmio_TcpPostSegEn => sSHL_ROL_Mmio_TcpPostSegEn,
1068  poROL_Mmio_TcpCaptSegEn => sSHL_ROL_Mmio_TcpCaptSegEn,
1069  ---- [APP_RDROL] -----------------
1070  piROL_Mmio_RdReg => sROL_SHL_Mmio_RdReg,
1071  ---- [APP_WRROL] -----------------
1072  poROL_Mmio_WrReg => sSHL_ROL_Mmio_WrReg,
1073 
1074  --------------------------------------------------------
1075  -- ROLE / Fmc / Management Interface
1076  --------------------------------------------------------
1077  poROL_Fmc_Rank => sSHL_ROL_Fmc_Rank,
1078  poROL_Fmc_Size => sSHL_ROL_Fmc_Size,
1079 
1080  poVoid => open
1081 
1082  ); -- End of SuperShell instantiation
1083 
1084 
1085  --==========================================================================
1086  -- INST: ROLE FOR FMKU60
1087  --==========================================================================
1088 
1089  -- drive MMIO signals if NOT used by the ROLE
1090  sROL_SHL_Mmio_Mc1_MemTestStat <= (others => '0');
1091  --sROL_SHL_Mmio_RdReg <= x"CFCF";
1092 
1093  -- security consideration: if we want to reset layer 7, the user should not be able to avoid it
1094  sROL_reset_combinded <= sSHL_156_25Rst or sSHL_ROL_Mmio_Ly7Rst;
1095 
1096  ROLE : Role_Themisto
1097  port map (
1098 
1099  ------------------------------------------------------
1100  -- SHELL / Global Input Clock and Reset Interface
1101  ------------------------------------------------------
1102  piSHL_156_25Clk => sSHL_156_25Clk,
1103  --piSHL_156_25Rst => sSHL_156_25Rst,
1104  piSHL_156_25Rst => sROL_reset_combinded,
1105  -- LY7 Enable and Reset
1106  piMMIO_Ly7_Rst => sSHL_ROL_Mmio_Ly7Rst,
1107  piMMIO_Ly7_En => sSHL_ROL_Mmio_Ly7En,
1108 
1109  ------------------------------------------------------
1110  -- SHELL / Role / Nts0 / Udp Interface
1111  ------------------------------------------------------
1112  -- Input AXI-Write Stream Interface ----------
1113  siNRC_Udp_Data_tdata => sSHL_Rol_Nts0_Udp_Axis_tdata,
1114  siNRC_Udp_Data_tkeep => sSHL_Rol_Nts0_Udp_Axis_tkeep,
1115  siNRC_Udp_Data_tlast => sSHL_Rol_Nts0_Udp_Axis_tlast,
1116  siNRC_Udp_Data_tvalid => sSHL_Rol_Nts0_Udp_Axis_tvalid,
1117  siNRC_Udp_Data_tready => sROL_Shl_Nts0_Udp_Axis_tready,
1118  -- Output AXI-Write Stream Interface ---------
1119  soNRC_Udp_Data_tdata => sROL_Shl_Nts0_Udp_Axis_tdata,
1120  soNRC_Udp_Data_tkeep => sROL_Shl_Nts0_Udp_Axis_tkeep,
1121  soNRC_Udp_Data_tlast => sROL_Shl_Nts0_Udp_Axis_tlast,
1122  soNRC_Udp_Data_tvalid => sROL_Shl_Nts0_Udp_Axis_tvalid,
1123  soNRC_Udp_Data_tready => sSHL_Rol_Nts0_Udp_Axis_tready,
1124  -- Open Port vector
1125  poROL_Nrc_Udp_Rx_ports => sROL_Nrc_Udp_Rx_ports ,
1126  -- ROLE <-> NRC Meta Interface
1127  soROLE_Nrc_Udp_Meta_TDATA => sROLE_Nrc_Udp_Meta_TDATA ,
1128  soROLE_Nrc_Udp_Meta_TVALID => sROLE_Nrc_Udp_Meta_TVALID ,
1129  soROLE_Nrc_Udp_Meta_TREADY => sROLE_Nrc_Udp_Meta_TREADY ,
1130  soROLE_Nrc_Udp_Meta_TKEEP => sROLE_Nrc_Udp_Meta_TKEEP ,
1131  soROLE_Nrc_Udp_Meta_TLAST => sROLE_Nrc_Udp_Meta_TLAST ,
1132  siNRC_Role_Udp_Meta_TDATA => sNRC_Role_Udp_Meta_TDATA ,
1133  siNRC_Role_Udp_Meta_TVALID => sNRC_Role_Udp_Meta_TVALID ,
1134  siNRC_Role_Udp_Meta_TREADY => sNRC_Role_Udp_Meta_TREADY ,
1135  siNRC_Role_Udp_Meta_TKEEP => sNRC_Role_Udp_Meta_TKEEP ,
1136  siNRC_Role_Udp_Meta_TLAST => sNRC_Role_Udp_Meta_TLAST ,
1137 
1138  ------------------------------------------------------
1139  -- SHELL / Role / Nts0 / Tcp Interface
1140  ------------------------------------------------------
1141  -- Input AXI-Write Stream Interface ----------
1142  siNRC_Tcp_Data_tdata => sSHL_Rol_Nts0_Tcp_Axis_tdata,
1143  siNRC_Tcp_Data_tkeep => sSHL_Rol_Nts0_Tcp_Axis_tkeep,
1144  siNRC_Tcp_Data_tlast => sSHL_Rol_Nts0_Tcp_Axis_tlast,
1145  siNRC_Tcp_Data_tvalid => sSHL_Rol_Nts0_Tcp_Axis_tvalid,
1146  siNRC_Tcp_Data_tready => sROL_Shl_Nts0_Tcp_Axis_tready,
1147  -- Output AXI-Write Stream Interface ---------
1148  soNRC_Tcp_Data_tdata => sROL_Shl_Nts0_Tcp_Axis_tdata,
1149  soNRC_Tcp_Data_tkeep => sROL_Shl_Nts0_Tcp_Axis_tkeep,
1150  soNRC_Tcp_Data_tlast => sROL_Shl_Nts0_Tcp_Axis_tlast,
1151  soNRC_Tcp_Data_tvalid => sROL_Shl_Nts0_Tcp_Axis_tvalid,
1152  soNRC_Tcp_Data_tready => sSHL_Rol_Nts0_Tcp_Axis_tready,
1153  -- Open Port vector
1154  poROL_Nrc_Tcp_Rx_ports => sROL_Nrc_Tcp_Rx_ports ,
1155  -- ROLE <-> NRC Meta Interface
1156  soROLE_Nrc_Tcp_Meta_TDATA => sROLE_Nrc_Tcp_Meta_TDATA ,
1157  soROLE_Nrc_Tcp_Meta_TVALID => sROLE_Nrc_Tcp_Meta_TVALID ,
1158  soROLE_Nrc_Tcp_Meta_TREADY => sROLE_Nrc_Tcp_Meta_TREADY ,
1159  soROLE_Nrc_Tcp_Meta_TKEEP => sROLE_Nrc_Tcp_Meta_TKEEP ,
1160  soROLE_Nrc_Tcp_Meta_TLAST => sROLE_Nrc_Tcp_Meta_TLAST ,
1161  siNRC_Role_Tcp_Meta_TDATA => sNRC_Role_Tcp_Meta_TDATA ,
1162  siNRC_Role_Tcp_Meta_TVALID => sNRC_Role_Tcp_Meta_TVALID ,
1163  siNRC_Role_Tcp_Meta_TREADY => sNRC_Role_Tcp_Meta_TREADY ,
1164  siNRC_Role_Tcp_Meta_TKEEP => sNRC_Role_Tcp_Meta_TKEEP ,
1165  siNRC_Role_Tcp_Meta_TLAST => sNRC_Role_Tcp_Meta_TLAST ,
1166 
1167 
1168 ------------------------------------------------------
1169  -- SHELL / Mem / Mp0 Interface
1170  ------------------------------------------------------
1171  -- Memory Port #0 / S2MM-AXIS ------------------
1172  ---- Stream Read Command ---------
1173  soMEM_Mp0_RdCmd_tdata => ssROL_SHL_Mem_Mp0_RdCmd_tdata,
1174  soMEM_Mp0_RdCmd_tvalid => ssROL_SHL_Mem_Mp0_RdCmd_tvalid,
1175  soMEM_Mp0_RdCmd_tready => ssROL_SHL_Mem_Mp0_RdCmd_tready,
1176  ---- Stream Read Status ----------
1177  siMEM_Mp0_RdSts_tdata => ssSHL_ROL_Mem_Mp0_RdSts_tdata,
1178  siMEM_Mp0_RdSts_tvalid => ssSHL_ROL_Mem_Mp0_RdSts_tvalid,
1179  siMEM_Mp0_RdSts_tready => ssSHL_ROL_Mem_Mp0_RdSts_tready,
1180  ---- Stream Data Input Channel ---
1181  siMEM_Mp0_Read_tdata => ssSHL_ROL_Mem_Mp0_Read_tdata,
1182  siMEM_Mp0_Read_tkeep => ssSHL_ROL_Mem_Mp0_Read_tkeep,
1183  siMEM_Mp0_Read_tlast => ssSHL_ROL_Mem_Mp0_Read_tlast,
1184  siMEM_Mp0_Read_tvalid => ssSHL_ROL_Mem_Mp0_Read_tvalid,
1185  siMEM_Mp0_Read_tready => ssSHL_ROL_Mem_Mp0_Read_tready,
1186  ---- Stream Write Command --------
1187  soMEM_Mp0_WrCmd_tdata => ssROL_SHL_Mem_Mp0_WrCmd_tdata,
1188  soMEM_Mp0_WrCmd_tvalid => ssROL_SHL_Mem_Mp0_WrCmd_tvalid,
1189  soMEM_Mp0_WrCmd_tready => ssROL_SHL_Mem_Mp0_WrCmd_tready,
1190  ---- Stream Write Status ---------
1191  siMEM_Mp0_WrSts_tvalid => ssSHL_ROL_Mem_Mp0_WrSts_tvalid,
1192  siMEM_Mp0_WrSts_tdata => ssSHL_ROL_Mem_Mp0_WrSts_tdata,
1193  siMEM_Mp0_WrSts_tready => ssSHL_ROL_Mem_Mp0_WrSts_tready,
1194  ---- Stream Data Output Channel --
1195  soMEM_Mp0_Write_tdata => ssROL_SHL_Mem_Mp0_Write_tdata,
1196  soMEM_Mp0_Write_tkeep => ssROL_SHL_Mem_Mp0_Write_tkeep,
1197  soMEM_Mp0_Write_tlast => ssROL_SHL_Mem_Mp0_Write_tlast,
1198  soMEM_Mp0_Write_tvalid => ssROL_SHL_Mem_Mp0_Write_tvalid,
1199  soMEM_Mp0_Write_tready => ssROL_SHL_Mem_Mp0_Write_tready,
1200 
1201  ------------------------------------------------------
1202  -- SHELL / Role / Mem / Mp1 Interface
1203  ------------------------------------------------------
1204  moMEM_Mp1_AWID => smROL_SHL_Mem_Mp1_AWID ,
1205  moMEM_Mp1_AWADDR => smROL_SHL_Mem_Mp1_AWADDR ,
1206  moMEM_Mp1_AWLEN => smROL_SHL_Mem_Mp1_AWLEN ,
1207  moMEM_Mp1_AWSIZE => smROL_SHL_Mem_Mp1_AWSIZE ,
1208  moMEM_Mp1_AWBURST => smROL_SHL_Mem_Mp1_AWBURST ,
1209  moMEM_Mp1_AWVALID => smROL_SHL_Mem_Mp1_AWVALID ,
1210  moMEM_Mp1_AWREADY => smROL_SHL_Mem_Mp1_AWREADY ,
1211  moMEM_Mp1_WDATA => smROL_SHL_Mem_Mp1_WDATA ,
1212  moMEM_Mp1_WSTRB => smROL_SHL_Mem_Mp1_WSTRB ,
1213  moMEM_Mp1_WLAST => smROL_SHL_Mem_Mp1_WLAST ,
1214  moMEM_Mp1_WVALID => smROL_SHL_Mem_Mp1_WVALID ,
1215  moMEM_Mp1_WREADY => smROL_SHL_Mem_Mp1_WREADY ,
1216  moMEM_Mp1_BID => smROL_SHL_Mem_Mp1_BID ,
1217  moMEM_Mp1_BRESP => smROL_SHL_Mem_Mp1_BRESP ,
1218  moMEM_Mp1_BVALID => smROL_SHL_Mem_Mp1_BVALID ,
1219  moMEM_Mp1_BREADY => smROL_SHL_Mem_Mp1_BREADY ,
1220  moMEM_Mp1_ARID => smROL_SHL_Mem_Mp1_ARID ,
1221  moMEM_Mp1_ARADDR => smROL_SHL_Mem_Mp1_ARADDR ,
1222  moMEM_Mp1_ARLEN => smROL_SHL_Mem_Mp1_ARLEN ,
1223  moMEM_Mp1_ARSIZE => smROL_SHL_Mem_Mp1_ARSIZE ,
1224  moMEM_Mp1_ARBURST => smROL_SHL_Mem_Mp1_ARBURST ,
1225  moMEM_Mp1_ARVALID => smROL_SHL_Mem_Mp1_ARVALID ,
1226  moMEM_Mp1_ARREADY => smROL_SHL_Mem_Mp1_ARREADY ,
1227  moMEM_Mp1_RID => smROL_SHL_Mem_Mp1_RID ,
1228  moMEM_Mp1_RDATA => smROL_SHL_Mem_Mp1_RDATA ,
1229  moMEM_Mp1_RRESP => smROL_SHL_Mem_Mp1_RRESP ,
1230  moMEM_Mp1_RLAST => smROL_SHL_Mem_Mp1_RLAST ,
1231  moMEM_Mp1_RVALID => smROL_SHL_Mem_Mp1_RVALID ,
1232  moMEM_Mp1_RREADY => smROL_SHL_Mem_Mp1_RREADY ,
1233 
1234  -- leave declarations here for higher privileged Roles?
1235  --------------------------------------------------------
1236  ---- SHELL / Mmio / Flash Debug Interface
1237  --------------------------------------------------------
1238  ------ [DIAG_CTRL_1] ---------------
1239  --piSHL_Mmio_Mc1_MemTestCtrl => sSHL_ROL_Mmio_Mc1_MemTestCtrl,
1240  ------ [DIAG_STAT_1] ---------------
1241  --poSHL_Mmio_Mc1_MemTestStat => sROL_SHL_Mmio_Mc1_MemTestStat,
1242  ------ [DIAG_CTRL_2] ---------------
1243  --piSHL_Mmio_UdpEchoCtrl => sSHL_ROL_Mmio_UdpEchoCtrl,
1244  --piSHL_Mmio_UdpPostDgmEn => sSHL_ROL_Mmio_UdpPostDgmEn,
1245  --piSHL_Mmio_UdpCaptDgmEn => sSHL_ROL_Mmio_UdpCaptDgmEn,
1246  --piSHL_Mmio_TcpEchoCtrl => sSHL_ROL_Mmio_TcpEchoCtrl,
1247  --piSHL_Mmio_TcpPostSegEn => sSHL_ROL_Mmio_TcpPostSegEn,
1248  --piSHL_Mmio_TcpCaptSegEn => sSHL_ROL_Mmio_TcpCaptSegEn,
1249  ---- [APP_RDROL] -----------------
1250  poSHL_Mmio_RdReg => sROL_SHL_Mmio_RdReg,
1251  ----- [APP_WRROL] ------------------
1252  --piSHL_Mmio_WrReg => sSHL_ROL_Mmio_WrReg,
1253 
1254  ------------------------------------------------------
1255  ---- TOP : Secondary Clock (Asynchronous)
1256  ------------------------------------------------------
1257  piTOP_250_00Clk => sTOP_250_00Clk, -- Freerunning
1258 
1259  --------------------------------------------------------
1260  -- ROLE / Fmc / Management Interface
1261  --------------------------------------------------------
1262  piFMC_ROLE_rank => sSHL_ROL_Fmc_Rank,
1263  piFMC_ROLE_size => sSHL_ROL_Fmc_Size,
1264 
1265  poVoid => open
1266 
1267  ); -- End of Role instantiation
1268 
1269 end structural;
1270 
Role_Themisto
Definition: Role.vhdl:43
Role_Themisto.soNRC_Tcp_Data_tready
in soNRC_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:98
Role_Themisto.moMEM_Mp1_ARSIZE
out moMEM_Mp1_ARSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:169
Role_Themisto.moMEM_Mp1_AWADDR
out moMEM_Mp1_AWADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:151
Role_Themisto.soNRC_Udp_Data_tdata
out soNRC_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:65
Role_Themisto.soROLE_Nrc_Udp_Meta_TREADY
in soROLE_Nrc_Udp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:75
Role_Themisto.piSHL_156_25Clk
in piSHL_156_25Clkstd_ulogic
Definition: Role.vhdl:49
Role_Themisto.moMEM_Mp1_RREADY
out moMEM_Mp1_RREADYstd_ulogic
Definition: Role.vhdl:178
Role_Themisto.soROLE_Nrc_Udp_Meta_TKEEP
out soROLE_Nrc_Udp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:76
Role_Themisto.piSHL_156_25Rst
in piSHL_156_25Rststd_ulogic
Definition: Role.vhdl:50
Role_Themisto.moMEM_Mp1_RLAST
in moMEM_Mp1_RLASTstd_ulogic
Definition: Role.vhdl:176
Role_Themisto.siNRC_Udp_Data_tlast
in siNRC_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:62
Role_Themisto.siMEM_Mp0_Read_tready
out siMEM_Mp0_Read_treadystd_ulogic
Definition: Role.vhdl:131
Role_Themisto.siNRC_Role_Udp_Meta_TKEEP
in siNRC_Role_Udp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:81
Role_Themisto.siMEM_Mp0_Read_tkeep
in siMEM_Mp0_Read_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:128
Role_Themisto.soNRC_Tcp_Data_tdata
out soNRC_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:94
Role_Themisto.soROLE_Nrc_Tcp_Meta_TREADY
in soROLE_Nrc_Tcp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:104
Role_Themisto.siNRC_Role_Tcp_Meta_TLAST
in siNRC_Role_Tcp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:111
Role_Themisto.siMEM_Mp0_WrSts_tdata
in siMEM_Mp0_WrSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:137
Role_Themisto.soMEM_Mp0_Write_tkeep
out soMEM_Mp0_Write_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:142
Role_Themisto.siNRC_Tcp_Data_tready
out siNRC_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:92
Role_Themisto.siNRC_Role_Udp_Meta_TDATA
in siNRC_Role_Udp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:78
Role_Themisto.moMEM_Mp1_AWVALID
out moMEM_Mp1_AWVALIDstd_ulogic
Definition: Role.vhdl:155
Role_Themisto.siNRC_Role_Tcp_Meta_TVALID
in siNRC_Role_Tcp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:108
Role_Themisto.siNRC_Role_Tcp_Meta_TDATA
in siNRC_Role_Tcp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:107
Role_Themisto.moMEM_Mp1_BVALID
in moMEM_Mp1_BVALIDstd_ulogic
Definition: Role.vhdl:164
Role_Themisto.moMEM_Mp1_WSTRB
out moMEM_Mp1_WSTRBstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:158
Role_Themisto.moMEM_Mp1_BREADY
out moMEM_Mp1_BREADYstd_ulogic
Definition: Role.vhdl:165
Role_Themisto.moMEM_Mp1_AWID
out moMEM_Mp1_AWIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:150
Role_Themisto.moMEM_Mp1_RVALID
in moMEM_Mp1_RVALIDstd_ulogic
Definition: Role.vhdl:177
Role_Themisto.soNRC_Udp_Data_tready
in soNRC_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:69
Role_Themisto.soMEM_Mp0_WrCmd_tready
in soMEM_Mp0_WrCmd_treadystd_ulogic
Definition: Role.vhdl:135
Role_Themisto.siNRC_Udp_Data_tvalid
in siNRC_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:61
Role_Themisto.piMMIO_Ly7_En
in piMMIO_Ly7_Enstd_ulogic
Definition: Role.vhdl:53
Role_Themisto.soMEM_Mp0_Write_tready
in soMEM_Mp0_Write_treadystd_ulogic
Definition: Role.vhdl:145
Role_Themisto.soNRC_Udp_Data_tlast
out soNRC_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:68
Role_Themisto.soROLE_Nrc_Udp_Meta_TVALID
out soROLE_Nrc_Udp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:74
Role_Themisto.soROLE_Nrc_Tcp_Meta_TVALID
out soROLE_Nrc_Tcp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:103
Role_Themisto.moMEM_Mp1_WLAST
out moMEM_Mp1_WLASTstd_ulogic
Definition: Role.vhdl:159
Role_Themisto.soNRC_Udp_Data_tvalid
out soNRC_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:67
Role_Themisto.moMEM_Mp1_WDATA
out moMEM_Mp1_WDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:157
Role_Themisto.siNRC_Tcp_Data_tdata
in siNRC_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:88
Role_Themisto.soMEM_Mp0_RdCmd_tdata
out soMEM_Mp0_RdCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:119
Role_Themisto.siMEM_Mp0_Read_tdata
in siMEM_Mp0_Read_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:127
Role_Themisto.soMEM_Mp0_Write_tdata
out soMEM_Mp0_Write_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:141
Role_Themisto.siMEM_Mp0_RdSts_tready
out siMEM_Mp0_RdSts_treadystd_ulogic
Definition: Role.vhdl:125
Role_Themisto.moMEM_Mp1_ARBURST
out moMEM_Mp1_ARBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:170
Role_Themisto.siNRC_Role_Tcp_Meta_TKEEP
in siNRC_Role_Tcp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:110
Role_Themisto.siMEM_Mp0_RdSts_tdata
in siMEM_Mp0_RdSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:123
Role_Themisto.poROL_Nrc_Tcp_Rx_ports
out poROL_Nrc_Tcp_Rx_portsstd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:100
Role_Themisto.siNRC_Tcp_Data_tvalid
in siNRC_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:90
Role_Themisto.siNRC_Role_Udp_Meta_TLAST
in siNRC_Role_Udp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:82
Role_Themisto.moMEM_Mp1_ARREADY
in moMEM_Mp1_ARREADYstd_ulogic
Definition: Role.vhdl:172
Role_Themisto.siNRC_Udp_Data_tready
out siNRC_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:63
Role_Themisto.moMEM_Mp1_RRESP
in moMEM_Mp1_RRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:175
Role_Themisto.soMEM_Mp0_Write_tlast
out soMEM_Mp0_Write_tlaststd_ulogic
Definition: Role.vhdl:143
Role_Themisto.moMEM_Mp1_ARID
out moMEM_Mp1_ARIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:166
Role_Themisto.soMEM_Mp0_WrCmd_tvalid
out soMEM_Mp0_WrCmd_tvalidstd_ulogic
Definition: Role.vhdl:134
Role_Themisto.moMEM_Mp1_ARVALID
out moMEM_Mp1_ARVALIDstd_ulogic
Definition: Role.vhdl:171
Role_Themisto.soROLE_Nrc_Tcp_Meta_TDATA
out soROLE_Nrc_Tcp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:102
Role_Themisto.moMEM_Mp1_AWBURST
out moMEM_Mp1_AWBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:154
Role_Themisto.siNRC_Udp_Data_tkeep
in siNRC_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:60
Role_Themisto.soMEM_Mp0_RdCmd_tvalid
out soMEM_Mp0_RdCmd_tvalidstd_ulogic
Definition: Role.vhdl:120
Role_Themisto.soNRC_Tcp_Data_tkeep
out soNRC_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:95
Role_Themisto.siMEM_Mp0_Read_tvalid
in siMEM_Mp0_Read_tvalidstd_ulogic
Definition: Role.vhdl:130
Role_Themisto.moMEM_Mp1_RID
in moMEM_Mp1_RIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:173
Role_Themisto.soROLE_Nrc_Udp_Meta_TDATA
out soROLE_Nrc_Udp_Meta_TDATAstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:73
Role_Themisto.piFMC_ROLE_rank
in piFMC_ROLE_rankstd_logic_vector(31 downto 0)
Definition: Role.vhdl:192
Role_Themisto.soROLE_Nrc_Tcp_Meta_TKEEP
out soROLE_Nrc_Tcp_Meta_TKEEPstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:105
Role_Themisto.piTOP_250_00Clk
in piTOP_250_00Clkstd_ulogic
Definition: Role.vhdl:187
Role_Themisto.moMEM_Mp1_AWLEN
out moMEM_Mp1_AWLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:152
Role_Themisto.piFMC_ROLE_size
in piFMC_ROLE_sizestd_logic_vector(31 downto 0)
Definition: Role.vhdl:193
Role_Themisto.siNRC_Tcp_Data_tkeep
in siNRC_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:89
Role_Themisto.soMEM_Mp0_RdCmd_tready
in soMEM_Mp0_RdCmd_treadystd_ulogic
Definition: Role.vhdl:121
Role_Themisto.moMEM_Mp1_WREADY
in moMEM_Mp1_WREADYstd_ulogic
Definition: Role.vhdl:161
Role_Themisto.siNRC_Role_Udp_Meta_TREADY
out siNRC_Role_Udp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:80
Role_Themisto.soNRC_Tcp_Data_tlast
out soNRC_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:97
Role_Themisto.siMEM_Mp0_RdSts_tvalid
in siMEM_Mp0_RdSts_tvalidstd_ulogic
Definition: Role.vhdl:124
Role_Themisto.soROLE_Nrc_Udp_Meta_TLAST
out soROLE_Nrc_Udp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:77
Role_Themisto.moMEM_Mp1_AWSIZE
out moMEM_Mp1_AWSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:153
Role_Themisto.moMEM_Mp1_RDATA
in moMEM_Mp1_RDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:174
Role_Themisto.moMEM_Mp1_BID
in moMEM_Mp1_BIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:162
Role_Themisto.soMEM_Mp0_WrCmd_tdata
out soMEM_Mp0_WrCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:133
Role_Themisto.piMMIO_Ly7_Rst
in piMMIO_Ly7_Rststd_ulogic
Definition: Role.vhdl:52
Role_Themisto.poSHL_Mmio_RdReg
out poSHL_Mmio_RdRegstd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:182
Role_Themisto.siNRC_Role_Tcp_Meta_TREADY
out siNRC_Role_Tcp_Meta_TREADYstd_ulogic
Definition: Role.vhdl:109
Role_Themisto.siNRC_Role_Udp_Meta_TVALID
in siNRC_Role_Udp_Meta_TVALIDstd_ulogic
Definition: Role.vhdl:79
Role_Themisto.moMEM_Mp1_BRESP
in moMEM_Mp1_BRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:163
Role_Themisto.moMEM_Mp1_WVALID
out moMEM_Mp1_WVALIDstd_ulogic
Definition: Role.vhdl:160
Role_Themisto.siNRC_Udp_Data_tdata
in siNRC_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:59
Role_Themisto.moMEM_Mp1_ARLEN
out moMEM_Mp1_ARLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:168
Role_Themisto.soROLE_Nrc_Tcp_Meta_TLAST
out soROLE_Nrc_Tcp_Meta_TLASTstd_ulogic
Definition: Role.vhdl:106
Role_Themisto.soNRC_Udp_Data_tkeep
out soNRC_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:66
Role_Themisto.siNRC_Tcp_Data_tlast
in siNRC_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:91
Role_Themisto.siMEM_Mp0_WrSts_tready
out siMEM_Mp0_WrSts_treadystd_ulogic
Definition: Role.vhdl:139
Role_Themisto.siMEM_Mp0_WrSts_tvalid
in siMEM_Mp0_WrSts_tvalidstd_ulogic
Definition: Role.vhdl:138
Role_Themisto.soMEM_Mp0_Write_tvalid
out soMEM_Mp0_Write_tvalidstd_ulogic
Definition: Role.vhdl:144
Role_Themisto.moMEM_Mp1_ARADDR
out moMEM_Mp1_ARADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:167
Role_Themisto.poVoid
out poVoidstd_ulogic
Definition: Role.vhdl:213
Role_Themisto.moMEM_Mp1_AWREADY
in moMEM_Mp1_AWREADYstd_ulogic
Definition: Role.vhdl:156
Role_Themisto.poROL_Nrc_Udp_Rx_ports
out poROL_Nrc_Udp_Rx_portsstd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:71
Role_Themisto.siMEM_Mp0_Read_tlast
in siMEM_Mp0_Read_tlaststd_ulogic
Definition: Role.vhdl:129
Role_Themisto.soNRC_Tcp_Data_tvalid
out soNRC_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:96
topFMKU60.poDDR4_Mem_Mc0_Reset_n
out poDDR4_Mem_Mc0_Reset_nstd_ulogic
Definition: top.vhdl:149
topFMKU60.pioPSOC_Emif_Data
inout pioPSOC_Emif_Datastd_ulogic_vector( gEmifDataWidth- 1 downto 0)
Definition: top.vhdl:126
topFMKU60.poDDR4_Mem_Mc0_Odt
out poDDR4_Mem_Mc0_Odtstd_ulogic
Definition: top.vhdl:145
topFMKU60.poDDR4_Mem_Mc0_Act_n
out poDDR4_Mem_Mc0_Act_nstd_ulogic
Definition: top.vhdl:140
topFMKU60.piPSOC_Emif_Addr
in piPSOC_Emif_Addrstd_ulogic_vector( gEmifAddrWidth- 1 downto 0)
Definition: top.vhdl:125
topFMKU60.piPSOC_Emif_Clk
in piPSOC_Emif_Clkstd_ulogic
Definition: top.vhdl:120
topFMKU60.pioDDR4_Mem_Mc0_Dqs_n
inout pioDDR4_Mem_Mc0_Dqs_nstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:139
topFMKU60.piPSOC_Emif_Cs_n
in piPSOC_Emif_Cs_nstd_ulogic
Definition: top.vhdl:121
topFMKU60.gBitstreamUsage
gBitstreamUsagestring := "flash"
Definition: top.vhdl:78
topFMKU60.poDDR4_Mem_Mc1_Ck_n
out poDDR4_Mem_Mc1_Ck_nstd_ulogic
Definition: top.vhdl:166
topFMKU60.pioDDR4_Mem_Mc0_DmDbi_n
inout pioDDR4_Mem_Mc0_DmDbi_nstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:136
topFMKU60.gEmifDataWidth
gEmifDataWidthinteger :=8
Definition: top.vhdl:87
topFMKU60.piCLKT_Usr1Clk_n
in piCLKT_Usr1Clk_nstd_ulogic
Definition: top.vhdl:114
topFMKU60.poDDR4_Mem_Mc0_Ck_n
out poDDR4_Mem_Mc0_Ck_nstd_ulogic
Definition: top.vhdl:148
topFMKU60.piCLKT_10GeClk_p
in piCLKT_10GeClk_pstd_ulogic
Definition: top.vhdl:107
topFMKU60.poDDR4_Mem_Mc0_Ck_p
out poDDR4_Mem_Mc0_Ck_pstd_ulogic
Definition: top.vhdl:147
topFMKU60.piPSOC_Emif_AdS_n
in piPSOC_Emif_AdS_nstd_ulogic
Definition: top.vhdl:124
topFMKU60.piPSOC_Emif_We_n
in piPSOC_Emif_We_nstd_ulogic
Definition: top.vhdl:122
topFMKU60.poDDR4_Mem_Mc0_Adr
out poDDR4_Mem_Mc0_Adrstd_ulogic_vector(16 downto 0)
Definition: top.vhdl:141
topFMKU60.poLED_HeartBeat_n
out poLED_HeartBeat_nstd_ulogic
Definition: top.vhdl:131
topFMKU60.piPSOC_Emif_Oe_n
in piPSOC_Emif_Oe_nstd_ulogic
Definition: top.vhdl:123
topFMKU60.gTopDateMonth
gTopDateMonthstDate :=8d"00"
Definition: top.vhdl:82
topFMKU60.pioDDR4_Mem_Mc1_Dqs_n
inout pioDDR4_Mem_Mc1_Dqs_nstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:157
topFMKU60.piCLKT_Mem0Clk_n
in piCLKT_Mem0Clk_nstd_ulogic
Definition: top.vhdl:98
topFMKU60.pioDDR4_Mem_Mc1_Dq
inout pioDDR4_Mem_Mc1_Dqstd_ulogic_vector(71 downto 0)
Definition: top.vhdl:155
topFMKU60.pioDDR4_Mem_Mc1_DmDbi_n
inout pioDDR4_Mem_Mc1_DmDbi_nstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:154
topFMKU60.piCLKT_Usr0Clk_n
in piCLKT_Usr0Clk_nstd_ulogic
Definition: top.vhdl:112
topFMKU60.pioDDR4_Mem_Mc0_Dq
inout pioDDR4_Mem_Mc0_Dqstd_ulogic_vector(71 downto 0)
Definition: top.vhdl:137
topFMKU60.poDDR4_Mem_Mc1_Cke
out poDDR4_Mem_Mc1_Ckestd_ulogic
Definition: top.vhdl:162
topFMKU60.piCLKT_Mem1Clk_p
in piCLKT_Mem1Clk_pstd_ulogic
Definition: top.vhdl:101
topFMKU60.pioDDR4_Mem_Mc0_Dqs_p
inout pioDDR4_Mem_Mc0_Dqs_pstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:138
topFMKU60.poDDR4_Mem_Mc1_Adr
out poDDR4_Mem_Mc1_Adrstd_ulogic_vector(16 downto 0)
Definition: top.vhdl:159
topFMKU60.gTopDateDay
gTopDateDaystDate :=8d"00"
Definition: top.vhdl:83
topFMKU60.gSecurityPriviledges
gSecurityPriviledgesstring := "super"
Definition: top.vhdl:79
topFMKU60.poDDR4_Mem_Mc1_Ck_p
out poDDR4_Mem_Mc1_Ck_pstd_ulogic
Definition: top.vhdl:165
topFMKU60.gEmifAddrWidth
gEmifAddrWidthinteger :=8
Definition: top.vhdl:85
topFMKU60.piCLKT_Usr1Clk_p
in piCLKT_Usr1Clk_pstd_ulogic
Definition: top.vhdl:115
topFMKU60.poDDR4_Mem_Mc1_Cs_n
out poDDR4_Mem_Mc1_Cs_nstd_ulogic
Definition: top.vhdl:164
topFMKU60.poDDR4_Mem_Mc0_Bg
out poDDR4_Mem_Mc0_Bgstd_ulogic_vector(1 downto 0)
Definition: top.vhdl:143
topFMKU60.piECON_Eth_10Ge0_p
in piECON_Eth_10Ge0_pstd_ulogic
Definition: top.vhdl:173
topFMKU60.poDDR4_Mem_Mc0_Cs_n
out poDDR4_Mem_Mc0_Cs_nstd_ulogic
Definition: top.vhdl:146
topFMKU60.piCLKT_Usr0Clk_p
in piCLKT_Usr0Clk_pstd_ulogic
Definition: top.vhdl:113
topFMKU60.poECON_Eth_10Ge0_n
out poECON_Eth_10Ge0_nstd_ulogic
Definition: top.vhdl:174
topFMKU60.piECON_Eth_10Ge0_n
in piECON_Eth_10Ge0_nstd_ulogic
Definition: top.vhdl:172
topFMKU60.piPSOC_Fcfg_Rst_n
in piPSOC_Fcfg_Rst_nstd_ulogic
Definition: top.vhdl:93
topFMKU60.gTopDateYear
gTopDateYearstDate :=8d"00"
Definition: top.vhdl:81
topFMKU60.piCLKT_Mem0Clk_p
in piCLKT_Mem0Clk_pstd_ulogic
Definition: top.vhdl:99
topFMKU60.poECON_Eth_10Ge0_p
out poECON_Eth_10Ge0_pstd_ulogic
Definition: top.vhdl:177
topFMKU60.poDDR4_Mem_Mc1_Act_n
out poDDR4_Mem_Mc1_Act_nstd_ulogic
Definition: top.vhdl:158
topFMKU60.pioDDR4_Mem_Mc1_Dqs_p
inout pioDDR4_Mem_Mc1_Dqs_pstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:156
topFMKU60.poDDR4_Mem_Mc0_Ba
out poDDR4_Mem_Mc0_Bastd_ulogic_vector(1 downto 0)
Definition: top.vhdl:142
topFMKU60.poDDR4_Mem_Mc1_Ba
out poDDR4_Mem_Mc1_Bastd_ulogic_vector(1 downto 0)
Definition: top.vhdl:160
topFMKU60.poDDR4_Mem_Mc1_Bg
out poDDR4_Mem_Mc1_Bgstd_ulogic_vector(1 downto 0)
Definition: top.vhdl:161
topFMKU60.poDDR4_Mem_Mc1_Odt
out poDDR4_Mem_Mc1_Odtstd_ulogic
Definition: top.vhdl:163
topFMKU60.poDDR4_Mem_Mc1_Reset_n
out poDDR4_Mem_Mc1_Reset_nstd_ulogic
Definition: top.vhdl:167
topFMKU60.piCLKT_10GeClk_n
in piCLKT_10GeClk_nstd_ulogic
Definition: top.vhdl:106
topFMKU60.poDDR4_Mem_Mc0_Cke
out poDDR4_Mem_Mc0_Ckestd_ulogic
Definition: top.vhdl:144
topFMKU60.piCLKT_Mem1Clk_n
in piCLKT_Mem1Clk_nstd_ulogic
Definition: top.vhdl:100