cloudFPGA (cF) API  1.0
The documentation of the source code of cloudFPGA (cF)
top.vhdl
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1 -- /*******************************************************************************
2 -- * Copyright 2016 -- 2021 IBM Corporation
3 -- *
4 -- * Licensed under the Apache License, Version 2.0 (the "License");
5 -- * you may not use this file except in compliance with the License.
6 -- * You may obtain a copy of the License at
7 -- *
8 -- * http://www.apache.org/licenses/LICENSE-2.0
9 -- *
10 -- * Unless required by applicable law or agreed to in writing, software
11 -- * distributed under the License is distributed on an "AS IS" BASIS,
12 -- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 -- * See the License for the specific language governing permissions and
14 -- * limitations under the License.
15 -- *******************************************************************************/
16 
17 
18 -- *****************************************************************************
19 -- *
20 -- * cloudFPGA
21 -- *
22 -- *----------------------------------------------------------------------------
23 -- *
24 -- * Title : Top level design for the BRING-UP TEST of the FMKU60 module.
25 -- *
26 -- * File : top.vhdl
27 -- *
28 -- * Created : Feb. 2018
29 -- * Authors : Francois Abel <fab@zurich.ibm.com>
30 -- *
31 -- * Devices : xcku060-ffva1156-2-i
32 -- * Tools : Vivado v2016.4 / 2017.4 (64-bit)
33 -- *
34 -- * Dependencies : cloudFPGA Shell IP v1.0.
35 -- *
36 -- * Description : This top level implements a design to test and bring-up
37 -- * the FMKU60 module. The design builds on the Shell-Role Architecture
38 -- * by specifying the content of the Role as if it was a specific user
39 -- * application.
40 -- * This design instantiates a limited version of the cloudFPGA Shell
41 -- * as an IP core which consists of a hardware TCP/IP network stack on top
42 -- * of the 10Gb Ethernet interface #0 (ETH0) and a synchronous dynamic
43 -- * random access memory (SRDM) interface with two DDR4 memory channels
44 -- * (i.e. 2x8GB).
45 -- *
46 -- * The Role is a container that consists of a set of diagnostic tests and
47 -- * initialization procedures for the FMKU60.
48 -- *
49 -- * Clocking:
50 -- * The SHELL and the ROLE operate with the source synchronous clock called
51 -- * 'sSHL_156_25Clk'. This clock is generated by the 10Gb PCS/PMA subsystem
52 -- * and also listed as follows after synthesis:
53 -- * SHELL/../xpcs/U0/ten_gig_eth_pcs_pma_shared_clock_reset_block/CLK
54 -- *****************************************************************************
55 
56 
57 --******************************************************************************
58 --** CONTEXT CLAUSE ** FMKU60 FLASH
59 --******************************************************************************
60 library IEEE;
61 use IEEE.std_logic_1164.all;
62 use IEEE.numeric_std.all;
63 
64 library UNISIM;
65 use UNISIM.vcomponents.all;
66 
67 --library WORK;
68 --use WORK.topFlash_pkg.all; -- Not used
69 
70 library XIL_DEFAULTLIB;
71 use XIL_DEFAULTLIB.topFMKU_pkg.all;
72 
73 
74 --******************************************************************************
75 --** ENTITY ** FMKU60 FLASH
76 --******************************************************************************
77 
78 entity topFMKU60 is
79  generic (
80  -- Synthesis parameters ----------------------
81  gBitstreamUsage : string := "flash"; -- "user" or "flash"
82  gSecurityPriviledges : string := "super"; -- "user" or "super"
83  gVivadoVersion : integer := 2019; -- E.g., 2019
84  -- Build date --------------------------------
85  gTopDateYear : stDate := 8d"00"; -- Not used w/ Xilinx parts (see USR_ACCESSE2)
86  gTopDateMonth : stDate := 8d"00"; -- Not used w/ Xilinx parts (see USR_ACCESSE2)
87  gTopDateDay : stDate := 8d"00"; -- Not used w/ Xilinx parts (see USR_ACCESSE2)
88  -- External Memory Interface (EMIF) ----------
89  gEmifAddrWidth : integer := 8;
90  gEmifDataWidth : integer := 8
91  );
92  port (
93  ------------------------------------------------------
94  -- PSOC / FPGA Configuration Interface (Fcfg)
95  -- System reset controlled by the PSoC.
96  ------------------------------------------------------
97  piPSOC_Fcfg_Rst_n : in std_ulogic;
98 
99  ------------------------------------------------------
100  -- CLKT / DRAM clocks 0 and 1 (Mem. Channels 0 and 1)
101  ------------------------------------------------------
102  piCLKT_Mem0Clk_n : in std_ulogic;
103  piCLKT_Mem0Clk_p : in std_ulogic;
104  piCLKT_Mem1Clk_n : in std_ulogic;
105  piCLKT_Mem1Clk_p : in std_ulogic;
106 
107  ------------------------------------------------------
108  -- CLKT / GTH clocks (10Ge, Sata, Gtio Interfaces)
109  ------------------------------------------------------
110  piCLKT_10GeClk_n : in std_ulogic;
111  piCLKT_10GeClk_p : in std_ulogic;
112 
113  ------------------------------------------------------
114  -- CLKT / User clocks 0 and 1 (156.25MHz, 250MHz)
115  ------------------------------------------------------
116  piCLKT_Usr0Clk_n : in std_ulogic;
117  piCLKT_Usr0Clk_p : in std_ulogic;
118  piCLKT_Usr1Clk_n : in std_ulogic;
119  piCLKT_Usr1Clk_p : in std_ulogic;
120 
121  ------------------------------------------------------
122  -- PSOC / External Memory Interface (Emif)
123  ------------------------------------------------------
124  piPSOC_Emif_Clk : in std_ulogic;
125  piPSOC_Emif_Cs_n : in std_ulogic;
126  piPSOC_Emif_We_n : in std_ulogic;
127  piPSOC_Emif_Oe_n : in std_ulogic;
128  piPSOC_Emif_AdS_n : in std_ulogic;
129  piPSOC_Emif_Addr : in std_ulogic_vector(gEmifAddrWidth-1 downto 0);
130  pioPSOC_Emif_Data : inout std_ulogic_vector(gEmifDataWidth-1 downto 0);
131 
132  ------------------------------------------------------
133  -- LED / Heart Beat Interface (Yellow LED)
134  ------------------------------------------------------
135  poLED_HeartBeat_n : out std_ulogic;
136 
137  ------------------------------------------------------
138  -- -- DDR(4) / Memory Channel 0 Interface (Mc0)
139  ------------------------------------------------------
140  pioDDR4_Mem_Mc0_DmDbi_n : inout std_ulogic_vector( 8 downto 0);
141  pioDDR4_Mem_Mc0_Dq : inout std_ulogic_vector(71 downto 0);
142  pioDDR4_Mem_Mc0_Dqs_p : inout std_ulogic_vector( 8 downto 0);
143  pioDDR4_Mem_Mc0_Dqs_n : inout std_ulogic_vector( 8 downto 0);
144  poDDR4_Mem_Mc0_Act_n : out std_ulogic;
145  poDDR4_Mem_Mc0_Adr : out std_ulogic_vector(16 downto 0);
146  poDDR4_Mem_Mc0_Ba : out std_ulogic_vector( 1 downto 0);
147  poDDR4_Mem_Mc0_Bg : out std_ulogic_vector( 1 downto 0);
148  poDDR4_Mem_Mc0_Cke : out std_ulogic;
149  poDDR4_Mem_Mc0_Odt : out std_ulogic;
150  poDDR4_Mem_Mc0_Cs_n : out std_ulogic;
151  poDDR4_Mem_Mc0_Ck_p : out std_ulogic;
152  poDDR4_Mem_Mc0_Ck_n : out std_ulogic;
153  poDDR4_Mem_Mc0_Reset_n : out std_ulogic;
154 
155  ------------------------------------------------------
156  -- DDR(4) / Memory Channel 1 Interface (Mc1)
157  ------------------------------------------------------
158  pioDDR4_Mem_Mc1_DmDbi_n : inout std_ulogic_vector( 8 downto 0);
159  pioDDR4_Mem_Mc1_Dq : inout std_ulogic_vector(71 downto 0);
160  pioDDR4_Mem_Mc1_Dqs_p : inout std_ulogic_vector( 8 downto 0);
161  pioDDR4_Mem_Mc1_Dqs_n : inout std_ulogic_vector( 8 downto 0);
162  poDDR4_Mem_Mc1_Act_n : out std_ulogic;
163  poDDR4_Mem_Mc1_Adr : out std_ulogic_vector(16 downto 0);
164  poDDR4_Mem_Mc1_Ba : out std_ulogic_vector( 1 downto 0);
165  poDDR4_Mem_Mc1_Bg : out std_ulogic_vector( 1 downto 0);
166  poDDR4_Mem_Mc1_Cke : out std_ulogic;
167  poDDR4_Mem_Mc1_Odt : out std_ulogic;
168  poDDR4_Mem_Mc1_Cs_n : out std_ulogic;
169  poDDR4_Mem_Mc1_Ck_p : out std_ulogic;
170  poDDR4_Mem_Mc1_Ck_n : out std_ulogic;
171  poDDR4_Mem_Mc1_Reset_n : out std_ulogic;
172 
173  ------------------------------------------------------
174  -- ECON / Edge Connector Interface (SPD08-200)
175  ------------------------------------------------------
176  piECON_Eth_10Ge0_n : in std_ulogic;
177  piECON_Eth_10Ge0_p : in std_ulogic;
178  poECON_Eth_10Ge0_n : out std_ulogic;
179  poECON_Eth_10Ge0_p : out std_ulogic
180 
181  );
182 
183 end topFMKU60;
184 
185 
186 --*****************************************************************************
187 --** ARCHITECTURE ** FMKU60 FLASH
188 --*****************************************************************************
189 architecture structural of topFMKU60 is
190 
191  --------------------------------------------------------n
192  -- [TOP] SIGNAL DECLARATIONS
193  --------------------------------------------------------
194 
195  -- Global User Clocks ----------------------------------
196  signal sTOP_156_25Clk : std_ulogic;
197  signal sTOP_250_00Clk : std_ulogic;
198 
199  -- Global Reset ----------------------------------------
200  signal sTOP_156_25Rst_n : std_ulogic;
201  signal sTOP_156_25Rst : std_ulogic;
202 
203  -- Global Source Synchronous Clock and Reset -----------
204  signal sSHL_156_25Clk : std_ulogic;
205  signal sSHL_156_25Rst : std_ulogic;
206 
207  -- Bitstream Identification Value ----------------------
208  signal sTOP_Timestamp : stTimeStamp;
209 
210  --------------------------------------------------------
211  -- SIGNAL DECLARATIONS : [SHELL/Nts] <--> [ROLE/Nts]
212  --------------------------------------------------------
213 
214  -- ROLE-->SHELL / Nts / Udp / Tx Data Interfaces
215  ---- Axi4-Stream UDP Data ---------------
216  signal ssROL_SHL_Nts_Udp_Data_tdata : std_ulogic_vector( 63 downto 0);
217  signal ssROL_SHL_Nts_Udp_Data_tkeep : std_ulogic_vector( 7 downto 0);
218  signal ssROL_SHL_Nts_Udp_Data_tlast : std_ulogic;
219  signal ssROL_SHL_Nts_Udp_Data_tvalid : std_ulogic;
220  signal ssROL_SHL_Nts_Udp_Data_tready : std_ulogic;
221  ---- Axi4-Stream UDP Metadata -----------
222  signal ssROL_SHL_Nts_Udp_Meta_tdata : std_ulogic_vector( 95 downto 0);
223  signal ssROL_SHL_Nts_Udp_Meta_tvalid : std_ulogic;
224  signal ssROL_SHL_Nts_Udp_Meta_tready : std_ulogic;
225  ---- Axis4Stream UDP Data Length ---------
226  signal ssROL_SHL_Nts_Udp_DLen_tdata : std_ulogic_vector( 15 downto 0);
227  signal ssROL_SHL_Nts_Udp_DLen_tvalid : std_ulogic;
228  signal ssROL_SHL_Nts_Udp_DLen_tready : std_ulogic;
229 
230  -- SHELL-->ROLE / Nts / Udp / Rx Data Interfaces
231  ---- UDP Data (AXI4S) --------------------
232  signal ssSHL_ROL_Nts_Udp_Data_tdata : std_ulogic_vector( 63 downto 0);
233  signal ssSHL_ROL_Nts_Udp_Data_tkeep : std_ulogic_vector( 7 downto 0);
234  signal ssSHL_ROL_Nts_Udp_Data_tlast : std_ulogic;
235  signal ssSHL_ROL_Nts_Udp_Data_tvalid : std_ulogic;
236  signal ssSHL_ROL_Nts_Udp_Data_tready : std_ulogic;
237  ---- Axi4-Stream UDP Metadata -----------
238  signal ssSHL_ROL_Nts_Udp_Meta_tdata : std_ulogic_vector( 95 downto 0);
239  signal ssSHL_ROL_Nts_Udp_Meta_tvalid : std_ulogic;
240  signal ssSHL_ROL_Nts_Udp_Meta_tready : std_ulogic;
241  ---- Axi4-Stream UDP Data Len -----------
242  signal ssSHL_ROL_Nts_Udp_DLen_tdata : std_ulogic_vector( 15 downto 0);
243  signal ssSHL_ROL_Nts_Udp_DLen_tvalid : std_ulogic;
244  signal ssSHL_ROL_Nts_Udp_DLen_tready : std_ulogic;
245 
246  -- SHELL-->ROLE / Nts/ Udp / Rx Ctrl Interfaces
247  ---- Axi4-Stream UDP Listen Request -----
248  signal ssROL_SHL_Nts_Udp_LsnReq_tdata : std_ulogic_vector( 15 downto 0);
249  signal ssROL_SHL_Nts_Udp_LsnReq_tvalid : std_ulogic;
250  signal ssROL_SHL_Nts_Udp_LsnReq_tready : std_ulogic;
251  ---- Axi4-Stream UDP Listen Reply --------
252  signal ssSHL_ROL_Nts_Udp_LsnRep_tdata : std_ulogic_vector( 7 downto 0);
253  signal ssSHL_ROL_Nts_Udp_LsnRep_tvalid : std_ulogic;
254  signal ssSHL_ROL_Nts_Udp_LsnRep_tready : std_ulogic;
255  ---- Axi4-Stream UDP Close Request ------
256  signal ssROL_SHL_Nts_Udp_ClsReq_tdata : std_ulogic_vector( 15 downto 0);
257  signal ssROL_SHL_Nts_Udp_ClsReq_tvalid : std_ulogic;
258  signal ssROL_SHL_Nts_Udp_ClsReq_tready : std_ulogic;
259  ---- Axi4-Stream UDP Close Reply ---------
260  signal ssSHL_ROL_Nts_Udp_ClsRep_tdata : std_ulogic_vector( 7 downto 0);
261  signal ssSHL_ROL_Nts_Udp_ClsRep_tvalid : std_ulogic;
262  signal ssSHL_ROL_Nts_Udp_ClsRep_tready : std_ulogic;
263 
264  -- ROLE-->SHELL / Nts / Tcp / Tx Data Interfaces
265  ---- Axi4-Stream TCP Data ----------------
266  signal ssROL_SHL_Nts_Tcp_Data_tdata : std_ulogic_vector( 63 downto 0);
267  signal ssROL_SHL_Nts_Tcp_Data_tkeep : std_ulogic_vector( 7 downto 0);
268  signal ssROL_SHL_Nts_Tcp_Data_tlast : std_ulogic;
269  signal ssROL_SHL_Nts_Tcp_Data_tvalid : std_ulogic;
270  signal ssROL_SHL_Nts_Tcp_Data_tready : std_ulogic;
271  ---- Axi4-Stream TCP Send Request --------
272  signal ssROL_SHL_Nts_Tcp_SndReq_tdata : std_ulogic_vector( 31 downto 0);
273  signal ssROL_SHL_Nts_Tcp_SndReq_tvalid : std_ulogic;
274  signal ssROL_SHL_Nts_Tcp_SndReq_tready : std_ulogic;
275  ---- Axi4-Stream TCP Send Reply ----------
276  signal ssSHL_ROL_Nts_Tcp_SndRep_tdata : std_ulogic_vector( 55 downto 0);
277  signal ssSHL_ROL_Nts_Tcp_SndRep_tvalid : std_ulogic;
278  signal ssSHL_ROL_Nts_Tcp_SndRep_tready : std_ulogic;
279 
280  -- SHELL-->ROLE / Nts / Tcp / Rx Data Interfaces
281  ---- Axi4-Stream TCP Data -----------------
282  signal ssSHL_ROL_Nts_Tcp_Data_tdata : std_ulogic_vector( 63 downto 0);
283  signal ssSHL_ROL_Nts_Tcp_Data_tkeep : std_ulogic_vector( 7 downto 0);
284  signal ssSHL_ROL_Nts_Tcp_Data_tlast : std_ulogic;
285  signal ssSHL_ROL_Nts_Tcp_Data_tvalid : std_ulogic;
286  signal ssSHL_ROL_Nts_Tcp_Data_tready : std_ulogic;
287  ---- Axi4-Stream TCP Metadata ------------
288  signal ssSHL_ROL_Nts_Tcp_Meta_tdata : std_ulogic_vector( 15 downto 0);
289  signal ssSHL_ROL_Nts_Tcp_Meta_tvalid : std_ulogic;
290  signal ssSHL_ROL_Nts_Tcp_Meta_tready : std_ulogic;
291  ---- Axi4-Stream TCP Data Notification ---
292  signal ssSHL_ROL_Nts_Tcp_Notif_tdata : std_ulogic_vector(7+96 downto 0); -- 8-bits boundary
293  signal ssSHL_ROL_Nts_Tcp_Notif_tvalid : std_ulogic;
294  signal ssSHL_ROL_Nts_Tcp_Notif_tready : std_ulogic;
295  ---- Axi4-Stream TCP Data Request --------
296  signal ssROL_SHL_Nts_Tcp_DReq_tdata : std_ulogic_vector( 31 downto 0);
297  signal ssROL_SHL_Nts_Tcp_DReq_tvalid : std_ulogic;
298  signal ssROL_SHL_Nts_Tcp_DReq_tready : std_ulogic;
299 
300  -- ROLE-->SHELL / Nts / Tcp / TxP Ctlr Interfaces
301  ---- Axi4-Stream TCP Open Session Request
302  signal ssROL_SHL_Nts_Tcp_OpnReq_tdata : std_ulogic_vector( 47 downto 0);
303  signal ssROL_SHL_Nts_Tcp_OpnReq_tvalid : std_ulogic;
304  signal ssROL_SHL_Nts_Tcp_OpnReq_tready : std_ulogic;
305  ---- Axi4-Stream TCP Open Session Reply
306  signal ssSHL_ROL_Nts_Tcp_OpnRep_tdata : std_ulogic_vector( 23 downto 0);
307  signal ssSHL_ROL_Nts_Tcp_OpnRep_tvalid : std_ulogic;
308  signal ssSHL_ROL_Nts_Tcp_OpnRep_tready : std_ulogic;
309  ---- Axi4-Stream TCP Close Request ------
310  signal ssROL_SHL_Nts_Tcp_ClsReq_tdata : std_ulogic_vector( 15 downto 0);
311  signal ssROL_SHL_Nts_Tcp_ClsReq_tvalid : std_ulogic;
312  signal ssROL_SHL_Nts_Tcp_ClsReq_tready : std_ulogic;
313 
314  -- SHELL-->ROLE / Nts / Tcp / Rx Ctlr Interfaces
315  ---- Axi4-Stream TCP Listen Request ----
316  signal ssROL_SHL_Nts_Tcp_LsnReq_tdata : std_ulogic_vector( 15 downto 0);
317  signal ssROL_SHL_Nts_Tcp_LsnReq_tvalid : std_ulogic;
318  signal ssROL_SHL_Nts_Tcp_LsnReq_tready : std_ulogic;
319  ---- Axi4-Stream TCP Listen Rep --------
320  signal ssSHL_ROL_Nts_Tcp_LsnRep_tdata : std_ulogic_vector( 7 downto 0);
321  signal ssSHL_ROL_Nts_Tcp_LsnRep_tvalid : std_ulogic;
322  signal ssSHL_ROL_Nts_Tcp_LsnRep_tready : std_ulogic;
323 
324  --------------------------------------------------------
325  -- SIGNAL DECLARATIONS : [SHELL/Mem] <--> [ROLE/Mem]
326  --------------------------------------------------------
327  -- Memory Port #0 ------------------------------
328  ------ Stream Read Command --------------
329  signal ssROL_SHL_Mem_Mp0_RdCmd_tdata : std_ulogic_vector( 79 downto 0);
330  signal ssROL_SHL_Mem_Mp0_RdCmd_tvalid : std_ulogic;
331  signal ssROL_SHL_Mem_Mp0_RdCmd_tready : std_ulogic;
332  ------ Stream Read Status ----------------
333  signal ssSHL_ROL_Mem_Mp0_RdSts_tdata : std_ulogic_vector( 7 downto 0);
334  signal ssSHL_ROL_Mem_Mp0_RdSts_tvalid : std_ulogic;
335  signal ssSHL_ROL_Mem_Mp0_RdSts_tready : std_ulogic;
336  ------ Stream Data Output Channel --------
337  signal ssSHL_ROL_Mem_Mp0_Read_tdata : std_ulogic_vector(511 downto 0);
338  signal ssSHL_ROL_Mem_Mp0_Read_tkeep : std_ulogic_vector( 63 downto 0);
339  signal ssSHL_ROL_Mem_Mp0_Read_tlast : std_ulogic;
340  signal ssSHL_ROL_Mem_Mp0_Read_tvalid : std_ulogic;
341  signal ssSHL_ROL_Mem_Mp0_Read_tready : std_ulogic;
342  ------ Stream Write Command --------------
343  signal ssROL_SHL_Mem_Mp0_WrCmd_tdata : std_ulogic_vector( 79 downto 0);
344  signal ssROL_SHL_Mem_Mp0_WrCmd_tvalid : std_ulogic;
345  signal ssROL_SHL_Mem_Mp0_WrCmd_tready : std_ulogic;
346  ------ Stream Write Status ---------------
347  signal ssSHL_ROL_Mem_Mp0_WrSts_tdata : std_ulogic_vector( 7 downto 0);
348  signal ssSHL_ROL_Mem_Mp0_WrSts_tvalid : std_ulogic;
349  signal ssSHL_ROL_Mem_Mp0_WrSts_tready : std_ulogic;
350  ------ Stream Data Input Channel ---------
351  signal ssROL_SHL_Mem_Mp0_Write_tdata : std_ulogic_vector(511 downto 0);
352  signal ssROL_SHL_Mem_Mp0_Write_tkeep : std_ulogic_vector( 63 downto 0);
353  signal ssROL_SHL_Mem_Mp0_Write_tlast : std_ulogic;
354  signal ssROL_SHL_Mem_Mp0_Write_tvalid : std_ulogic;
355  signal ssROL_SHL_Mem_Mp0_Write_tready : std_ulogic;
356  -- Memory Port #1 ------------------------------
357  signal smROL_SHL_Mem_Mp1_AWID : std_ulogic_vector( 7 downto 0);
358  signal smROL_SHL_Mem_Mp1_AWADDR : std_ulogic_vector( 32 downto 0);
359  signal smROL_SHL_Mem_Mp1_AWLEN : std_ulogic_vector( 7 downto 0);
360  signal smROL_SHL_Mem_Mp1_AWSIZE : std_ulogic_vector( 2 downto 0);
361  signal smROL_SHL_Mem_Mp1_AWBURST : std_ulogic_vector( 1 downto 0);
362  signal smROL_SHL_Mem_Mp1_AWVALID : std_ulogic;
363  signal smROL_SHL_Mem_Mp1_AWREADY : std_ulogic;
364  signal smROL_SHL_Mem_Mp1_WDATA : std_ulogic_vector(511 downto 0);
365  signal smROL_SHL_Mem_Mp1_WSTRB : std_ulogic_vector( 63 downto 0);
366  signal smROL_SHL_Mem_Mp1_WLAST : std_ulogic;
367  signal smROL_SHL_Mem_Mp1_WVALID : std_ulogic;
368  signal smROL_SHL_Mem_Mp1_WREADY : std_ulogic;
369  signal smROL_SHL_Mem_Mp1_BID : std_ulogic_vector( 7 downto 0);
370  signal smROL_SHL_Mem_Mp1_BRESP : std_ulogic_vector( 1 downto 0);
371  signal smROL_SHL_Mem_Mp1_BVALID : std_ulogic;
372  signal smROL_SHL_Mem_Mp1_BREADY : std_ulogic;
373  signal smROL_SHL_Mem_Mp1_ARID : std_ulogic_vector( 7 downto 0);
374  signal smROL_SHL_Mem_Mp1_ARADDR : std_ulogic_vector( 32 downto 0);
375  signal smROL_SHL_Mem_Mp1_ARLEN : std_ulogic_vector( 7 downto 0);
376  signal smROL_SHL_Mem_Mp1_ARSIZE : std_ulogic_vector( 2 downto 0);
377  signal smROL_SHL_Mem_Mp1_ARBURST : std_ulogic_vector( 1 downto 0);
378  signal smROL_SHL_Mem_Mp1_ARVALID : std_ulogic;
379  signal smROL_SHL_Mem_Mp1_ARREADY : std_ulogic;
380  signal smROL_SHL_Mem_Mp1_RID : std_ulogic_vector( 7 downto 0);
381  signal smROL_SHL_Mem_Mp1_RDATA : std_ulogic_vector(511 downto 0);
382  signal smROL_SHL_Mem_Mp1_RRESP : std_ulogic_vector( 1 downto 0);
383  signal smROL_SHL_Mem_Mp1_RLAST : std_ulogic;
384  signal smROL_SHL_Mem_Mp1_RVALID : std_ulogic;
385  signal smROL_SHL_Mem_Mp1_RREADY : std_ulogic;
386 
387  --------------------------------------------------------
388  -- SIGNAL DECLARATIONS : [MMIO] <--> [ROLE]
389  --------------------------------------------------------
390  ---- [PHY_RESET] -------------------------
391  signal sSHL_ROL_Mmio_Ly7Rst : std_ulogic;
392  ---- [PHY_ENABLE] ------------------------
393  signal sSHL_ROL_Mmio_Ly7En : std_ulogic;
394  ---- DIAG_CTRL_1 -------------------------
395  signal sSHL_ROL_Mmio_Mc1_MemTestCtrl : std_ulogic_vector( 1 downto 0);
396  ---- DIAG_STAT_1 -------------------------
397  signal sROL_SHL_Mmio_Mc1_MemTestStat : std_ulogic_vector( 1 downto 0);
398  ---- CTRL_2 Register ---------------------
399  signal sSHL_ROL_Mmio_UdpEchoCtrl : std_ulogic_vector( 1 downto 0);
400  signal sSHL_ROL_Mmio_UdpPostDgmEn : std_ulogic;
401  signal sSHL_ROL_Mmio_UdpCaptDgmEn : std_ulogic;
402  signal sSHL_ROL_Mmio_TcpEchoCtrl : std_ulogic_vector( 1 downto 0);
403  signal sSHL_ROL_Mmio_TcpPostSegEn : std_ulogic;
404  signal sSHL_ROL_Mmio_TcpCaptSegEn : std_ulogic;
405  ---- APP_RDROL[0:1] ---------------------
406  signal sROL_SHL_Mmio_RdReg : std_ulogic_vector( 15 downto 0);
407  ---- APP_WRROL[0:1] ---------------------
408  signal sSHL_ROL_Mmio_WrReg : std_ulogic_vector( 15 downto 0);
409 
410  --===========================================================================
411  --== COMPONENT DECLARATIONS
412  --===========================================================================
413 
414  -- [INFO] The SHELL component is declared in the corresponding TOP package.
415  -- not this time
416  -- to declare the component in the pkg seems not to work for Verilog or .dcp modules
417  component Shell_Kale
418  generic (
419  gSecurityPriviledges : string := "super"; -- Can be "user" or "super"
420  gBitstreamUsage : string := "flash"; -- Can be "user" or "flash"
421  gMmioAddrWidth : integer := 8; -- Default is 8-bits
422  gMmioDataWidth : integer := 8 -- Default is 8-bits
423  );
424  port (
425  ------------------------------------------------------
426  -- TOP / Input Clocks and Resets from topFMKU60
427  ------------------------------------------------------
428  piTOP_156_25Rst : in std_ulogic;
429  piTOP_156_25Clk : in std_ulogic;
430  ------------------------------------------------------
431  -- TOP / Bitstream Identification
432  ------------------------------------------------------
433  piTOP_Timestamp : in std_ulogic_vector( 31 downto 0);
434  ------------------------------------------------------
435  -- CLKT / Clock Tree Interface
436  ------------------------------------------------------
437  piCLKT_Mem0Clk_n : in std_ulogic;
438  piCLKT_Mem0Clk_p : in std_ulogic;
439  piCLKT_Mem1Clk_n : in std_ulogic;
440  piCLKT_Mem1Clk_p : in std_ulogic;
441  piCLKT_10GeClk_n : in std_ulogic;
442  piCLKT_10GeClk_p : in std_ulogic;
443  ------------------------------------------------------
444  -- PSOC / External Memory Interface (Emif)
445  ------------------------------------------------------
446  piPSOC_Emif_Clk : in std_ulogic;
447  piPSOC_Emif_Cs_n : in std_ulogic;
448  piPSOC_Emif_We_n : in std_ulogic;
449  piPSOC_Emif_Oe_n : in std_ulogic;
450  piPSOC_Emif_AdS_n : in std_ulogic;
451  piPSOC_Emif_Addr : in std_ulogic_vector(gMmioAddrWidth-1 downto 0);
452  pioPSOC_Emif_Data : inout std_ulogic_vector(gMmioDataWidth-1 downto 0);
453  ------------------------------------------------------
454  -- LED / Heart Beat Interface (Yellow LED)
455  ------------------------------------------------------
456  poLED_HeartBeat_n : out std_ulogic;
457  ------------------------------------------------------
458  -- DDR4 / Memory Channel 0 Interface (Mc0)
459  ------------------------------------------------------
460  pioDDR4_Mem_Mc0_DmDbi_n : inout std_ulogic_vector( 8 downto 0);
461  pioDDR4_Mem_Mc0_Dq : inout std_ulogic_vector( 71 downto 0);
462  pioDDR4_Mem_Mc0_Dqs_n : inout std_ulogic_vector( 8 downto 0);
463  pioDDR4_Mem_Mc0_Dqs_p : inout std_ulogic_vector( 8 downto 0);
464  poDDR4_Mem_Mc0_Act_n : out std_ulogic;
465  poDDR4_Mem_Mc0_Adr : out std_ulogic_vector( 16 downto 0);
466  poDDR4_Mem_Mc0_Ba : out std_ulogic_vector( 1 downto 0);
467  poDDR4_Mem_Mc0_Bg : out std_ulogic_vector( 1 downto 0);
468  poDDR4_Mem_Mc0_Cke : out std_ulogic;
469  poDDR4_Mem_Mc0_Odt : out std_ulogic;
470  poDDR4_Mem_Mc0_Cs_n : out std_ulogic;
471  poDDR4_Mem_Mc0_Ck_n : out std_ulogic;
472  poDDR4_Mem_Mc0_Ck_p : out std_ulogic;
473  poDDR4_Mem_Mc0_Reset_n : out std_ulogic;
474  ------------------------------------------------------
475  -- DDR4 / Memory Channel 1 Interface (Mc1)
476  ------------------------------------------------------
477  pioDDR4_Mem_Mc1_DmDbi_n : inout std_ulogic_vector( 8 downto 0);
478  pioDDR4_Mem_Mc1_Dq : inout std_ulogic_vector( 71 downto 0);
479  pioDDR4_Mem_Mc1_Dqs_n : inout std_ulogic_vector( 8 downto 0);
480  pioDDR4_Mem_Mc1_Dqs_p : inout std_ulogic_vector( 8 downto 0);
481  poDDR4_Mem_Mc1_Act_n : out std_ulogic;
482  poDDR4_Mem_Mc1_Adr : out std_ulogic_vector( 16 downto 0);
483  poDDR4_Mem_Mc1_Ba : out std_ulogic_vector( 1 downto 0);
484  poDDR4_Mem_Mc1_Bg : out std_ulogic_vector( 1 downto 0);
485  poDDR4_Mem_Mc1_Cke : out std_ulogic;
486  poDDR4_Mem_Mc1_Odt : out std_ulogic;
487  poDDR4_Mem_Mc1_Cs_n : out std_ulogic;
488  poDDR4_Mem_Mc1_Ck_n : out std_ulogic;
489  poDDR4_Mem_Mc1_Ck_p : out std_ulogic;
490  poDDR4_Mem_Mc1_Reset_n : out std_ulogic;
491  ------------------------------------------------------
492  -- ECON / Edge Connector Interface (SPD08-200)
493  ------------------------------------------------------
494  piECON_Eth_10Ge0_n : in std_ulogic;
495  piECON_Eth_10Ge0_p : in std_ulogic;
496  poECON_Eth_10Ge0_n : out std_ulogic;
497  poECON_Eth_10Ge0_p : out std_ulogic;
498  ------------------------------------------------------
499  -- ROLE / Output Clock and Reset Interfaces
500  ------------------------------------------------------
501  poROL_156_25Clk : out std_ulogic;
502  poROL_156_25Rst : out std_ulogic;
503  ------------------------------------------------------
504  -- ROLE / Nts / Udp / Tx Data Interfaces (.i.e ROLE-->SHELL)
505  ------------------------------------------------------
506  ---- Axi4-Stream UDP Data ---------------
507  siROL_Nts_Udp_Data_tdata : in std_ulogic_vector( 63 downto 0);
508  siROL_Nts_Udp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
509  siROL_Nts_Udp_Data_tlast : in std_ulogic;
510  siROL_Nts_Udp_Data_tvalid : in std_ulogic;
511  siROL_Nts_Udp_Data_tready : out std_ulogic;
512  ---- Axi4-Stream UDP Metadata -----------
513  siROL_Nts_Udp_Meta_tdata : in std_logic_vector( 95 downto 0);
514  siROL_Nts_Udp_Meta_tvalid : in std_ulogic;
515  siROL_Nts_Udp_Meta_tready : out std_ulogic;
516  ---- Axis4Stream UDP Data Length ---------
517  siROL_Nts_Udp_DLen_tdata : in std_logic_vector( 15 downto 0);
518  siROL_Nts_Udp_DLen_tvalid : in std_ulogic;
519  siROL_Nts_Udp_DLen_tready : out std_ulogic;
520  ------------------------------------------------------
521  -- ROLE / Nts / Udp / Rx Data Interfaces (.i.e SHELL-->ROLE)
522  ------------------------------------------------------
523  ---- Axi4-Stream UDP Data ---------------
524  soROL_Nts_Udp_Data_tdata : out std_ulogic_vector( 63 downto 0);
525  soROL_Nts_Udp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
526  soROL_Nts_Udp_Data_tlast : out std_ulogic;
527  soROL_Nts_Udp_Data_tvalid : out std_ulogic;
528  soROL_Nts_Udp_Data_tready : in std_ulogic;
529  ---- Axi4-Stream UDP Metadata -----------
530  soROL_Nts_Udp_Meta_tdata : out std_logic_vector( 95 downto 0);
531  soROL_Nts_Udp_Meta_tvalid : out std_ulogic;
532  soROL_Nts_Udp_Meta_tready : in std_ulogic;
533  ---- Axi4-Stream UDP Data Len -----------
534  soROL_Nts_Udp_DLen_tdata : out std_logic_vector( 15 downto 0);
535  soROL_Nts_Udp_DLen_tvalid : out std_ulogic;
536  soROL_Nts_Udp_DLen_tready : in std_ulogic;
537  ------------------------------------------------------
538  -- ROLE / Nts/ Udp / Rx Ctrl Interfaces (.i.e SHELL<-->ROLE)
539  ------------------------------------------------------
540  ---- Axi4-Stream UDP Listen Request -----
541  siROL_Nts_Udp_LsnReq_tdata : in std_ulogic_vector( 15 downto 0);
542  siROL_Nts_Udp_LsnReq_tvalid : in std_ulogic;
543  siROL_Nts_Udp_LsnReq_tready : out std_ulogic;
544  ---- Axi4-Stream UDP Listen Reply --------
545  soROL_Nts_Udp_LsnRep_tdata : out std_ulogic_vector( 7 downto 0);
546  soROL_Nts_Udp_LsnRep_tvalid : out std_ulogic;
547  soROL_Nts_Udp_LsnRep_tready : in std_ulogic;
548  ---- Axi4-Stream UDP Close Request ------
549  siROL_Nts_Udp_ClsReq_tdata : in std_ulogic_vector( 15 downto 0);
550  siROL_Nts_Udp_ClsReq_tvalid : in std_ulogic;
551  siROL_Nts_Udp_ClsReq_tready : out std_ulogic;
552  ---- Axi4-Stream UDP Close Reply ---------
553  soROL_Nts_Udp_ClsRep_tdata : out std_ulogic_vector( 7 downto 0);
554  soROL_Nts_Udp_ClsRep_tvalid : out std_ulogic;
555  soROL_Nts_Udp_ClsRep_tready : in std_ulogic;
556  ------------------------------------------------------
557  -- ROLE / Nts / Tcp / Tx Data Interfaces (.i.e ROLE-->SHELL)
558  ------------------------------------------------------
559  ---- Axi4-Stream TCP Data ---------------
560  siROL_Nts_Tcp_Data_tdata : in std_ulogic_vector( 63 downto 0);
561  siROL_Nts_Tcp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
562  siROL_Nts_Tcp_Data_tlast : in std_ulogic;
563  siROL_Nts_Tcp_Data_tvalid : in std_ulogic;
564  siROL_Nts_Tcp_Data_tready : out std_ulogic;
565  ---- Axi4-Stream TCP Send Request -------
566  siROL_Nts_Tcp_SndReq_tdata : in std_ulogic_vector( 31 downto 0);
567  siROL_Nts_Tcp_SndReq_tvalid : in std_ulogic;
568  siROL_Nts_Tcp_SndReq_tready : out std_ulogic;
569  ---- Axi4-Stream TCP Send Reply ---------
570  soROL_Nts_Tcp_SndRep_tdata : out std_ulogic_vector( 55 downto 0);
571  soROL_Nts_Tcp_SndRep_tvalid : out std_ulogic;
572  soROL_Nts_Tcp_SndRep_tready : in std_ulogic;
573  ------------------------------------------------------
574  -- ROLE / Nts / Tcp / Rx Data Interfaces (.i.e SHELL-->ROLE)
575  ------------------------------------------------------
576  -- Axi4-Stream TCP Data -----------------
577  soROL_Nts_Tcp_Data_tdata : out std_ulogic_vector( 63 downto 0);
578  soROL_Nts_Tcp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
579  soROL_Nts_Tcp_Data_tlast : out std_ulogic;
580  soROL_Nts_Tcp_Data_tvalid : out std_ulogic;
581  soROL_Nts_Tcp_Data_tready : in std_ulogic;
582  -- Axi4-Stream TCP Metadata ------------
583  soROL_Nts_Tcp_Meta_tdata : out std_ulogic_vector( 15 downto 0);
584  soROL_Nts_Tcp_Meta_tvalid : out std_ulogic;
585  soROL_Nts_Tcp_Meta_tready : in std_ulogic;
586  -- Axi4-Stream TCP Data Notification ---
587  soROL_Nts_Tcp_Notif_tdata : out std_ulogic_vector(7+96 downto 0); -- 8-bits boundary
588  soROL_Nts_Tcp_Notif_tvalid : out std_ulogic;
589  soROL_Nts_Tcp_Notif_tready : in std_ulogic;
590  ---- Stream TCP Data Request -------
591  siROL_Nts_Tcp_DReq_tdata : in std_ulogic_vector( 31 downto 0);
592  siROL_Nts_Tcp_DReq_tvalid : in std_ulogic;
593  siROL_Nts_Tcp_DReq_tready : out std_ulogic;
594  ------------------------------------------------------
595  -- ROLE / Nts / Tcp / TxP Ctlr Interfaces (.i.e ROLE-->SHELL)
596  ------------------------------------------------------
597  ---- Axi4-Stream TCP Open Session Request
598  siROL_Nts_Tcp_OpnReq_tdata : in std_ulogic_vector( 47 downto 0);
599  siROL_Nts_Tcp_OpnReq_tvalid : in std_ulogic;
600  siROL_Nts_Tcp_OpnReq_tready : out std_ulogic;
601  ----- Axi4-Stream TCP Open Session Reply
602  soROL_Nts_Tcp_OpnRep_tdata : out std_ulogic_vector( 23 downto 0);
603  soROL_Nts_Tcp_OpnRep_tvalid : out std_ulogic;
604  soROL_Nts_Tcp_OpnRep_tready : in std_ulogic;
605  ---- Axi4-Stream TCP Close Request ------
606  siROL_Nts_Tcp_ClsReq_tdata : in std_ulogic_vector( 15 downto 0);
607  siROL_Nts_Tcp_ClsReq_tvalid : in std_ulogic;
608  siROL_Nts_Tcp_ClsReq_tready : out std_ulogic;
609  ------------------------------------------------------
610  -- ROLE / Nts / Tcp / Rx Ctlr Interfaces (.i.e SHELL-->ROLE)
611  ------------------------------------------------------
612  ---- Axi4-Stream TCP Listen Request ----
613  siROL_Nts_Tcp_LsnReq_tdata : in std_ulogic_vector( 15 downto 0);
614  siROL_Nts_Tcp_LsnReq_tvalid : in std_ulogic;
615  siROL_Nts_Tcp_LsnReq_tready : out std_ulogic;
616  ---- Axi4-Stream TCP Listen Rep --------
617  soROL_Nts_Tcp_LsnRep_tdata : out std_ulogic_vector( 7 downto 0);
618  soROL_Nts_Tcp_LsnRep_tvalid : out std_ulogic;
619  soROL_Nts_Tcp_LsnRep_tready : in std_ulogic;
620  ------------------------------------------------------
621  -- ROLE / Mem / Mp0 Interface
622  ------------------------------------------------------
623  -- Memory Port #0 / S2MM-AXIS ------------------
624  ---- Stream Read Command -----------------
625  siROL_Mem_Mp0_RdCmd_tdata : in std_ulogic_vector( 79 downto 0);
626  siROL_Mem_Mp0_RdCmd_tvalid : in std_ulogic;
627  siROL_Mem_Mp0_RdCmd_tready : out std_ulogic;
628  ---- Stream Read Status ------------------
629  soROL_Mem_Mp0_RdSts_tdata : out std_ulogic_vector( 7 downto 0);
630  soROL_Mem_Mp0_RdSts_tvalid : out std_ulogic;
631  soROL_Mem_Mp0_RdSts_tready : in std_ulogic;
632  ---- Stream Data Output Channel ----------
633  soROL_Mem_Mp0_Read_tdata : out std_ulogic_vector(511 downto 0);
634  soROL_Mem_Mp0_Read_tkeep : out std_ulogic_vector( 63 downto 0);
635  soROL_Mem_Mp0_Read_tlast : out std_ulogic;
636  soROL_Mem_Mp0_Read_tvalid : out std_ulogic;
637  soROL_Mem_Mp0_Read_tready : in std_ulogic;
638  ---- Stream Write Command ----------------
639  siROL_Mem_Mp0_WrCmd_tdata : in std_ulogic_vector( 79 downto 0);
640  siROL_Mem_Mp0_WrCmd_tvalid : in std_ulogic;
641  siROL_Mem_Mp0_WrCmd_tready : out std_ulogic;
642  ---- Stream Write Status -----------------
643  soROL_Mem_Mp0_WrSts_tvalid : out std_ulogic;
644  soROL_Mem_Mp0_WrSts_tdata : out std_ulogic_vector( 7 downto 0);
645  soROL_Mem_Mp0_WrSts_tready : in std_ulogic;
646  ---- Stream Data Input Channel -----------
647  siROL_Mem_Mp0_Write_tdata : in std_ulogic_vector(511 downto 0);
648  siROL_Mem_Mp0_Write_tkeep : in std_ulogic_vector( 63 downto 0);
649  siROL_Mem_Mp0_Write_tlast : in std_ulogic;
650  siROL_Mem_Mp0_Write_tvalid : in std_ulogic;
651  siROL_Mem_Mp0_Write_tready : out std_ulogic;
652  ------------------------------------------------------
653  -- ROLE / Mem / Mp1 Interface
654  ------------------------------------------------------
655  miROL_Mem_Mp1_AWID : in std_ulogic_vector( 7 downto 0);
656  miROL_Mem_Mp1_AWADDR : in std_ulogic_vector( 32 downto 0);
657  miROL_Mem_Mp1_AWLEN : in std_ulogic_vector( 7 downto 0);
658  miROL_Mem_Mp1_AWSIZE : in std_ulogic_vector( 2 downto 0);
659  miROL_Mem_Mp1_AWBURST : in std_ulogic_vector( 1 downto 0);
660  miROL_Mem_Mp1_AWVALID : in std_ulogic;
661  miROL_Mem_Mp1_AWREADY : out std_ulogic;
662  miROL_Mem_Mp1_WDATA : in std_ulogic_vector(511 downto 0);
663  miROL_Mem_Mp1_WSTRB : in std_ulogic_vector( 63 downto 0);
664  miROL_Mem_Mp1_WLAST : in std_ulogic;
665  miROL_Mem_Mp1_WVALID : in std_ulogic;
666  miROL_Mem_Mp1_WREADY : out std_ulogic;
667  miROL_Mem_Mp1_BID : out std_ulogic_vector( 7 downto 0);
668  miROL_Mem_Mp1_BRESP : out std_ulogic_vector( 1 downto 0);
669  miROL_Mem_Mp1_BVALID : out std_ulogic;
670  miROL_Mem_Mp1_BREADY : in std_ulogic;
671  miROL_Mem_Mp1_ARID : in std_ulogic_vector( 7 downto 0);
672  miROL_Mem_Mp1_ARADDR : in std_ulogic_vector( 32 downto 0);
673  miROL_Mem_Mp1_ARLEN : in std_ulogic_vector( 7 downto 0);
674  miROL_Mem_Mp1_ARSIZE : in std_ulogic_vector( 2 downto 0);
675  miROL_Mem_Mp1_ARBURST : in std_ulogic_vector( 1 downto 0);
676  miROL_Mem_Mp1_ARVALID : in std_ulogic;
677  miROL_Mem_Mp1_ARREADY : out std_ulogic;
678  miROL_Mem_Mp1_RID : out std_ulogic_vector( 7 downto 0);
679  miROL_Mem_Mp1_RDATA : out std_ulogic_vector(511 downto 0);
680  miROL_Mem_Mp1_RRESP : out std_ulogic_vector( 1 downto 0);
681  miROL_Mem_Mp1_RLAST : out std_ulogic;
682  miROL_Mem_Mp1_RVALID : out std_ulogic;
683  miROL_Mem_Mp1_RREADY : in std_ulogic;
684  --------------------------------------------------------
685  -- ROLE / Mmio / AppFlash Interface
686  --------------------------------------------------------
687  ---- PHY_RESET --------------------
688  poROL_Mmio_Ly7Rst : out std_ulogic;
689  ---- PHY_ENABLE -------------------
690  poROL_Mmio_Ly7En : out std_ulogic;
691  ---- DIAG_CTRL_1 ------------------
692  poROL_Mmio_Mc1_MemTestCtrl : out std_ulogic_vector( 1 downto 0);
693  ---- DIAG_STAT_1 -----------------
694  piROL_Mmio_Mc1_MemTestStat : in std_ulogic_vector( 1 downto 0); -- [FIXME: Why 7:0 and not 7:6 ? ]
695  ---- DIAG_CTRL_2 ------------------
696  poROL_Mmio_UdpEchoCtrl : out std_ulogic_vector( 1 downto 0);
697  poROL_Mmio_UdpPostDgmEn : out std_ulogic;
698  poROL_Mmio_UdpCaptDgmEn : out std_ulogic;
699  poROL_Mmio_TcpEchoCtrl : out std_ulogic_vector( 1 downto 0);
700  poROL_Mmio_TcpPostSegEn : out std_ulogic;
701  poROL_Mmio_TcpCaptSegEn : out std_ulogic;
702  ---- APP_RDROL --------------------
703  piROL_Mmio_RdReg : in std_ulogic_vector( 15 downto 0);
704  ---- APP_WRROL --------------------
705  poROL_Mmio_WrReg : out std_ulogic_vector( 15 downto 0)
706  );
707  end component Shell_Kale;
708 
709  -- [INFO] The ROLE component is declared in the corresponding TOP package.
710  -- not this time
711  -- to declare the component in the pkg seems not to work for Verilog or .dcp modules
712  component Role_Kale
713  generic (
714  gVivadoVersion : integer := 2019
715  );
716  port (
717  ------------------------------------------------------
718  -- TOP / Global Input Clock and Reset Interface
719  ------------------------------------------------------
720  piSHL_156_25Clk : in std_ulogic;
721  piSHL_156_25Rst : in std_ulogic;
722  ------------------------------------------------------
723  --- SHELL / Nts / Udp / Tx Data Interfaces (.i.e SHELL-->ROLE)
724  ------------------------------------------------------
725  ---- Axi4-Stream UDP Data ----------------
726  siSHL_Nts_Udp_Data_tdata : in std_ulogic_vector( 63 downto 0);
727  siSHL_Nts_Udp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
728  siSHL_Nts_Udp_Data_tvalid : in std_ulogic;
729  siSHL_Nts_Udp_Data_tlast : in std_ulogic;
730  siSHL_Nts_Udp_Data_tready : out std_ulogic;
731  ---- Axi4-Stream UDP Metadata ------------
732  siSHL_Nts_Udp_Meta_tdata : in std_ulogic_vector( 95 downto 0);
733  siSHL_Nts_Udp_Meta_tvalid : in std_ulogic;
734  siSHL_Nts_Udp_Meta_tready : out std_ulogic;
735  ---- Axi4-Stream UDP Data Len ------------
736  siSHL_Nts_Udp_DLen_tdata : in std_ulogic_vector( 15 downto 0);
737  siSHL_Nts_Udp_DLen_tvalid : in std_ulogic;
738  siSHL_Nts_Udp_DLen_tready : out std_ulogic;
739  ------------------------------------------------------
740  -- SHELL / Nts / Udp / Rx Data Interfaces (.i.e ROLE-->SHELL)
741  -----------------------------------------------------
742  ---- Axi4-Stream UDP Data ---------------
743  soSHL_Nts_Udp_Data_tdata : out std_ulogic_vector( 63 downto 0);
744  soSHL_Nts_Udp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
745  soSHL_Nts_Udp_Data_tvalid : out std_ulogic;
746  soSHL_Nts_Udp_Data_tlast : out std_ulogic;
747  soSHL_Nts_Udp_Data_tready : in std_ulogic;
748  ---- Axi4-Stream UDP Meta ---------------
749  soSHL_Nts_Udp_Meta_tdata : out std_ulogic_vector( 95 downto 0);
750  soSHL_Nts_Udp_Meta_tvalid : out std_ulogic;
751  soSHL_Nts_Udp_Meta_tready : in std_ulogic;
752  ---- Axi4-Stream UDP Data Length ---------
753  soSHL_Nts_Udp_DLen_tdata : out std_ulogic_vector( 15 downto 0);
754  soSHL_Nts_Udp_DLen_tvalid : out std_ulogic;
755  soSHL_Nts_Udp_DLen_tready : in std_ulogic;
756  ------------------------------------------------------
757  -- SHELL / Nts/ Udp / Rx Ctrl Interfaces (.i.e ROLE<-->SHELL)
758  ------------------------------------------------------
759  ---- Axi4-Stream UDP Listen Request -----
760  soSHL_Nts_Udp_LsnReq_tdata : out std_ulogic_vector( 15 downto 0);
761  soSHL_Nts_Udp_LsnReq_tvalid : out std_ulogic;
762  soSHL_Nts_Udp_LsnReq_tready : in std_ulogic;
763  ---- Axi4-Stream UDP Listen Reply --------
764  siSHL_Nts_Udp_LsnRep_tdata : in std_ulogic_vector( 7 downto 0);
765  siSHL_Nts_Udp_LsnRep_tvalid : in std_ulogic;
766  siSHL_Nts_Udp_LsnRep_tready : out std_ulogic;
767  ---- Axi4-Stream UDP Close Request ------
768  soSHL_Nts_Udp_ClsReq_tdata : out std_ulogic_vector( 15 downto 0);
769  soSHL_Nts_Udp_ClsReq_tvalid : out std_ulogic;
770  soSHL_Nts_Udp_ClsReq_tready : in std_ulogic;
771  --- Axi4-Stream UDP Close Reply ---------
772  siSHL_Nts_Udp_ClsRep_tdata : in std_ulogic_vector( 7 downto 0);
773  siSHL_Nts_Udp_ClsRep_tvalid : in std_ulogic;
774  siSHL_Nts_Udp_ClsRep_tready : out std_ulogic;
775  ------------------------------------------------------
776  -- SHELL / Nts / Tcp / Tx Data Interfaces (.i.e ROLE-->SHELL)
777  ------------------------------------------------------
778  ---- Axi4-Stream TCP Data ---------------
779  soSHL_Nts_Tcp_Data_tdata : out std_ulogic_vector( 63 downto 0);
780  soSHL_Nts_Tcp_Data_tkeep : out std_ulogic_vector( 7 downto 0);
781  soSHL_Nts_Tcp_Data_tlast : out std_ulogic;
782  soSHL_Nts_Tcp_Data_tvalid : out std_ulogic;
783  soSHL_Nts_Tcp_Data_tready : in std_ulogic;
784  ---- Axi4-Stream TCP Send Request -------
785  soSHL_Nts_Tcp_SndReq_tdata : out std_ulogic_vector( 31 downto 0);
786  soSHL_Nts_Tcp_SndReq_tvalid : out std_ulogic;
787  soSHL_Nts_Tcp_SndReq_tready : in std_ulogic;
788  ---- Axi4-Stream TCP Send Reply ---------
789  siSHL_Nts_Tcp_SndRep_tdata : in std_ulogic_vector( 55 downto 0);
790  siSHL_Nts_Tcp_SndRep_tvalid : in std_ulogic;
791  siSHL_Nts_Tcp_SndRep_tready : out std_ulogic;
792  --------------------------------------------------------
793  -- SHELL / Nts / Tcp / Rx Data Interfaces (.i.e SHELL-->ROLE)
794  --------------------------------------------------------
795  ---- Axi4-Stream TCP Data -----------------
796  siSHL_Nts_Tcp_Data_tdata : in std_ulogic_vector( 63 downto 0);
797  siSHL_Nts_Tcp_Data_tkeep : in std_ulogic_vector( 7 downto 0);
798  siSHL_Nts_Tcp_Data_tlast : in std_ulogic;
799  siSHL_Nts_Tcp_Data_tvalid : in std_ulogic;
800  siSHL_Nts_Tcp_Data_tready : out std_ulogic;
801  ----- Axi4-Stream TCP Metadata ------------
802  siSHL_Nts_Tcp_Meta_tdata : in std_ulogic_vector( 15 downto 0);
803  siSHL_Nts_Tcp_Meta_tvalid : in std_ulogic;
804  siSHL_Nts_Tcp_Meta_tready : out std_ulogic;
805  ---- Axi4-Stream TCP Data Notification ---
806  siSHL_Nts_Tcp_Notif_tdata : in std_ulogic_vector(7+96 downto 0); -- 8-bits boundary
807  siSHL_Nts_Tcp_Notif_tvalid : in std_ulogic;
808  siSHL_Nts_Tcp_Notif_tready : out std_ulogic;
809  ---- Axi4-Stream TCP Data Request --------
810  soSHL_Nts_Tcp_DReq_tdata : out std_ulogic_vector( 31 downto 0);
811  soSHL_Nts_Tcp_DReq_tvalid : out std_ulogic;
812  soSHL_Nts_Tcp_DReq_tready : in std_ulogic;
813  ------------------------------------------------------
814  -- SHELL / Nts / Tcp / TxP Ctlr Interfaces (.i.e ROLE<-->SHELL)
815  ------------------------------------------------------
816  ---- Axi4-Stream TCP Open Session Request
817  soSHL_Nts_Tcp_OpnReq_tdata : out std_ulogic_vector( 47 downto 0);
818  soSHL_Nts_Tcp_OpnReq_tvalid : out std_ulogic;
819  soSHL_Nts_Tcp_OpnReq_tready : in std_ulogic;
820  ---- Axi4-Stream TCP Open Session Reply
821  siSHL_Nts_Tcp_OpnRep_tdata : in std_ulogic_vector( 23 downto 0);
822  siSHL_Nts_Tcp_OpnRep_tvalid : in std_ulogic;
823  siSHL_Nts_Tcp_OpnRep_tready : out std_ulogic;
824  ---- Axi4-Stream TCP Close Request ------
825  soSHL_Nts_Tcp_ClsReq_tdata : out std_ulogic_vector( 15 downto 0);
826  soSHL_Nts_Tcp_ClsReq_tvalid : out std_ulogic;
827  soSHL_Nts_Tcp_ClsReq_tready : in std_ulogic;
828  ------------------------------------------------------
829  -- SHELL / Nts / Tcp / Rx Ctlr Interfaces (.i.e SHELL-->ROLE)
830  ------------------------------------------------------
831  ---- Axi4-Stream TCP Listen Request ----
832  soSHL_Nts_Tcp_LsnReq_tdata : out std_ulogic_vector( 15 downto 0);
833  soSHL_Nts_Tcp_LsnReq_tvalid : out std_ulogic;
834  soSHL_Nts_Tcp_LsnReq_tready : in std_ulogic;
835  ---- Stream TCP Listen Status ----
836  siSHL_Nts_Tcp_LsnRep_tdata : in std_ulogic_vector( 7 downto 0);
837  siSHL_Nts_Tcp_LsnRep_tvalid : in std_ulogic;
838  siSHL_Nts_Tcp_LsnRep_tready : out std_ulogic;
839  ------------------------------------------------------
840  -- SHELL / Mem / Mp0 Interface
841  ------------------------------------------------------
842  ---- Memory Port #0 / S2MM-AXIS -------------
843  ------ Stream Read Command ---------
844  soSHL_Mem_Mp0_RdCmd_tdata : out std_ulogic_vector( 79 downto 0);
845  soSHL_Mem_Mp0_RdCmd_tvalid : out std_ulogic;
846  soSHL_Mem_Mp0_RdCmd_tready : in std_ulogic;
847  ------ Stream Read Status ----------
848  siSHL_Mem_Mp0_RdSts_tdata : in std_ulogic_vector( 7 downto 0);
849  siSHL_Mem_Mp0_RdSts_tvalid : in std_ulogic;
850  siSHL_Mem_Mp0_RdSts_tready : out std_ulogic;
851  ------ Stream Data Input Channel ---
852  siSHL_Mem_Mp0_Read_tdata : in std_ulogic_vector(511 downto 0);
853  siSHL_Mem_Mp0_Read_tkeep : in std_ulogic_vector( 63 downto 0);
854  siSHL_Mem_Mp0_Read_tlast : in std_ulogic;
855  siSHL_Mem_Mp0_Read_tvalid : in std_ulogic;
856  siSHL_Mem_Mp0_Read_tready : out std_ulogic;
857  ------ Stream Write Command --------
858  soSHL_Mem_Mp0_WrCmd_tdata : out std_ulogic_vector( 79 downto 0);
859  soSHL_Mem_Mp0_WrCmd_tvalid : out std_ulogic;
860  soSHL_Mem_Mp0_WrCmd_tready : in std_ulogic;
861  ------ Stream Write Status ---------
862  siSHL_Mem_Mp0_WrSts_tvalid : in std_ulogic;
863  siSHL_Mem_Mp0_WrSts_tdata : in std_ulogic_vector( 7 downto 0);
864  siSHL_Mem_Mp0_WrSts_tready : out std_ulogic;
865  ------ Stream Data Output Channel --
866  soSHL_Mem_Mp0_Write_tdata : out std_ulogic_vector(511 downto 0);
867  soSHL_Mem_Mp0_Write_tkeep : out std_ulogic_vector( 63 downto 0);
868  soSHL_Mem_Mp0_Write_tlast : out std_ulogic;
869  soSHL_Mem_Mp0_Write_tvalid : out std_ulogic;
870  soSHL_Mem_Mp0_Write_tready : in std_ulogic;
871  ------------------------------------------------------
872  -- SHELL / Mem / Mp1 Interface
873  ------------------------------------------------------
874  moSHL_Mem_Mp1_AWID : out std_ulogic_vector( 7 downto 0);
875  moSHL_Mem_Mp1_AWADDR : out std_ulogic_vector( 32 downto 0);
876  moSHL_Mem_Mp1_AWLEN : out std_ulogic_vector( 7 downto 0);
877  moSHL_Mem_Mp1_AWSIZE : out std_ulogic_vector( 2 downto 0);
878  moSHL_Mem_Mp1_AWBURST : out std_ulogic_vector( 1 downto 0);
879  moSHL_Mem_Mp1_AWVALID : out std_ulogic;
880  moSHL_Mem_Mp1_AWREADY : in std_ulogic;
881  moSHL_Mem_Mp1_WDATA : out std_ulogic_vector(511 downto 0);
882  moSHL_Mem_Mp1_WSTRB : out std_ulogic_vector( 63 downto 0);
883  moSHL_Mem_Mp1_WLAST : out std_ulogic;
884  moSHL_Mem_Mp1_WVALID : out std_ulogic;
885  moSHL_Mem_Mp1_WREADY : in std_ulogic;
886  moSHL_Mem_Mp1_BID : in std_ulogic_vector( 7 downto 0);
887  moSHL_Mem_Mp1_BRESP : in std_ulogic_vector( 1 downto 0);
888  moSHL_Mem_Mp1_BVALID : in std_ulogic;
889  moSHL_Mem_Mp1_BREADY : out std_ulogic;
890  moSHL_Mem_Mp1_ARID : out std_ulogic_vector( 7 downto 0);
891  moSHL_Mem_Mp1_ARADDR : out std_ulogic_vector( 32 downto 0);
892  moSHL_Mem_Mp1_ARLEN : out std_ulogic_vector( 7 downto 0);
893  moSHL_Mem_Mp1_ARSIZE : out std_ulogic_vector( 2 downto 0);
894  moSHL_Mem_Mp1_ARBURST : out std_ulogic_vector( 1 downto 0);
895  moSHL_Mem_Mp1_ARVALID : out std_ulogic;
896  moSHL_Mem_Mp1_ARREADY : in std_ulogic;
897  moSHL_Mem_Mp1_RID : in std_ulogic_vector( 7 downto 0);
898  moSHL_Mem_Mp1_RDATA : in std_ulogic_vector(511 downto 0);
899  moSHL_Mem_Mp1_RRESP : in std_ulogic_vector( 1 downto 0);
900  moSHL_Mem_Mp1_RLAST : in std_ulogic;
901  moSHL_Mem_Mp1_RVALID : in std_ulogic;
902  moSHL_Mem_Mp1_RREADY : out std_ulogic;
903  --------------------------------------------------------
904  -- SHELL / Mmio / AppFlash Interface
905  --------------------------------------------------------
906  ---- [PHY_RESET] -------------------
907  piSHL_Mmio_Ly7Rst : in std_ulogic;
908  ---- [PHY_ENABLE] ------------------
909  piSHL_Mmio_Ly7En : in std_ulogic;
910  ---- [DIAG_CTRL_1] -----------------
911  piSHL_Mmio_Mc1_MemTestCtrl : in std_ulogic_vector( 1 downto 0);
912  ---- [DIAG_STAT_1] -----------------
913  poSHL_Mmio_Mc1_MemTestStat : out std_ulogic_vector( 1 downto 0);
914  ---- [DIAG_CTRL_2] -----------------
915  --[NOT_USED] piSHL_Mmio_UdpEchoCtrl : in std_ulogic_vector( 1 downto 0);
916  --[NOT_USED] piSHL_Mmio_UdpPostDgmEn : in std_ulogic;
917  --[NOT_USED] piSHL_Mmio_UdpCaptDgmEn : in std_ulogic;
918  --[NOT_USED] piSHL_Mmio_TcpEchoCtrl : in std_ulogic_vector( 1 downto 0);
919  --[NOT_USED] piSHL_Mmio_TcpPostSegEn : in std_ulogic;
920  --[NOT_USED] piSHL_Mmio_TcpCaptSegEn : in std_ulogic;
921  ---- [APP_RDROL] -------------------
922  poSHL_Mmio_RdReg : out std_ulogic_vector( 15 downto 0);
923  --- [APP_WRROL] --------------------
924  piSHL_Mmio_WrReg : in std_ulogic_vector( 15 downto 0);
925  --------------------------------------------------------
926  -- TOP : Secondary Clock (Asynchronous)
927  --------------------------------------------------------
928  piTOP_250_00Clk : in std_ulogic -- Freerunning
929  );
930  end component Role_Kale;
931 
932 begin
933 
934  --===========================================================================
935  --== INST: INPUT USER CLOCK BUFFERS
936  --===========================================================================
937  CLKBUF0 : IBUFDS
938  generic map (
939  DQS_BIAS => "FALSE" -- (FALSE, TRUE)
940  )
941  port map (
942  O => sTOP_156_25Clk,
943  I => piCLKT_Usr0Clk_p,
944  IB => piCLKT_Usr0Clk_n
945  );
946 
947  CLKBUF1 : IBUFDS
948  generic map (
949  DQS_BIAS => "FALSE" -- (FALSE, TRUE)
950  )
951  port map (
952  O => sTOP_250_00Clk,
953  I => piCLKT_Usr1Clk_p,
954  IB => piCLKT_Usr1Clk_n
955  );
956 
957  --===========================================================================
958  --== INST: METASTABILITY HARDENED BLOCK FOR THE SYSTEM RESET (Active high)
959  --== [INFO] Note that we instantiate 2 or 3 library primitives rather than
960  --== a VHDL process because it makes it easier to apply the "ASYNC_REG"
961  --== property to those instances.
962  --===========================================================================
963  HW_RESET : HARD_SYNC
964  generic map (
965  INIT => '0', -- Initial values, '0', '1'
966  IS_CLK_INVERTED => '0', -- Programmable inversion on CLK input
967  LATENCY => 2 -- 2-3
968  )
969  port map (
970  CLK => sTOP_156_25Clk,
971  DIN => piPSOC_Fcfg_Rst_n,
972  DOUT => sTOP_156_25Rst_n
973  );
974  sTOP_156_25Rst <= not sTOP_156_25Rst_n;
975 
976  --===========================================================================
977  --== INST: BITSTREAM IDENTIFICATION BLOCK with USR_ACCESSE2 PRIMITIVE
978  --== [INFO] This component provides direct FPGA logic access to the 32-bit
979  --== value stored by the FPGA bitstream. We use this register to retrieve
980  --== an accurate timestamp corresponding to the date of the bitstream
981  --== generation (note that we don't track the sminiutes and seconds).
982  --============================================================================
983  TOP_TIMESTAMP : USR_ACCESSE2
984  port map (
985  CFGCLK => open, -- Not used in the static mode
986  DATA => sTOP_Timestamp, -- 32-bit configuration data
987  DATAVALID => open -- Not used in the static mode
988  );
989 
990  --==========================================================================
991  --== INST: SHELL FOR FMKU60
992  --== This version of the SHELL has the following user interfaces:
993  --== - one UDP, one TCP, and two MemoryPort interfaces.
994  --==========================================================================
995  SHELL : Shell_Kale
996  generic map (
997  gSecurityPriviledges => "super",
998  gBitstreamUsage => "flash",
999  gMmioAddrWidth => gEmifAddrWidth,
1000  gMmioDataWidth => gEmifDataWidth
1001  )
1002  port map (
1003  ------------------------------------------------------
1004  -- TOP / Input Clocks and Resets from topFMKU60
1005  ------------------------------------------------------
1006  piTOP_156_25Rst => sTOP_156_25Rst,
1007  piTOP_156_25Clk => sTOP_156_25Clk,
1008  ------------------------------------------------------
1009  -- TOP / Bitstream Identification
1010  ------------------------------------------------------
1011  piTOP_Timestamp => sTOP_Timestamp,
1012  ------------------------------------------------------
1013  -- CLKT / Clock Tree Interface
1014  ------------------------------------------------------
1015  piCLKT_Mem0Clk_n => piCLKT_Mem0Clk_n,
1016  piCLKT_Mem0Clk_p => piCLKT_Mem0Clk_p,
1017  piCLKT_Mem1Clk_n => piCLKT_Mem1Clk_n,
1018  piCLKT_Mem1Clk_p => piCLKT_Mem1Clk_p,
1019  piCLKT_10GeClk_n => piCLKT_10GeClk_n,
1020  piCLKT_10GeClk_p => piCLKT_10GeClk_p,
1021  ------------------------------------------------------
1022  -- PSOC / External Memory Interface => Emif)
1023  ------------------------------------------------------
1024  piPSOC_Emif_Clk => piPSOC_Emif_Clk,
1025  piPSOC_Emif_Cs_n => piPSOC_Emif_Cs_n,
1026  piPSOC_Emif_We_n => piPSOC_Emif_We_n,
1027  piPSOC_Emif_Oe_n => piPSOC_Emif_Oe_n,
1028  piPSOC_Emif_AdS_n => piPSOC_Emif_AdS_n,
1029  piPSOC_Emif_Addr => piPSOC_Emif_Addr,
1030  pioPSOC_Emif_Data => pioPSOC_Emif_Data,
1031  ------------------------------------------------------
1032  -- LED / Shl / Heart Beat Interface => Yellow LED)
1033  ------------------------------------------------------
1034  poLED_HeartBeat_n => poLED_HeartBeat_n,
1035  ------------------------------------------------------
1036  -- DDR4 / Memory Channel 0 Interface => (Mc0)
1037  ------------------------------------------------------
1038  pioDDR4_Mem_Mc0_DmDbi_n => pioDDR4_Mem_Mc0_DmDbi_n,
1039  pioDDR4_Mem_Mc0_Dq => pioDDR4_Mem_Mc0_Dq,
1040  pioDDR4_Mem_Mc0_Dqs_n => pioDDR4_Mem_Mc0_Dqs_n,
1041  pioDDR4_Mem_Mc0_Dqs_p => pioDDR4_Mem_Mc0_Dqs_p,
1042  poDDR4_Mem_Mc0_Act_n => poDDR4_Mem_Mc0_Act_n,
1043  poDDR4_Mem_Mc0_Adr => poDDR4_Mem_Mc0_Adr,
1044  poDDR4_Mem_Mc0_Ba => poDDR4_Mem_Mc0_Ba,
1045  poDDR4_Mem_Mc0_Bg => poDDR4_Mem_Mc0_Bg,
1046  poDDR4_Mem_Mc0_Cke => poDDR4_Mem_Mc0_Cke,
1047  poDDR4_Mem_Mc0_Odt => poDDR4_Mem_Mc0_Odt,
1048  poDDR4_Mem_Mc0_Cs_n => poDDR4_Mem_Mc0_Cs_n,
1049  poDDR4_Mem_Mc0_Ck_n => poDDR4_Mem_Mc0_Ck_n,
1050  poDDR4_Mem_Mc0_Ck_p => poDDR4_Mem_Mc0_Ck_p,
1051  poDDR4_Mem_Mc0_Reset_n => poDDR4_Mem_Mc0_Reset_n,
1052  ------------------------------------------------------
1053  -- DDR4 / Shl / Memory Channel 1 Interface (Mc1)
1054  ------------------------------------------------------
1055  pioDDR4_Mem_Mc1_DmDbi_n => pioDDR4_Mem_Mc1_DmDbi_n,
1056  pioDDR4_Mem_Mc1_Dq => pioDDR4_Mem_Mc1_Dq,
1057  pioDDR4_Mem_Mc1_Dqs_n => pioDDR4_Mem_Mc1_Dqs_n,
1058  pioDDR4_Mem_Mc1_Dqs_p => pioDDR4_Mem_Mc1_Dqs_p,
1059  poDDR4_Mem_Mc1_Act_n => poDDR4_Mem_Mc1_Act_n,
1060  poDDR4_Mem_Mc1_Adr => poDDR4_Mem_Mc1_Adr,
1061  poDDR4_Mem_Mc1_Ba => poDDR4_Mem_Mc1_Ba,
1062  poDDR4_Mem_Mc1_Bg => poDDR4_Mem_Mc1_Bg,
1063  poDDR4_Mem_Mc1_Cke => poDDR4_Mem_Mc1_Cke,
1064  poDDR4_Mem_Mc1_Odt => poDDR4_Mem_Mc1_Odt,
1065  poDDR4_Mem_Mc1_Cs_n => poDDR4_Mem_Mc1_Cs_n,
1066  poDDR4_Mem_Mc1_Ck_n => poDDR4_Mem_Mc1_Ck_n,
1067  poDDR4_Mem_Mc1_Ck_p => poDDR4_Mem_Mc1_Ck_p,
1068  poDDR4_Mem_Mc1_Reset_n => poDDR4_Mem_Mc1_Reset_n,
1069  ------------------------------------------------------
1070  -- ECON / Edge / Connector Interface (SPD08-200)
1071  ------------------------------------------------------
1072  piECON_Eth_10Ge0_n => piECON_Eth_10Ge0_n,
1073  piECON_Eth_10Ge0_p => piECON_Eth_10Ge0_p,
1074  poECON_Eth_10Ge0_n => poECON_Eth_10Ge0_n,
1075  poECON_Eth_10Ge0_p => poECON_Eth_10Ge0_p,
1076  ------------------------------------------------------
1077  -- ROLE / Reset and Clock Interfaces
1078  ------------------------------------------------------
1079  poROL_156_25Clk => sSHL_156_25Clk,
1080  poROL_156_25Rst => sSHL_156_25Rst,
1081  ------------------------------------------------------
1082  -- ROLE / Nts / Udp / Tx Data Interfaces (.i.e ROLE-->SHELL)
1083  ------------------------------------------------------
1084  ---- Axi4-Stream UDP Data ---------------
1085  siROL_Nts_Udp_Data_tdata => ssROL_SHL_Nts_Udp_Data_tdata,
1086  siROL_Nts_Udp_Data_tkeep => ssROL_SHL_Nts_Udp_Data_tkeep,
1087  siROL_Nts_Udp_Data_tlast => ssROL_SHL_Nts_Udp_Data_tlast,
1088  siROL_Nts_Udp_Data_tvalid => ssROL_SHL_Nts_Udp_Data_tvalid,
1089  siROL_Nts_Udp_Data_tready => ssROL_SHL_Nts_Udp_Data_tready,
1090  ---- Axi4-Stream UDP Metadata -----------
1091  siROL_Nts_Udp_Meta_tdata => ssROL_SHL_Nts_Udp_Meta_tdata ,
1092  siROL_Nts_Udp_Meta_tvalid => ssROL_SHL_Nts_Udp_Meta_tvalid,
1093  siROL_Nts_Udp_Meta_tready => ssROL_SHL_Nts_Udp_Meta_tready,
1094  ---- Axis4Stream UDP Data Length ---------
1095  siROL_Nts_Udp_DLen_tdata => ssROL_SHL_Nts_Udp_DLen_tdata ,
1096  siROL_Nts_Udp_DLen_tvalid => ssROL_SHL_Nts_Udp_DLen_tvalid,
1097  siROL_Nts_Udp_DLen_tready => ssROL_SHL_Nts_Udp_DLen_tready,
1098  ------------------------------------------------------
1099  --ROLE / Nts / Udp / Rx Data Interfaces (.i.e SHELL-->ROLE)
1100  ------------------------------------------------------
1101  ---- Axi4-Stream UDP Data ---------------
1102  soROL_Nts_Udp_Data_tdata => ssSHL_ROL_Nts_Udp_Data_tdata,
1103  soROL_Nts_Udp_Data_tkeep => ssSHL_ROL_Nts_Udp_Data_tkeep,
1104  soROL_Nts_Udp_Data_tlast => ssSHL_ROL_Nts_Udp_Data_tlast,
1105  soROL_Nts_Udp_Data_tvalid => ssSHL_ROL_Nts_Udp_Data_tvalid,
1106  soROL_Nts_Udp_Data_tready => ssSHL_ROL_Nts_Udp_Data_tready,
1107  ---- Axi4-Stream UDP Metadata -----------
1108  soROL_Nts_Udp_Meta_tdata => ssSHL_ROL_Nts_Udp_Meta_tdata ,
1109  soROL_Nts_Udp_Meta_tvalid => ssSHL_ROL_Nts_Udp_Meta_tvalid,
1110  soROL_Nts_Udp_Meta_tready => ssSHL_ROL_Nts_Udp_Meta_tready,
1111  ---- Axi4-Stream UDP Data Len -----------
1112  soROL_Nts_Udp_DLen_tdata => ssSHL_ROL_Nts_Udp_DLen_tdata ,
1113  soROL_Nts_Udp_DLen_tvalid => ssSHL_ROL_Nts_Udp_DLen_tvalid,
1114  soROL_Nts_Udp_DLen_tready => ssSHL_ROL_Nts_Udp_DLen_tready,
1115  ------------------------------------------------------
1116  -- ROLE / Nts/ Udp / Rx Ctrl Interfaces (.i.e SHELL-->ROLE)
1117  ------------------------------------------------------
1118  ---- Axi4-Stream UDP Listen Request -----
1119  siROL_Nts_Udp_LsnReq_tdata => ssROL_SHL_Nts_Udp_LsnReq_tdata ,
1120  siROL_Nts_Udp_LsnReq_tvalid => ssROL_SHL_Nts_Udp_LsnReq_tvalid,
1121  siROL_Nts_Udp_LsnReq_tready => ssROL_SHL_Nts_Udp_LsnReq_tready,
1122  ---- Axi4-Stream UDP Listen Reply --------
1123  soROL_Nts_Udp_LsnRep_tdata => ssSHL_ROL_Nts_Udp_LsnRep_tdata ,
1124  soROL_Nts_Udp_LsnRep_tvalid => ssSHL_ROL_Nts_Udp_LsnRep_tvalid,
1125  soROL_Nts_Udp_LsnRep_tready => ssSHL_ROL_Nts_Udp_LsnRep_tready,
1126  ---- Axi4-Stream UDP Close Request ------
1127  siROL_Nts_Udp_ClsReq_tdata => ssROL_SHL_Nts_Udp_ClsReq_tdata ,
1128  siROL_Nts_Udp_ClsReq_tvalid => ssROL_SHL_Nts_Udp_ClsReq_tvalid,
1129  siROL_Nts_Udp_ClsReq_tready => ssROL_SHL_Nts_Udp_ClsReq_tready,
1130  ---- Axi4-Stream UDP Close Reply ---------
1131  soROL_Nts_Udp_ClsRep_tdata => ssSHL_ROL_Nts_Udp_ClsRep_tdata ,
1132  soROL_Nts_Udp_ClsRep_tvalid => ssSHL_ROL_Nts_Udp_ClsRep_tvalid,
1133  soROL_Nts_Udp_ClsRep_tready => ssSHL_ROL_Nts_Udp_ClsRep_tready,
1134  ------------------------------------------------------
1135  -- ROLE / Nts / Tcp / Tx Data Interfaces (.i.e ROLE-->SHELL)
1136  ------------------------------------------------------
1137  ---- Axi4-Stream TCP Data ---------------
1138  siROL_Nts_Tcp_Data_tdata => ssROL_SHL_Nts_Tcp_Data_tdata,
1139  siROL_Nts_Tcp_Data_tkeep => ssROL_SHL_Nts_Tcp_Data_tkeep,
1140  siROL_Nts_Tcp_Data_tlast => ssROL_SHL_Nts_Tcp_Data_tlast,
1141  siROL_Nts_Tcp_Data_tvalid => ssROL_SHL_Nts_Tcp_Data_tvalid,
1142  siROL_Nts_Tcp_Data_tready => ssROL_SHL_Nts_Tcp_Data_tready,
1143  ---- Axi4-Stream TCP Send Request -------
1144  siROL_Nts_Tcp_SndReq_tdata => ssROL_SHL_Nts_Tcp_SndReq_tdata,
1145  siROL_Nts_Tcp_SndReq_tvalid => ssROL_SHL_Nts_Tcp_SndReq_tvalid,
1146  siROL_Nts_Tcp_SndReq_tready => ssROL_SHL_Nts_Tcp_SndReq_tready,
1147  ---- Axi4-Stream TCP Send Reply ---------
1148  soROL_Nts_Tcp_SndRep_tdata => ssSHL_ROL_Nts_Tcp_SndRep_tdata,
1149  soROL_Nts_Tcp_SndRep_tvalid => ssSHL_ROL_Nts_Tcp_SndRep_tvalid,
1150  soROL_Nts_Tcp_SndRep_tready => ssSHL_ROL_Nts_Tcp_SndRep_tready,
1151  ------------------------------------------------------
1152  -- ROLE / Nts / Tcp / Rx Data Interfaces (.i.e SHELL-->ROLE)
1153  ------------------------------------------------------
1154  ---- Axi4-Stream TCP Data -----------------
1155  soROL_Nts_Tcp_Data_tdata => ssSHL_ROL_Nts_Tcp_Data_tdata,
1156  soROL_Nts_Tcp_Data_tkeep => ssSHL_ROL_Nts_Tcp_Data_tkeep,
1157  soROL_Nts_Tcp_Data_tlast => ssSHL_ROL_Nts_Tcp_Data_tlast,
1158  soROL_Nts_Tcp_Data_tvalid => ssSHL_ROL_Nts_Tcp_Data_tvalid,
1159  soROL_Nts_Tcp_Data_tready => ssSHL_ROL_Nts_Tcp_Data_tready,
1160  ---- Axi4-Stream TCP Metadata ------------
1161  soROL_Nts_Tcp_Meta_tdata => ssSHL_ROL_Nts_Tcp_Meta_tdata,
1162  soROL_Nts_Tcp_Meta_tvalid => ssSHL_ROL_Nts_Tcp_Meta_tvalid,
1163  soROL_Nts_Tcp_Meta_tready => ssSHL_ROL_Nts_Tcp_Meta_tready,
1164  ---- Axi4-Stream TCP Data Notification ---
1165  soROL_Nts_Tcp_Notif_tdata => ssSHL_ROL_Nts_Tcp_Notif_tdata,
1166  soROL_Nts_Tcp_Notif_tvalid => ssSHL_ROL_Nts_Tcp_Notif_tvalid,
1167  soROL_Nts_Tcp_Notif_tready => ssSHL_ROL_Nts_Tcp_Notif_tready,
1168  ---- Axi4-Stream TCP Data Request --------
1169  siROL_Nts_Tcp_DReq_tdata => ssROL_SHL_Nts_Tcp_DReq_tdata,
1170  siROL_Nts_Tcp_DReq_tvalid => ssROL_SHL_Nts_Tcp_DReq_tvalid,
1171  siROL_Nts_Tcp_DReq_tready => ssROL_SHL_Nts_Tcp_DReq_tready,
1172  ------------------------------------------------------
1173  -- ROLE / Nts / Tcp / TxP Ctlr Interfaces (.i.e ROLE-->SHELL)
1174  ------------------------------------------------------
1175  ---- Axi4-Stream TCP Open Session Request
1176  siROL_Nts_Tcp_OpnReq_tdata => ssROL_SHL_Nts_Tcp_OpnReq_tdata,
1177  siROL_Nts_Tcp_OpnReq_tvalid => ssROL_SHL_Nts_Tcp_OpnReq_tvalid,
1178  siROL_Nts_Tcp_OpnReq_tready => ssROL_SHL_Nts_Tcp_OpnReq_tready,
1179  ---- Axi4-Stream TCP Open Session Reply
1180  soROL_Nts_Tcp_OpnRep_tdata => ssSHL_ROL_Nts_Tcp_OpnRep_tdata,
1181  soROL_Nts_Tcp_OpnRep_tvalid => ssSHL_ROL_Nts_Tcp_OpnRep_tvalid,
1182  soROL_Nts_Tcp_OpnRep_tready => ssSHL_ROL_Nts_Tcp_OpnRep_tready,
1183  ---- Axi4-Stream TCP Close Request ------
1184  siROL_Nts_Tcp_ClsReq_tdata => ssROL_SHL_Nts_Tcp_ClsReq_tdata,
1185  siROL_Nts_Tcp_ClsReq_tvalid => ssROL_SHL_Nts_Tcp_ClsReq_tvalid,
1186  siROL_Nts_Tcp_ClsReq_tready => ssROL_SHL_Nts_Tcp_ClsReq_tready,
1187  ------------------------------------------------------
1188  -- ROLE / Nts / Tcp / Rx Ctlr Interfaces (.i.e SHELL-->ROLE)
1189  ------------------------------------------------------
1190  ---- Axi4-Stream TCP Listen Request ----
1191  siROL_Nts_Tcp_LsnReq_tdata => ssROL_SHL_Nts_Tcp_LsnReq_tdata,
1192  siROL_Nts_Tcp_LsnReq_tvalid => ssROL_SHL_Nts_Tcp_LsnReq_tvalid,
1193  siROL_Nts_Tcp_LsnReq_tready => ssROL_SHL_Nts_Tcp_LsnReq_tready,
1194  ---- Axi4-Stream TCP Listen Rep --------
1195  soROL_Nts_Tcp_LsnRep_tdata => ssSHL_ROL_Nts_Tcp_LsnRep_tdata,
1196  soROL_Nts_Tcp_LsnRep_tvalid => ssSHL_ROL_Nts_Tcp_LsnRep_tvalid,
1197  soROL_Nts_Tcp_LsnRep_tready => ssSHL_ROL_Nts_Tcp_LsnRep_tready,
1198  ------------------------------------------------------
1199  -- ROLE / Mem / Mp0 Interface
1200  ------------------------------------------------------
1201  -- Memory Port #0 / S2MM-AXIS ------------------
1202  ---- Stream Read Command ---------
1203  siROL_Mem_Mp0_RdCmd_tdata => ssROL_SHL_Mem_Mp0_RdCmd_tdata,
1204  siROL_Mem_Mp0_RdCmd_tvalid => ssROL_SHL_Mem_Mp0_RdCmd_tvalid,
1205  siROL_Mem_Mp0_RdCmd_tready => ssROL_SHL_Mem_Mp0_RdCmd_tready,
1206  ---- Stream Read Status ----------
1207  soROL_Mem_Mp0_RdSts_tdata => ssSHL_ROL_Mem_Mp0_RdSts_tdata,
1208  soROL_Mem_Mp0_RdSts_tvalid => ssSHL_ROL_Mem_Mp0_RdSts_tvalid,
1209  soROL_Mem_Mp0_RdSts_tready => ssSHL_ROL_Mem_Mp0_RdSts_tready,
1210  ---- Stream Data Output Channel --
1211  soROL_Mem_Mp0_Read_tdata => ssSHL_ROL_Mem_Mp0_Read_tdata,
1212  soROL_Mem_Mp0_Read_tkeep => ssSHL_ROL_Mem_Mp0_Read_tkeep,
1213  soROL_Mem_Mp0_Read_tlast => ssSHL_ROL_Mem_Mp0_Read_tlast,
1214  soROL_Mem_Mp0_Read_tvalid => ssSHL_ROL_Mem_Mp0_Read_tvalid,
1215  soROL_Mem_Mp0_Read_tready => ssSHL_ROL_Mem_Mp0_Read_tready,
1216  ---- Stream Write Command --------
1217  siROL_Mem_Mp0_WrCmd_tdata => ssROL_SHL_Mem_Mp0_WrCmd_tdata,
1218  siROL_Mem_Mp0_WrCmd_tvalid => ssROL_SHL_Mem_Mp0_WrCmd_tvalid,
1219  siROL_Mem_Mp0_WrCmd_tready => ssROL_SHL_Mem_Mp0_WrCmd_tready,
1220  ---- Stream Write Status ---------
1221  soROL_Mem_Mp0_WrSts_tvalid => ssSHL_ROL_Mem_Mp0_WrSts_tvalid,
1222  soROL_Mem_Mp0_WrSts_tdata => ssSHL_ROL_Mem_Mp0_WrSts_tdata,
1223  soROL_Mem_Mp0_WrSts_tready => ssSHL_ROL_Mem_Mp0_WrSts_tready,
1224  ---- Stream Data Input Channel ---
1225  siROL_Mem_Mp0_Write_tdata => ssROL_SHL_Mem_Mp0_Write_tdata,
1226  siROL_Mem_Mp0_Write_tkeep => ssROL_SHL_Mem_Mp0_Write_tkeep,
1227  siROL_Mem_Mp0_Write_tlast => ssROL_SHL_Mem_Mp0_Write_tlast,
1228  siROL_Mem_Mp0_Write_tvalid => ssROL_SHL_Mem_Mp0_Write_tvalid,
1229  siROL_Mem_Mp0_Write_tready => ssROL_SHL_Mem_Mp0_Write_tready,
1230  ------------------------------------------------------
1231  -- ROLE / Mem / Mp1 Interface
1232  ------------------------------------------------------
1233  miROL_Mem_Mp1_AWID => smROL_SHL_Mem_Mp1_AWID ,
1234  miROL_Mem_Mp1_AWADDR => smROL_SHL_Mem_Mp1_AWADDR ,
1235  miROL_Mem_Mp1_AWLEN => smROL_SHL_Mem_Mp1_AWLEN ,
1236  miROL_Mem_Mp1_AWSIZE => smROL_SHL_Mem_Mp1_AWSIZE ,
1237  miROL_Mem_Mp1_AWBURST => smROL_SHL_Mem_Mp1_AWBURST ,
1238  miROL_Mem_Mp1_AWVALID => smROL_SHL_Mem_Mp1_AWVALID ,
1239  miROL_Mem_Mp1_AWREADY => smROL_SHL_Mem_Mp1_AWREADY ,
1240  miROL_Mem_Mp1_WDATA => smROL_SHL_Mem_Mp1_WDATA ,
1241  miROL_Mem_Mp1_WSTRB => smROL_SHL_Mem_Mp1_WSTRB ,
1242  miROL_Mem_Mp1_WLAST => smROL_SHL_Mem_Mp1_WLAST ,
1243  miROL_Mem_Mp1_WVALID => smROL_SHL_Mem_Mp1_WVALID ,
1244  miROL_Mem_Mp1_WREADY => smROL_SHL_Mem_Mp1_WREADY ,
1245  miROL_Mem_Mp1_BID => smROL_SHL_Mem_Mp1_BID ,
1246  miROL_Mem_Mp1_BRESP => smROL_SHL_Mem_Mp1_BRESP ,
1247  miROL_Mem_Mp1_BVALID => smROL_SHL_Mem_Mp1_BVALID ,
1248  miROL_Mem_Mp1_BREADY => smROL_SHL_Mem_Mp1_BREADY ,
1249  miROL_Mem_Mp1_ARID => smROL_SHL_Mem_Mp1_ARID ,
1250  miROL_Mem_Mp1_ARADDR => smROL_SHL_Mem_Mp1_ARADDR ,
1251  miROL_Mem_Mp1_ARLEN => smROL_SHL_Mem_Mp1_ARLEN ,
1252  miROL_Mem_Mp1_ARSIZE => smROL_SHL_Mem_Mp1_ARSIZE ,
1253  miROL_Mem_Mp1_ARBURST => smROL_SHL_Mem_Mp1_ARBURST ,
1254  miROL_Mem_Mp1_ARVALID => smROL_SHL_Mem_Mp1_ARVALID ,
1255  miROL_Mem_Mp1_ARREADY => smROL_SHL_Mem_Mp1_ARREADY ,
1256  miROL_Mem_Mp1_RID => smROL_SHL_Mem_Mp1_RID ,
1257  miROL_Mem_Mp1_RDATA => smROL_SHL_Mem_Mp1_RDATA ,
1258  miROL_Mem_Mp1_RRESP => smROL_SHL_Mem_Mp1_RRESP ,
1259  miROL_Mem_Mp1_RLAST => smROL_SHL_Mem_Mp1_RLAST ,
1260  miROL_Mem_Mp1_RVALID => smROL_SHL_Mem_Mp1_RVALID ,
1261  miROL_Mem_Mp1_RREADY => smROL_SHL_Mem_Mp1_RREADY ,
1262  ------------------------------------------------------
1263  -- ROLE / Mmio / AppFlash Interface
1264  ------------------------------------------------------
1265  ---- [PHY_RESET] -----------------
1266  poROL_Mmio_Ly7Rst => (sSHL_ROL_Mmio_Ly7Rst),
1267  ---- [PHY_ENABLE] --------------
1268  poROL_Mmio_Ly7En => (sSHL_ROL_Mmio_Ly7En),
1269  ---- [DIAG_CTRL_1] ---------------
1270  poROL_Mmio_Mc1_MemTestCtrl => sSHL_ROL_Mmio_Mc1_MemTestCtrl,
1271  ---- [DIAG_STAT_1] ---------------
1272  piROL_Mmio_Mc1_MemTestStat => sROL_SHL_Mmio_Mc1_MemTestStat,
1273  ---- [DIAG_CTRL_2] ---------------
1274  poROL_Mmio_UdpEchoCtrl => sSHL_ROL_Mmio_UdpEchoCtrl,
1275  poROL_Mmio_UdpPostDgmEn => sSHL_ROL_Mmio_UdpPostDgmEn,
1276  poROL_Mmio_UdpCaptDgmEn => sSHL_ROL_Mmio_UdpCaptDgmEn,
1277  poROL_Mmio_TcpEchoCtrl => sSHL_ROL_Mmio_TcpEchoCtrl,
1278  poROL_Mmio_TcpPostSegEn => sSHL_ROL_Mmio_TcpPostSegEn,
1279  poROL_Mmio_TcpCaptSegEn => sSHL_ROL_Mmio_TcpCaptSegEn,
1280  ---- [APP_RDROL] -----------------
1281  piROL_Mmio_RdReg => sROL_SHL_Mmio_RdReg,
1282  ---- [APP_WRROL] -----------------
1283  poROL_Mmio_WrReg => sSHL_ROL_Mmio_WrReg
1284  ); -- End-of: Shell_Kale instantiation
1285 
1286  --==========================================================================
1287  -- INST: ROLE FOR FMKU60
1288  --==========================================================================
1289 
1290  ROLE : Role_Kale
1291  generic map (
1292  gVivadoVersion => gVivadoVersion
1293  )
1294  port map (
1295  ------------------------------------------------------
1296  -- SHELL / Global Input Clock and Reset Interface
1297  ------------------------------------------------------
1298  piSHL_156_25Clk => sSHL_156_25Clk,
1299  piSHL_156_25Rst => sSHL_156_25Rst,
1300  ------------------------------------------------------
1301  -- SHELL / Nts / Udp / Tx Data Interfaces (.i.e SHELL-->ROLE)
1302  ------------------------------------------------------
1303  ---- Axi4-Stream UDP Data ----------------
1304  siSHL_Nts_Udp_Data_tdata => ssSHL_ROL_Nts_Udp_Data_tdata ,
1305  siSHL_Nts_Udp_Data_tkeep => ssSHL_ROL_Nts_Udp_Data_tkeep ,
1306  siSHL_Nts_Udp_Data_tlast => ssSHL_ROL_Nts_Udp_Data_tlast ,
1307  siSHL_Nts_Udp_Data_tvalid => ssSHL_ROL_Nts_Udp_Data_tvalid,
1308  siSHL_Nts_Udp_Data_tready => ssSHL_ROL_Nts_Udp_Data_tready,
1309  ---- Axi4-Stream UDP Metadata ------------
1310  siSHL_Nts_Udp_Meta_tdata => ssSHL_ROL_Nts_Udp_Meta_tdata ,
1311  siSHL_Nts_Udp_Meta_tvalid => ssSHL_ROL_Nts_Udp_Meta_tvalid,
1312  siSHL_Nts_Udp_Meta_tready => ssSHL_ROL_Nts_Udp_Meta_tready,
1313  ---- Axi4-Stream UDP Metadata ------------
1314  siSHL_Nts_Udp_DLen_tdata => ssSHL_ROL_Nts_Udp_DLen_tdata ,
1315  siSHL_Nts_Udp_DLen_tvalid => ssSHL_ROL_Nts_Udp_DLen_tvalid,
1316  siSHL_Nts_Udp_DLen_tready => ssSHL_ROL_Nts_Udp_DLen_tready,
1317  -----------------------------------------------------
1318  -- SHELL / Nts / Udp / Rx Data Interfaces (.i.e ROLE-->SHELL)
1319  ------------------------------------------------------
1320  ---- Axi4-Stream UDP Data ---------------
1321  soSHL_Nts_Udp_Data_tdata => ssROL_SHL_Nts_Udp_Data_tdata ,
1322  soSHL_Nts_Udp_Data_tkeep => ssROL_SHL_Nts_Udp_Data_tkeep ,
1323  soSHL_Nts_Udp_Data_tlast => ssROL_SHL_Nts_Udp_Data_tlast ,
1324  soSHL_Nts_Udp_Data_tvalid => ssROL_SHL_Nts_Udp_Data_tvalid,
1325  soSHL_Nts_Udp_Data_tready => ssROL_SHL_Nts_Udp_Data_tready,
1326  ---- Axi4-Stream UDP Meta ---------------
1327  soSHL_Nts_Udp_Meta_tdata => ssROL_SHL_Nts_Udp_Meta_tdata ,
1328  soSHL_Nts_Udp_Meta_tvalid => ssROL_SHL_Nts_Udp_Meta_tvalid,
1329  soSHL_Nts_Udp_Meta_tready => ssROL_SHL_Nts_Udp_Meta_tready,
1330  ---- Axi4-Stream UDP Data Length ---------
1331  soSHL_Nts_Udp_DLen_tdata => ssROL_SHL_Nts_Udp_DLen_tdata ,
1332  soSHL_Nts_Udp_DLen_tvalid => ssROL_SHL_Nts_Udp_DLen_tvalid,
1333  soSHL_Nts_Udp_DLen_tready => ssROL_SHL_Nts_Udp_DLen_tready,
1334  ------------------------------------------------------
1335  -- SHELL / Nts/ Udp / Rx Ctrl Interfaces (.i.e ROLE-->SHELL)
1336  ------------------------------------------------------
1337  ---- Axi4-Stream UDP Listen Request -----
1338  soSHL_Nts_Udp_LsnReq_tdata => ssROL_SHL_Nts_Udp_LsnReq_tdata ,
1339  soSHL_Nts_Udp_LsnReq_tvalid => ssROL_SHL_Nts_Udp_LsnReq_tvalid,
1340  soSHL_Nts_Udp_LsnReq_tready => ssROL_SHL_Nts_Udp_LsnReq_tready,
1341  ---- Axi4-Stream UDP Listen Reply --------
1342  siSHL_Nts_Udp_LsnRep_tdata => ssSHL_ROL_Nts_Udp_LsnRep_tdata ,
1343  siSHL_Nts_Udp_LsnRep_tvalid => ssSHL_ROL_Nts_Udp_LsnRep_tvalid,
1344  siSHL_Nts_Udp_LsnRep_tready => ssSHL_ROL_Nts_Udp_LsnRep_tready,
1345  ---- Axi4-Stream UDP Close Request ------
1346  soSHL_Nts_Udp_ClsReq_tdata => ssROL_SHL_Nts_Udp_ClsReq_tdata ,
1347  soSHL_Nts_Udp_ClsReq_tvalid => ssROL_SHL_Nts_Udp_ClsReq_tvalid,
1348  soSHL_Nts_Udp_ClsReq_tready => ssROL_SHL_Nts_Udp_ClsReq_tready,
1349  ---- Axi4-Stream UDP Close Reply ---------
1350  siSHL_Nts_Udp_ClsRep_tdata => ssSHL_ROL_Nts_Udp_ClsRep_tdata ,
1351  siSHL_Nts_Udp_ClsRep_tvalid => ssSHL_ROL_Nts_Udp_ClsRep_tvalid,
1352  siSHL_Nts_Udp_ClsRep_tready => ssSHL_ROL_Nts_Udp_ClsRep_tready,
1353  ------------------------------------------------------
1354  -- SHELL / Nts / Tcp / Tx Data Interfaces (.i.e ROLE-->SHELL)
1355  ------------------------------------------------------
1356  ---- Axi4-Stream TCP Data ---------------
1357  soSHL_Nts_Tcp_Data_tdata => ssROL_SHL_Nts_Tcp_Data_tdata ,
1358  soSHL_Nts_Tcp_Data_tkeep => ssROL_SHL_Nts_Tcp_Data_tkeep ,
1359  soSHL_Nts_Tcp_Data_tlast => ssROL_SHL_Nts_Tcp_Data_tlast ,
1360  soSHL_Nts_Tcp_Data_tvalid => ssROL_SHL_Nts_Tcp_Data_tvalid,
1361  soSHL_Nts_Tcp_Data_tready => ssROL_SHL_Nts_Tcp_Data_tready,
1362  ---- Axi4-Stream TCP Send Request --------
1363  soSHL_Nts_Tcp_SndReq_tdata => ssROL_SHL_Nts_Tcp_SndReq_tdata ,
1364  soSHL_Nts_Tcp_SndReq_tvalid => ssROL_SHL_Nts_Tcp_SndReq_tvalid,
1365  soSHL_Nts_Tcp_SndReq_tready => ssROL_SHL_Nts_Tcp_SndReq_tready,
1366  ---- Axi4-Stream TCP Send Reply ---------
1367  siSHL_Nts_Tcp_SndRep_tdata => ssSHL_ROL_Nts_Tcp_SndRep_tdata ,
1368  siSHL_Nts_Tcp_SndRep_tvalid => ssSHL_ROL_Nts_Tcp_SndRep_tvalid,
1369  siSHL_Nts_Tcp_SndRep_tready => ssSHL_ROL_Nts_Tcp_SndRep_tready,
1370  --------------------------------------------------------
1371  -- SHELL / Nts / Tcp / Rx Data Interfaces (.i.e SHELL-->ROLE)
1372  --------------------------------------------------------
1373  ---- Axi4-Stream TCP Data -----------------
1374  siSHL_Nts_Tcp_Data_tdata => ssSHL_ROL_Nts_Tcp_Data_tdata,
1375  siSHL_Nts_Tcp_Data_tkeep => ssSHL_ROL_Nts_Tcp_Data_tkeep,
1376  siSHL_Nts_Tcp_Data_tlast => ssSHL_ROL_Nts_Tcp_Data_tlast,
1377  siSHL_Nts_Tcp_Data_tvalid => ssSHL_ROL_Nts_Tcp_Data_tvalid,
1378  siSHL_Nts_Tcp_Data_tready => ssSHL_ROL_Nts_Tcp_Data_tready,
1379  ---- Axi4-Stream TCP Metadata ------------
1380  siSHL_Nts_Tcp_Meta_tdata => ssSHL_ROL_Nts_Tcp_Meta_tdata,
1381  siSHL_Nts_Tcp_Meta_tvalid => ssSHL_ROL_Nts_Tcp_Meta_tvalid,
1382  siSHL_Nts_Tcp_Meta_tready => ssSHL_ROL_Nts_Tcp_Meta_tready,
1383  ---- Axi4-Stream TCP Data Notification ---
1384  siSHL_Nts_Tcp_Notif_tdata => ssSHL_ROL_Nts_Tcp_Notif_tdata,
1385  siSHL_Nts_Tcp_Notif_tvalid => ssSHL_ROL_Nts_Tcp_Notif_tvalid,
1386  siSHL_Nts_Tcp_Notif_tready => ssSHL_ROL_Nts_Tcp_Notif_tready,
1387  ---- Axi4-Stream TCP Data Request --------
1388  soSHL_Nts_Tcp_DReq_tdata => ssROL_SHL_Nts_Tcp_DReq_tdata,
1389  soSHL_Nts_Tcp_DReq_tvalid => ssROL_SHL_Nts_Tcp_DReq_tvalid,
1390  soSHL_Nts_Tcp_DReq_tready => ssROL_SHL_Nts_Tcp_DReq_tready,
1391  ------------------------------------------------------
1392  -- SHELL / Nts / Tcp / TxP Ctlr Interfaces (.i.e ROLE-->SHELL)
1393  ------------------------------------------------------
1394  ---- Axi4-Stream TCP Open Session Request
1395  ---- Stream TCP Open Session Request
1396  soSHL_Nts_Tcp_OpnReq_tdata => ssROL_SHL_Nts_Tcp_OpnReq_tdata,
1397  soSHL_Nts_Tcp_OpnReq_tvalid => ssROL_SHL_Nts_Tcp_OpnReq_tvalid,
1398  soSHL_Nts_Tcp_OpnReq_tready => ssROL_SHL_Nts_Tcp_OpnReq_tready,
1399  ---- Axi4-Stream TCP Open Session Reply
1400  siSHL_Nts_Tcp_OpnRep_tdata => ssSHL_ROL_Nts_Tcp_OpnRep_tdata,
1401  siSHL_Nts_Tcp_OpnRep_tvalid => ssSHL_ROL_Nts_Tcp_OpnRep_tvalid,
1402  siSHL_Nts_Tcp_OpnRep_tready => ssSHL_ROL_Nts_Tcp_OpnRep_tready,
1403  ---- Axi4-Stream TCP Close Request ------
1404  soSHL_Nts_Tcp_ClsReq_tdata => ssROL_SHL_Nts_Tcp_ClsReq_tdata,
1405  soSHL_Nts_Tcp_ClsReq_tvalid => ssROL_SHL_Nts_Tcp_ClsReq_tvalid,
1406  soSHL_Nts_Tcp_ClsReq_tready => ssROL_SHL_Nts_Tcp_ClsReq_tready,
1407  ------------------------------------------------------
1408  -- SHELL / Nts / Tcp / Rx Ctlr Interfaces (.i.e SHELL-->ROLE)
1409  ------------------------------------------------------
1410  ---- Axi4-Stream TCP Listen Request ----
1411  soSHL_Nts_Tcp_LsnReq_tdata => ssROL_SHL_Nts_Tcp_LsnReq_tdata,
1412  soSHL_Nts_Tcp_LsnReq_tvalid => ssROL_SHL_Nts_Tcp_LsnReq_tvalid,
1413  soSHL_Nts_Tcp_LsnReq_tready => ssROL_SHL_Nts_Tcp_LsnReq_tready,
1414  ----- Axi4-Stream TCP Listen Rep --------
1415  siSHL_Nts_Tcp_LsnRep_tdata => ssSHL_ROL_Nts_Tcp_LsnRep_tdata,
1416  siSHL_Nts_Tcp_LsnRep_tvalid => ssSHL_ROL_Nts_Tcp_LsnRep_tvalid,
1417  siSHL_Nts_Tcp_LsnRep_tready => ssSHL_ROL_Nts_Tcp_LsnRep_tready,
1418  ------------------------------------------------------
1419  -- SHELL / Mem / Mp0 Interface
1420  ------------------------------------------------------
1421  -- Memory Port #0 / S2MM-AXIS ------------------
1422  ---- Stream Read Command ---------
1423  soSHL_Mem_Mp0_RdCmd_tdata => ssROL_SHL_Mem_Mp0_RdCmd_tdata,
1424  soSHL_Mem_Mp0_RdCmd_tvalid => ssROL_SHL_Mem_Mp0_RdCmd_tvalid,
1425  soSHL_Mem_Mp0_RdCmd_tready => ssROL_SHL_Mem_Mp0_RdCmd_tready,
1426  ---- Stream Read Status ----------
1427  siSHL_Mem_Mp0_RdSts_tdata => ssSHL_ROL_Mem_Mp0_RdSts_tdata,
1428  siSHL_Mem_Mp0_RdSts_tvalid => ssSHL_ROL_Mem_Mp0_RdSts_tvalid,
1429  siSHL_Mem_Mp0_RdSts_tready => ssSHL_ROL_Mem_Mp0_RdSts_tready,
1430  ---- Stream Data Input Channel ---
1431  siSHL_Mem_Mp0_Read_tdata => ssSHL_ROL_Mem_Mp0_Read_tdata,
1432  siSHL_Mem_Mp0_Read_tkeep => ssSHL_ROL_Mem_Mp0_Read_tkeep,
1433  siSHL_Mem_Mp0_Read_tlast => ssSHL_ROL_Mem_Mp0_Read_tlast,
1434  siSHL_Mem_Mp0_Read_tvalid => ssSHL_ROL_Mem_Mp0_Read_tvalid,
1435  siSHL_Mem_Mp0_Read_tready => ssSHL_ROL_Mem_Mp0_Read_tready,
1436  ---- Stream Write Command --------
1437  soSHL_Mem_Mp0_WrCmd_tdata => ssROL_SHL_Mem_Mp0_WrCmd_tdata,
1438  soSHL_Mem_Mp0_WrCmd_tvalid => ssROL_SHL_Mem_Mp0_WrCmd_tvalid,
1439  soSHL_Mem_Mp0_WrCmd_tready => ssROL_SHL_Mem_Mp0_WrCmd_tready,
1440  ---- Stream Write Status ---------
1441  siSHL_Mem_Mp0_WrSts_tvalid => ssSHL_ROL_Mem_Mp0_WrSts_tvalid,
1442  siSHL_Mem_Mp0_WrSts_tdata => ssSHL_ROL_Mem_Mp0_WrSts_tdata,
1443  siSHL_Mem_Mp0_WrSts_tready => ssSHL_ROL_Mem_Mp0_WrSts_tready,
1444  ---- Stream Data Output Channel --
1445  soSHL_Mem_Mp0_Write_tdata => ssROL_SHL_Mem_Mp0_Write_tdata,
1446  soSHL_Mem_Mp0_Write_tkeep => ssROL_SHL_Mem_Mp0_Write_tkeep,
1447  soSHL_Mem_Mp0_Write_tlast => ssROL_SHL_Mem_Mp0_Write_tlast,
1448  soSHL_Mem_Mp0_Write_tvalid => ssROL_SHL_Mem_Mp0_Write_tvalid,
1449  soSHL_Mem_Mp0_Write_tready => ssROL_SHL_Mem_Mp0_Write_tready,
1450  ------------------------------------------------------
1451  -- SHELL / Role / Mem / Mp1 Interface
1452  ------------------------------------------------------
1453  moSHL_Mem_Mp1_AWID => smROL_SHL_Mem_Mp1_AWID ,
1454  moSHL_Mem_Mp1_AWADDR => smROL_SHL_Mem_Mp1_AWADDR ,
1455  moSHL_Mem_Mp1_AWLEN => smROL_SHL_Mem_Mp1_AWLEN ,
1456  moSHL_Mem_Mp1_AWSIZE => smROL_SHL_Mem_Mp1_AWSIZE ,
1457  moSHL_Mem_Mp1_AWBURST => smROL_SHL_Mem_Mp1_AWBURST ,
1458  moSHL_Mem_Mp1_AWVALID => smROL_SHL_Mem_Mp1_AWVALID ,
1459  moSHL_Mem_Mp1_AWREADY => smROL_SHL_Mem_Mp1_AWREADY ,
1460  moSHL_Mem_Mp1_WDATA => smROL_SHL_Mem_Mp1_WDATA ,
1461  moSHL_Mem_Mp1_WSTRB => smROL_SHL_Mem_Mp1_WSTRB ,
1462  moSHL_Mem_Mp1_WLAST => smROL_SHL_Mem_Mp1_WLAST ,
1463  moSHL_Mem_Mp1_WVALID => smROL_SHL_Mem_Mp1_WVALID ,
1464  moSHL_Mem_Mp1_WREADY => smROL_SHL_Mem_Mp1_WREADY ,
1465  moSHL_Mem_Mp1_BID => smROL_SHL_Mem_Mp1_BID ,
1466  moSHL_Mem_Mp1_BRESP => smROL_SHL_Mem_Mp1_BRESP ,
1467  moSHL_Mem_Mp1_BVALID => smROL_SHL_Mem_Mp1_BVALID ,
1468  moSHL_Mem_Mp1_BREADY => smROL_SHL_Mem_Mp1_BREADY ,
1469  moSHL_Mem_Mp1_ARID => smROL_SHL_Mem_Mp1_ARID ,
1470  moSHL_Mem_Mp1_ARADDR => smROL_SHL_Mem_Mp1_ARADDR ,
1471  moSHL_Mem_Mp1_ARLEN => smROL_SHL_Mem_Mp1_ARLEN ,
1472  moSHL_Mem_Mp1_ARSIZE => smROL_SHL_Mem_Mp1_ARSIZE ,
1473  moSHL_Mem_Mp1_ARBURST => smROL_SHL_Mem_Mp1_ARBURST ,
1474  moSHL_Mem_Mp1_ARVALID => smROL_SHL_Mem_Mp1_ARVALID ,
1475  moSHL_Mem_Mp1_ARREADY => smROL_SHL_Mem_Mp1_ARREADY ,
1476  moSHL_Mem_Mp1_RID => smROL_SHL_Mem_Mp1_RID ,
1477  moSHL_Mem_Mp1_RDATA => smROL_SHL_Mem_Mp1_RDATA ,
1478  moSHL_Mem_Mp1_RRESP => smROL_SHL_Mem_Mp1_RRESP ,
1479  moSHL_Mem_Mp1_RLAST => smROL_SHL_Mem_Mp1_RLAST ,
1480  moSHL_Mem_Mp1_RVALID => smROL_SHL_Mem_Mp1_RVALID ,
1481  moSHL_Mem_Mp1_RREADY => smROL_SHL_Mem_Mp1_RREADY ,
1482  ------------------------------------------------------
1483  -- SHELL / Mmio / AppFlash Interface
1484  ------------------------------------------------------
1485  ---- [PHY_RESET] -----------------
1486  piSHL_Mmio_Ly7Rst => sSHL_ROL_Mmio_Ly7Rst,
1487  ---- [PHY_ENABLE] ----------------
1488  piSHL_Mmio_Ly7En => sSHL_ROL_Mmio_Ly7En,
1489  ---- [DIAG_CTRL_1] ---------------
1490  piSHL_Mmio_Mc1_MemTestCtrl => sSHL_ROL_Mmio_Mc1_MemTestCtrl,
1491  ---- [DIAG_STAT_1] ---------------
1492  poSHL_Mmio_Mc1_MemTestStat => sROL_SHL_Mmio_Mc1_MemTestStat,
1493  ---- [DIAG_CTRL_2] ---------------
1494  --[NOT_USED] piSHL_Mmio_UdpEchoCtrl => sSHL_ROL_Mmio_UdpEchoCtrl,
1495  --[NOT_USED] piSHL_Mmio_UdpPostDgmEn => sSHL_ROL_Mmio_UdpPostDgmEn,
1496  --[NOT_USED] piSHL_Mmio_UdpCaptDgmEn => sSHL_ROL_Mmio_UdpCaptDgmEn,
1497  --[NOT_USED] piSHL_Mmio_TcpEchoCtrl => sSHL_ROL_Mmio_TcpEchoCtrl,
1498  --[NOT_USED] piSHL_Mmio_TcpPostSegEn => sSHL_ROL_Mmio_TcpPostSegEn,
1499  --[NOT_USED] piSHL_Mmio_TcpCaptSegEn => sSHL_ROL_Mmio_TcpCaptSegEn,
1500  ---- [APP_RDROL] -----------------
1501  poSHL_Mmio_RdReg => sROL_SHL_Mmio_RdReg,
1502  --- [APP_WRROL] ------------------
1503  piSHL_Mmio_WrReg => sSHL_ROL_Mmio_WrReg,
1504  ------------------------------------------------------
1505  ---- TOP : Secondary Clock (Asynchronous)
1506  ------------------------------------------------------
1507  piTOP_250_00Clk => sTOP_250_00Clk -- Freerunning
1508  ); -- End-of: Role instantiation
1509 
1510 end structural;
1511 
Role_Kale
Definition: Role.vhdl:74
Role_Kale.soSHL_Mem_Mp0_RdCmd_tvalid
out soSHL_Mem_Mp0_RdCmd_tvalidstd_ulogic
Definition: Role.vhdl:179
Role_Kale.soSHL_Nts_Udp_DLen_tready
in soSHL_Nts_Udp_DLen_treadystd_ulogic
Definition: Role.vhdl:94
Role_Kale.siSHL_Nts_Tcp_Data_tkeep
in siSHL_Nts_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:124
Role_Kale.siSHL_Nts_Tcp_Notif_tvalid
in siSHL_Nts_Tcp_Notif_tvalidstd_ulogic
Definition: Role.vhdl:136
Role_Kale.siSHL_Nts_Tcp_SndRep_tdata
in siSHL_Nts_Tcp_SndRep_tdatastd_ulogic_vector(55 downto 0)
Definition: Role.vhdl:128
Role_Kale.siSHL_Nts_Tcp_LsnRep_tdata
in siSHL_Nts_Tcp_LsnRep_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:175
Role_Kale.siSHL_Mem_Mp0_Read_tlast
in siSHL_Mem_Mp0_Read_tlaststd_ulogic
Definition: Role.vhdl:188
Role_Kale.soSHL_Nts_Tcp_Data_tvalid
out soSHL_Nts_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:107
Role_Kale.moSHL_Mem_Mp1_RREADY
out moSHL_Mem_Mp1_RREADYstd_ulogic
Definition: Role.vhdl:246
Role_Kale.moSHL_Mem_Mp1_WREADY
in moSHL_Mem_Mp1_WREADYstd_ulogic
Definition: Role.vhdl:226
Role_Kale.siSHL_Nts_Tcp_OpnRep_tdata
in siSHL_Nts_Tcp_OpnRep_tdatastd_ulogic_vector(23 downto 0)
Definition: Role.vhdl:152
Role_Kale.siSHL_Mem_Mp0_WrSts_tvalid
in siSHL_Mem_Mp0_WrSts_tvalidstd_ulogic
Definition: Role.vhdl:197
Role_Kale.poSHL_Mmio_RdReg
out poSHL_Mmio_RdRegstd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:258
Role_Kale.piSHL_156_25Rst
in piSHL_156_25Rststd_ulogic
Definition: Role.vhdl:81
Role_Kale.siSHL_Nts_Udp_Data_tlast
in siSHL_Nts_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:89
Role_Kale.siSHL_Mem_Mp0_Read_tkeep
in siSHL_Mem_Mp0_Read_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:187
Role_Kale.soSHL_Nts_Tcp_SndReq_tvalid
out soSHL_Nts_Tcp_SndReq_tvalidstd_ulogic
Definition: Role.vhdl:125
Role_Kale.moSHL_Mem_Mp1_AWBURST
out moSHL_Mem_Mp1_AWBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:218
Role_Kale.soSHL_Nts_Tcp_DReq_tvalid
out soSHL_Nts_Tcp_DReq_tvalidstd_ulogic
Definition: Role.vhdl:140
Role_Kale.moSHL_Mem_Mp1_RID
in moSHL_Mem_Mp1_RIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:241
Role_Kale.soSHL_Nts_Tcp_OpnReq_tready
in soSHL_Nts_Tcp_OpnReq_treadystd_ulogic
Definition: Role.vhdl:150
Role_Kale.siSHL_Mem_Mp0_RdSts_tvalid
in siSHL_Mem_Mp0_RdSts_tvalidstd_ulogic
Definition: Role.vhdl:183
Role_Kale.soSHL_Mem_Mp0_WrCmd_tvalid
out soSHL_Mem_Mp0_WrCmd_tvalidstd_ulogic
Definition: Role.vhdl:193
Role_Kale.piSHL_Mmio_Ly7En
in piSHL_Mmio_Ly7Enstd_ulogic
Definition: Role.vhdl:245
Role_Kale.soSHL_Nts_Udp_LsnReq_tdata
out soSHL_Nts_Udp_LsnReq_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:99
Role_Kale.soSHL_Nts_Tcp_Data_tlast
out soSHL_Nts_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:106
Role_Kale.moSHL_Mem_Mp1_WVALID
out moSHL_Mem_Mp1_WVALIDstd_ulogic
Definition: Role.vhdl:225
Role_Kale.siSHL_Mem_Mp0_Read_tready
out siSHL_Mem_Mp0_Read_treadystd_ulogic
Definition: Role.vhdl:190
Role_Kale.soSHL_Nts_Udp_DLen_tvalid
out soSHL_Nts_Udp_DLen_tvalidstd_ulogic
Definition: Role.vhdl:93
Role_Kale.soSHL_Nts_Tcp_ClsReq_tdata
out soSHL_Nts_Tcp_ClsReq_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:156
Role_Kale.soSHL_Nts_Udp_Meta_tdata
out soSHL_Nts_Udp_Meta_tdatastd_ulogic_vector(95 downto 0)
Definition: Role.vhdl:88
Role_Kale.moSHL_Mem_Mp1_BREADY
out moSHL_Mem_Mp1_BREADYstd_ulogic
Definition: Role.vhdl:231
Role_Kale.siSHL_Nts_Udp_Data_tready
out siSHL_Nts_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:91
Role_Kale.siSHL_Nts_Udp_ClsRep_tvalid
in siSHL_Nts_Udp_ClsRep_tvalidstd_ulogic
Definition: Role.vhdl:112
Role_Kale.siSHL_Nts_Udp_ClsRep_tdata
in siSHL_Nts_Udp_ClsRep_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:111
Role_Kale.siSHL_Mem_Mp0_WrSts_tdata
in siSHL_Mem_Mp0_WrSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:196
Role_Kale.soSHL_Nts_Tcp_DReq_tready
in soSHL_Nts_Tcp_DReq_treadystd_ulogic
Definition: Role.vhdl:141
Role_Kale.piSHL_156_25Clk
in piSHL_156_25Clkstd_ulogic
Definition: Role.vhdl:80
Role_Kale.soSHL_Nts_Tcp_LsnReq_tvalid
out soSHL_Nts_Tcp_LsnReq_tvalidstd_ulogic
Definition: Role.vhdl:166
Role_Kale.siSHL_Nts_Tcp_Meta_tready
out siSHL_Nts_Tcp_Meta_treadystd_ulogic
Definition: Role.vhdl:133
Role_Kale.siSHL_Nts_Udp_Meta_tdata
in siSHL_Nts_Udp_Meta_tdatastd_ulogic_vector(95 downto 0)
Definition: Role.vhdl:71
Role_Kale.moSHL_Mem_Mp1_AWREADY
in moSHL_Mem_Mp1_AWREADYstd_ulogic
Definition: Role.vhdl:220
Role_Kale.moSHL_Mem_Mp1_RRESP
in moSHL_Mem_Mp1_RRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:243
Role_Kale.soSHL_Nts_Udp_Data_tvalid
out soSHL_Nts_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:96
Role_Kale.siSHL_Nts_Tcp_Data_tready
out siSHL_Nts_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:127
Role_Kale.siSHL_Nts_Udp_Data_tdata
in siSHL_Nts_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:87
Role_Kale.poSHL_Mmio_Mc1_MemTestStat
out poSHL_Mmio_Mc1_MemTestStatstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:249
Role_Kale.soSHL_Nts_Tcp_Data_tready
in soSHL_Nts_Tcp_Data_treadystd_ulogic
Definition: Role.vhdl:108
Role_Kale.soSHL_Mem_Mp0_Write_tready
in soSHL_Mem_Mp0_Write_treadystd_ulogic
Definition: Role.vhdl:204
Role_Kale.moSHL_Mem_Mp1_BID
in moSHL_Mem_Mp1_BIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:228
Role_Kale.soSHL_Nts_Udp_ClsReq_tready
in soSHL_Nts_Udp_ClsReq_treadystd_ulogic
Definition: Role.vhdl:109
Role_Kale.siSHL_Nts_Tcp_Notif_tready
out siSHL_Nts_Tcp_Notif_treadystd_ulogic
Definition: Role.vhdl:137
Role_Kale.siSHL_Nts_Tcp_OpnRep_tvalid
in siSHL_Nts_Tcp_OpnRep_tvalidstd_ulogic
Definition: Role.vhdl:153
Role_Kale.soSHL_Mem_Mp0_WrCmd_tdata
out soSHL_Mem_Mp0_WrCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:192
Role_Kale.siSHL_Nts_Tcp_OpnRep_tready
out siSHL_Nts_Tcp_OpnRep_treadystd_ulogic
Definition: Role.vhdl:154
Role_Kale.siSHL_Nts_Tcp_Data_tlast
in siSHL_Nts_Tcp_Data_tlaststd_ulogic
Definition: Role.vhdl:125
Role_Kale.siSHL_Nts_Udp_Meta_tvalid
in siSHL_Nts_Udp_Meta_tvalidstd_ulogic
Definition: Role.vhdl:72
Role_Kale.soSHL_Nts_Udp_Data_tready
in soSHL_Nts_Udp_Data_treadystd_ulogic
Definition: Role.vhdl:97
Role_Kale.moSHL_Mem_Mp1_BRESP
in moSHL_Mem_Mp1_BRESPstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:229
Role_Kale.siSHL_Nts_Udp_DLen_tdata
in siSHL_Nts_Udp_DLen_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:75
Role_Kale.soSHL_Mem_Mp0_Write_tdata
out soSHL_Mem_Mp0_Write_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:200
Role_Kale.siSHL_Mem_Mp0_RdSts_tdata
in siSHL_Mem_Mp0_RdSts_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:182
Role_Kale.soSHL_Nts_Tcp_LsnReq_tdata
out soSHL_Nts_Tcp_LsnReq_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:165
Role_Kale.moSHL_Mem_Mp1_AWSIZE
out moSHL_Mem_Mp1_AWSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:217
Role_Kale.soSHL_Mem_Mp0_RdCmd_tready
in soSHL_Mem_Mp0_RdCmd_treadystd_ulogic
Definition: Role.vhdl:180
Role_Kale.piSHL_Mmio_Mc1_MemTestCtrl
in piSHL_Mmio_Mc1_MemTestCtrlstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:247
Role_Kale.soSHL_Nts_Udp_Data_tlast
out soSHL_Nts_Udp_Data_tlaststd_ulogic
Definition: Role.vhdl:95
Role_Kale.siSHL_Nts_Udp_LsnRep_tready
out siSHL_Nts_Udp_LsnRep_treadystd_ulogic
Definition: Role.vhdl:105
Role_Kale.soSHL_Nts_Udp_LsnReq_tready
in soSHL_Nts_Udp_LsnReq_treadystd_ulogic
Definition: Role.vhdl:101
Role_Kale.soSHL_Nts_Udp_DLen_tdata
out soSHL_Nts_Udp_DLen_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:92
Role_Kale.soSHL_Nts_Tcp_OpnReq_tvalid
out soSHL_Nts_Tcp_OpnReq_tvalidstd_ulogic
Definition: Role.vhdl:149
Role_Kale.gVivadoVersion
gVivadoVersioninteger :=2019
Definition: Role.vhdl:54
Role_Kale.soSHL_Nts_Tcp_OpnReq_tdata
out soSHL_Nts_Tcp_OpnReq_tdatastd_ulogic_vector(47 downto 0)
Definition: Role.vhdl:148
Role_Kale.moSHL_Mem_Mp1_RDATA
in moSHL_Mem_Mp1_RDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:242
Role_Kale.siSHL_Nts_Udp_DLen_tvalid
in siSHL_Nts_Udp_DLen_tvalidstd_ulogic
Definition: Role.vhdl:76
Role_Kale.moSHL_Mem_Mp1_RVALID
in moSHL_Mem_Mp1_RVALIDstd_ulogic
Definition: Role.vhdl:245
Role_Kale.moSHL_Mem_Mp1_WSTRB
out moSHL_Mem_Mp1_WSTRBstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:223
Role_Kale.soSHL_Nts_Tcp_ClsReq_tvalid
out soSHL_Nts_Tcp_ClsReq_tvalidstd_ulogic
Definition: Role.vhdl:157
Role_Kale.moSHL_Mem_Mp1_AWVALID
out moSHL_Mem_Mp1_AWVALIDstd_ulogic
Definition: Role.vhdl:219
Role_Kale.moSHL_Mem_Mp1_AWID
out moSHL_Mem_Mp1_AWIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:214
Role_Kale.soSHL_Mem_Mp0_Write_tvalid
out soSHL_Mem_Mp0_Write_tvalidstd_ulogic
Definition: Role.vhdl:203
Role_Kale.siSHL_Nts_Udp_ClsRep_tready
out siSHL_Nts_Udp_ClsRep_treadystd_ulogic
Definition: Role.vhdl:113
Role_Kale.siSHL_Nts_Tcp_SndRep_tready
out siSHL_Nts_Tcp_SndRep_treadystd_ulogic
Definition: Role.vhdl:130
Role_Kale.siSHL_Nts_Udp_Data_tkeep
in siSHL_Nts_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:88
Role_Kale.soSHL_Nts_Tcp_LsnReq_tready
in soSHL_Nts_Tcp_LsnReq_treadystd_ulogic
Definition: Role.vhdl:167
Role_Kale.soSHL_Nts_Tcp_SndReq_tready
in soSHL_Nts_Tcp_SndReq_treadystd_ulogic
Definition: Role.vhdl:126
Role_Kale.siSHL_Nts_Udp_LsnRep_tdata
in siSHL_Nts_Udp_LsnRep_tdatastd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:103
Role_Kale.moSHL_Mem_Mp1_ARADDR
out moSHL_Mem_Mp1_ARADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:234
Role_Kale.soSHL_Mem_Mp0_WrCmd_tready
in soSHL_Mem_Mp0_WrCmd_treadystd_ulogic
Definition: Role.vhdl:194
Role_Kale.soSHL_Mem_Mp0_Write_tlast
out soSHL_Mem_Mp0_Write_tlaststd_ulogic
Definition: Role.vhdl:202
Role_Kale.siSHL_Nts_Tcp_Notif_tdata
in siSHL_Nts_Tcp_Notif_tdatastd_ulogic_vector(7+96 downto 0)
Definition: Role.vhdl:135
Role_Kale.soSHL_Nts_Tcp_Data_tdata
out soSHL_Nts_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:104
Role_Kale.soSHL_Nts_Udp_Meta_tvalid
out soSHL_Nts_Udp_Meta_tvalidstd_ulogic
Definition: Role.vhdl:89
Role_Kale.moSHL_Mem_Mp1_ARLEN
out moSHL_Mem_Mp1_ARLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:235
Role_Kale.siSHL_Nts_Udp_Meta_tready
out siSHL_Nts_Udp_Meta_treadystd_ulogic
Definition: Role.vhdl:73
Role_Kale.soSHL_Nts_Tcp_Data_tkeep
out soSHL_Nts_Tcp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:105
Role_Kale.soSHL_Nts_Udp_Data_tdata
out soSHL_Nts_Udp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:93
Role_Kale.moSHL_Mem_Mp1_ARREADY
in moSHL_Mem_Mp1_ARREADYstd_ulogic
Definition: Role.vhdl:239
Role_Kale.siSHL_Nts_Tcp_Meta_tdata
in siSHL_Nts_Tcp_Meta_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:129
Role_Kale.soSHL_Nts_Udp_LsnReq_tvalid
out soSHL_Nts_Udp_LsnReq_tvalidstd_ulogic
Definition: Role.vhdl:100
Role_Kale.soSHL_Mem_Mp0_RdCmd_tdata
out soSHL_Mem_Mp0_RdCmd_tdatastd_ulogic_vector(79 downto 0)
Definition: Role.vhdl:178
Role_Kale.siSHL_Nts_Tcp_Data_tdata
in siSHL_Nts_Tcp_Data_tdatastd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:123
Role_Kale.moSHL_Mem_Mp1_AWLEN
out moSHL_Mem_Mp1_AWLENstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:216
Role_Kale.moSHL_Mem_Mp1_ARSIZE
out moSHL_Mem_Mp1_ARSIZEstd_ulogic_vector(2 downto 0)
Definition: Role.vhdl:236
Role_Kale.soSHL_Nts_Tcp_SndReq_tdata
out soSHL_Nts_Tcp_SndReq_tdatastd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:124
Role_Kale.siSHL_Nts_Udp_DLen_tready
out siSHL_Nts_Udp_DLen_treadystd_ulogic
Definition: Role.vhdl:77
Role_Kale.soSHL_Nts_Udp_Meta_tready
in soSHL_Nts_Udp_Meta_treadystd_ulogic
Definition: Role.vhdl:90
Role_Kale.moSHL_Mem_Mp1_WLAST
out moSHL_Mem_Mp1_WLASTstd_ulogic
Definition: Role.vhdl:224
Role_Kale.siSHL_Nts_Udp_LsnRep_tvalid
in siSHL_Nts_Udp_LsnRep_tvalidstd_ulogic
Definition: Role.vhdl:104
Role_Kale.soSHL_Nts_Tcp_DReq_tdata
out soSHL_Nts_Tcp_DReq_tdatastd_ulogic_vector(31 downto 0)
Definition: Role.vhdl:139
Role_Kale.moSHL_Mem_Mp1_WDATA
out moSHL_Mem_Mp1_WDATAstd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:222
Role_Kale.soSHL_Nts_Udp_Data_tkeep
out soSHL_Nts_Udp_Data_tkeepstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:94
Role_Kale.siSHL_Nts_Tcp_SndRep_tvalid
in siSHL_Nts_Tcp_SndRep_tvalidstd_ulogic
Definition: Role.vhdl:129
Role_Kale.soSHL_Nts_Udp_ClsReq_tvalid
out soSHL_Nts_Udp_ClsReq_tvalidstd_ulogic
Definition: Role.vhdl:108
Role_Kale.soSHL_Nts_Udp_ClsReq_tdata
out soSHL_Nts_Udp_ClsReq_tdatastd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:107
Role_Kale.siSHL_Mem_Mp0_Read_tvalid
in siSHL_Mem_Mp0_Read_tvalidstd_ulogic
Definition: Role.vhdl:189
Role_Kale.soSHL_Mem_Mp0_Write_tkeep
out soSHL_Mem_Mp0_Write_tkeepstd_ulogic_vector(63 downto 0)
Definition: Role.vhdl:201
Role_Kale.siSHL_Nts_Udp_Data_tvalid
in siSHL_Nts_Udp_Data_tvalidstd_ulogic
Definition: Role.vhdl:90
Role_Kale.siSHL_Nts_Tcp_LsnRep_tready
out siSHL_Nts_Tcp_LsnRep_treadystd_ulogic
Definition: Role.vhdl:177
Role_Kale.piTOP_250_00Clk
in piTOP_250_00Clkstd_ulogic
Definition: Role.vhdl:265
Role_Kale.moSHL_Mem_Mp1_RLAST
in moSHL_Mem_Mp1_RLASTstd_ulogic
Definition: Role.vhdl:244
Role_Kale.moSHL_Mem_Mp1_ARBURST
out moSHL_Mem_Mp1_ARBURSTstd_ulogic_vector(1 downto 0)
Definition: Role.vhdl:237
Role_Kale.siSHL_Nts_Tcp_Meta_tvalid
in siSHL_Nts_Tcp_Meta_tvalidstd_ulogic
Definition: Role.vhdl:132
Role_Kale.piSHL_Mmio_WrReg
in piSHL_Mmio_WrRegstd_ulogic_vector(15 downto 0)
Definition: Role.vhdl:260
Role_Kale.moSHL_Mem_Mp1_BVALID
in moSHL_Mem_Mp1_BVALIDstd_ulogic
Definition: Role.vhdl:230
Role_Kale.siSHL_Nts_Tcp_LsnRep_tvalid
in siSHL_Nts_Tcp_LsnRep_tvalidstd_ulogic
Definition: Role.vhdl:176
Role_Kale.soSHL_Nts_Tcp_ClsReq_tready
in soSHL_Nts_Tcp_ClsReq_treadystd_ulogic
Definition: Role.vhdl:158
Role_Kale.moSHL_Mem_Mp1_ARID
out moSHL_Mem_Mp1_ARIDstd_ulogic_vector(7 downto 0)
Definition: Role.vhdl:233
Role_Kale.siSHL_Mem_Mp0_WrSts_tready
out siSHL_Mem_Mp0_WrSts_treadystd_ulogic
Definition: Role.vhdl:198
Role_Kale.siSHL_Mem_Mp0_RdSts_tready
out siSHL_Mem_Mp0_RdSts_treadystd_ulogic
Definition: Role.vhdl:184
Role_Kale.moSHL_Mem_Mp1_ARVALID
out moSHL_Mem_Mp1_ARVALIDstd_ulogic
Definition: Role.vhdl:238
Role_Kale.siSHL_Mem_Mp0_Read_tdata
in siSHL_Mem_Mp0_Read_tdatastd_ulogic_vector(511 downto 0)
Definition: Role.vhdl:186
Role_Kale.moSHL_Mem_Mp1_AWADDR
out moSHL_Mem_Mp1_AWADDRstd_ulogic_vector(32 downto 0)
Definition: Role.vhdl:215
Role_Kale.piSHL_Mmio_Ly7Rst
in piSHL_Mmio_Ly7Rststd_ulogic
Definition: Role.vhdl:243
Role_Kale.siSHL_Nts_Tcp_Data_tvalid
in siSHL_Nts_Tcp_Data_tvalidstd_ulogic
Definition: Role.vhdl:126
topFMKU60.poDDR4_Mem_Mc0_Reset_n
out poDDR4_Mem_Mc0_Reset_nstd_ulogic
Definition: top.vhdl:149
topFMKU60.pioPSOC_Emif_Data
inout pioPSOC_Emif_Datastd_ulogic_vector( gEmifDataWidth- 1 downto 0)
Definition: top.vhdl:126
topFMKU60.poDDR4_Mem_Mc0_Odt
out poDDR4_Mem_Mc0_Odtstd_ulogic
Definition: top.vhdl:145
topFMKU60.poDDR4_Mem_Mc0_Act_n
out poDDR4_Mem_Mc0_Act_nstd_ulogic
Definition: top.vhdl:140
topFMKU60.piPSOC_Emif_Addr
in piPSOC_Emif_Addrstd_ulogic_vector( gEmifAddrWidth- 1 downto 0)
Definition: top.vhdl:125
topFMKU60.piPSOC_Emif_Clk
in piPSOC_Emif_Clkstd_ulogic
Definition: top.vhdl:120
topFMKU60.pioDDR4_Mem_Mc0_Dqs_n
inout pioDDR4_Mem_Mc0_Dqs_nstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:139
topFMKU60.piPSOC_Emif_Cs_n
in piPSOC_Emif_Cs_nstd_ulogic
Definition: top.vhdl:121
topFMKU60.gBitstreamUsage
gBitstreamUsagestring := "flash"
Definition: top.vhdl:78
topFMKU60.poDDR4_Mem_Mc1_Ck_n
out poDDR4_Mem_Mc1_Ck_nstd_ulogic
Definition: top.vhdl:166
topFMKU60.pioDDR4_Mem_Mc0_DmDbi_n
inout pioDDR4_Mem_Mc0_DmDbi_nstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:136
topFMKU60.gEmifDataWidth
gEmifDataWidthinteger :=8
Definition: top.vhdl:87
topFMKU60.piCLKT_Usr1Clk_n
in piCLKT_Usr1Clk_nstd_ulogic
Definition: top.vhdl:114
topFMKU60.poDDR4_Mem_Mc0_Ck_n
out poDDR4_Mem_Mc0_Ck_nstd_ulogic
Definition: top.vhdl:148
topFMKU60.piCLKT_10GeClk_p
in piCLKT_10GeClk_pstd_ulogic
Definition: top.vhdl:107
topFMKU60.poDDR4_Mem_Mc0_Ck_p
out poDDR4_Mem_Mc0_Ck_pstd_ulogic
Definition: top.vhdl:147
topFMKU60.piPSOC_Emif_AdS_n
in piPSOC_Emif_AdS_nstd_ulogic
Definition: top.vhdl:124
topFMKU60.piPSOC_Emif_We_n
in piPSOC_Emif_We_nstd_ulogic
Definition: top.vhdl:122
topFMKU60.poDDR4_Mem_Mc0_Adr
out poDDR4_Mem_Mc0_Adrstd_ulogic_vector(16 downto 0)
Definition: top.vhdl:141
topFMKU60.poLED_HeartBeat_n
out poLED_HeartBeat_nstd_ulogic
Definition: top.vhdl:131
topFMKU60.piPSOC_Emif_Oe_n
in piPSOC_Emif_Oe_nstd_ulogic
Definition: top.vhdl:123
topFMKU60.gTopDateMonth
gTopDateMonthstDate :=8d"00"
Definition: top.vhdl:82
topFMKU60.pioDDR4_Mem_Mc1_Dqs_n
inout pioDDR4_Mem_Mc1_Dqs_nstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:157
topFMKU60.piCLKT_Mem0Clk_n
in piCLKT_Mem0Clk_nstd_ulogic
Definition: top.vhdl:98
topFMKU60.pioDDR4_Mem_Mc1_Dq
inout pioDDR4_Mem_Mc1_Dqstd_ulogic_vector(71 downto 0)
Definition: top.vhdl:155
topFMKU60.pioDDR4_Mem_Mc1_DmDbi_n
inout pioDDR4_Mem_Mc1_DmDbi_nstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:154
topFMKU60.gVivadoVersion
gVivadoVersioninteger :=2019
Definition: top.vhdl:83
topFMKU60.piCLKT_Usr0Clk_n
in piCLKT_Usr0Clk_nstd_ulogic
Definition: top.vhdl:112
topFMKU60.pioDDR4_Mem_Mc0_Dq
inout pioDDR4_Mem_Mc0_Dqstd_ulogic_vector(71 downto 0)
Definition: top.vhdl:137
topFMKU60.poDDR4_Mem_Mc1_Cke
out poDDR4_Mem_Mc1_Ckestd_ulogic
Definition: top.vhdl:162
topFMKU60.piCLKT_Mem1Clk_p
in piCLKT_Mem1Clk_pstd_ulogic
Definition: top.vhdl:101
topFMKU60.pioDDR4_Mem_Mc0_Dqs_p
inout pioDDR4_Mem_Mc0_Dqs_pstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:138
topFMKU60.poDDR4_Mem_Mc1_Adr
out poDDR4_Mem_Mc1_Adrstd_ulogic_vector(16 downto 0)
Definition: top.vhdl:159
topFMKU60.gTopDateDay
gTopDateDaystDate :=8d"00"
Definition: top.vhdl:83
topFMKU60.gSecurityPriviledges
gSecurityPriviledgesstring := "super"
Definition: top.vhdl:79
topFMKU60.poDDR4_Mem_Mc1_Ck_p
out poDDR4_Mem_Mc1_Ck_pstd_ulogic
Definition: top.vhdl:165
topFMKU60.gEmifAddrWidth
gEmifAddrWidthinteger :=8
Definition: top.vhdl:85
topFMKU60.piCLKT_Usr1Clk_p
in piCLKT_Usr1Clk_pstd_ulogic
Definition: top.vhdl:115
topFMKU60.poDDR4_Mem_Mc1_Cs_n
out poDDR4_Mem_Mc1_Cs_nstd_ulogic
Definition: top.vhdl:164
topFMKU60.poDDR4_Mem_Mc0_Bg
out poDDR4_Mem_Mc0_Bgstd_ulogic_vector(1 downto 0)
Definition: top.vhdl:143
topFMKU60.piECON_Eth_10Ge0_p
in piECON_Eth_10Ge0_pstd_ulogic
Definition: top.vhdl:173
topFMKU60.poDDR4_Mem_Mc0_Cs_n
out poDDR4_Mem_Mc0_Cs_nstd_ulogic
Definition: top.vhdl:146
topFMKU60.piCLKT_Usr0Clk_p
in piCLKT_Usr0Clk_pstd_ulogic
Definition: top.vhdl:113
topFMKU60.poECON_Eth_10Ge0_n
out poECON_Eth_10Ge0_nstd_ulogic
Definition: top.vhdl:174
topFMKU60.piECON_Eth_10Ge0_n
in piECON_Eth_10Ge0_nstd_ulogic
Definition: top.vhdl:172
topFMKU60.piPSOC_Fcfg_Rst_n
in piPSOC_Fcfg_Rst_nstd_ulogic
Definition: top.vhdl:93
topFMKU60.gTopDateYear
gTopDateYearstDate :=8d"00"
Definition: top.vhdl:81
topFMKU60.piCLKT_Mem0Clk_p
in piCLKT_Mem0Clk_pstd_ulogic
Definition: top.vhdl:99
topFMKU60.poECON_Eth_10Ge0_p
out poECON_Eth_10Ge0_pstd_ulogic
Definition: top.vhdl:177
topFMKU60.poDDR4_Mem_Mc1_Act_n
out poDDR4_Mem_Mc1_Act_nstd_ulogic
Definition: top.vhdl:158
topFMKU60.pioDDR4_Mem_Mc1_Dqs_p
inout pioDDR4_Mem_Mc1_Dqs_pstd_ulogic_vector(8 downto 0)
Definition: top.vhdl:156
topFMKU60.poDDR4_Mem_Mc0_Ba
out poDDR4_Mem_Mc0_Bastd_ulogic_vector(1 downto 0)
Definition: top.vhdl:142
topFMKU60.poDDR4_Mem_Mc1_Ba
out poDDR4_Mem_Mc1_Bastd_ulogic_vector(1 downto 0)
Definition: top.vhdl:160
topFMKU60.poDDR4_Mem_Mc1_Bg
out poDDR4_Mem_Mc1_Bgstd_ulogic_vector(1 downto 0)
Definition: top.vhdl:161
topFMKU60.poDDR4_Mem_Mc1_Odt
out poDDR4_Mem_Mc1_Odtstd_ulogic
Definition: top.vhdl:163
topFMKU60.poDDR4_Mem_Mc1_Reset_n
out poDDR4_Mem_Mc1_Reset_nstd_ulogic
Definition: top.vhdl:167
topFMKU60.piCLKT_10GeClk_n
in piCLKT_10GeClk_nstd_ulogic
Definition: top.vhdl:106
topFMKU60.poDDR4_Mem_Mc0_Cke
out poDDR4_Mem_Mc0_Ckestd_ulogic
Definition: top.vhdl:144
topFMKU60.piCLKT_Mem1Clk_n
in piCLKT_Mem1Clk_nstd_ulogic
Definition: top.vhdl:100