cloudFPGA (cF) API  1.0
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MedianBlur HLS
cF » cFp » cFp_Zoo » cF Vitis Vision » MedianBlur

This is a subgroup of MedianBlur accelerated function with only synthesizable (HLS) functions/classes. More...

Collaboration diagram for MedianBlur HLS:

Files

file  median_blur.hpp
 The Role for a MedianBlur Example application (UDP or TCP)
 
file  xf_config_params.h
 The MedianBlur IP configuration header.
 
file  median_blur.cpp
 The Role for a MedianBlur Example application (UDP or TCP)
 
file  xf_median_blur_accel.cpp
 The MedianBlur top-level.
 

Classes

struct  Axis< D >
 

Macros

#define ENABLE_DDR
 
#define ROLE_IS_MEDIANBLUR
 
#define WAIT_FOR_META   0
 
#define PROCESSING_PACKET   1
 
#define LOAD_IN_STREAM   2
 
#define MEDIANBLUR_RETURN_RESULTS   3
 
#define MEDIANBLUR_RETURN_RESULTS_ABSORB_DDR_LAT   4
 
#define MEDIANBLUR_RETURN_RESULTS_UNPACK   5
 
#define MEDIANBLUR_RETURN_RESULTS_FWD   6
 
#define WAIT_FOR_TX   7
 
#define FSM_IDLE   8
 
#define FSM_CHK_SKIP   9
 
#define FSM_CHK_PROC_BYTES   10
 
#define FSM_CHK_WRT_CHNK_TO_DDR_PND   11
 
#define FSM_WR_PAT_CMD   12
 
#define FSM_WR_PAT_LOAD   13
 
#define FSM_WR_PAT_DATA   14
 
#define FSM_WR_PAT_STS_A   15
 
#define FSM_WR_PAT_STS_B   16
 
#define FSM_WR_PAT_STS_C   17
 
#define PacketFsmType   uint8_t
 
#define FSM_WRITE_NEW_DATA   0
 
#define FSM_DONE   1
 
#define PortFsmType   uint8_t
 
#define DEFAULT_TX_PORT   2718
 
#define DEFAULT_RX_PORT   2718
 
#define PORTS_OPENED   0x1F
 
#define Data_t_in   ap_axiu<INPUT_PTR_WIDTH, 0, 0, 0>
 
#define Data_t_out   ap_axiu<OUTPUT_PTR_WIDTH, 0, 0, 0>
 
#define MAX_NB_OF_ELMT_READ   16
 
#define MAX_NB_OF_WORDS_READ   (MAX_NB_OF_ELMT_READ*sizeof(mat_elmt_t)/BPERDW)
 
#define MAX_NB_OF_ELMT_PERDW   (BPERDW/sizeof(mat_elmt_t))
 
#define MEMDW_512   512
 
#define BPERMDW_512   (MEMDW_512/8)
 
#define KWPERMDW_512   (BPERMDW_512/sizeof(TYPE))
 
#define TOTMEMDW_512   (1 + (IMGSIZE - 1) / BPERMDW_512)
 
#define CHECK_CHUNK_SIZE   0x1000
 This define configures tha AXI burst size of DDRM memory-mapped interfaces AXI4 allows 4KiB, but Role's AXI interconnect is configured at max 1KiB 0x40->64, 0x400->1024B(1KiB), 0x1000->4KiB. More...
 
#define BYTE_PER_MEM_WORD   BPERMDW_512
 
#define TRANSFERS_PER_CHUNK   (CHECK_CHUNK_SIZE/BYTE_PER_MEM_WORD)
 
#define TRANSFERS_PER_CHUNK_DIVEND   (TOTMEMDW_512-(TOTMEMDW_512/TRANSFERS_PER_CHUNK)*TRANSFERS_PER_CHUNK)
 
#define fsmStateDDRdef   uint8_t
 
#define CYCLES_UNTIL_TIMEOUT   0x0100
 
#define TYPICAL_DDR_LATENCY   4
 
#define DDR_LATENCY   (52/4)
 
#define EXTRA_DDR_LATENCY_DUE_II   (64 + 8)
 
#define NO   1
 
#define RO   0
 
#define RGB   0
 
#define GRAY   1
 
#define WINDOW_SIZE   9
 
#define TRANSFERS_PER_CHUNK_LAST_BURST   TRANSFERS_PER_CHUNK
 

Typedefs

typedef uint8_t mat_elmt_t
 
typedef ap_uint< 512 > membus_512_t
 
typedef membus_512_t membus_t
 

Enumerations

enum  EchoCtrl {
  ECHO_PATH_THRU = 0 , ECHO_STORE_FWD = 1 , ECHO_OFF = 2 , ECHO_PATH_THRU = 0 ,
  ECHO_STORE_FWD = 1 , ECHO_OFF = 2 , ECHO_PATH_THRU = 0 , ECHO_STORE_FWD = 1 ,
  ECHO_OFF = 2 , ECHO_PATH_THRU = 0 , ECHO_STORE_FWD = 1 , ECHO_OFF = 2 ,
  ECHO_PATH_THRU = 0 , ECHO_STORE_FWD = 1 , ECHO_OFF = 2 , ECHO_PATH_THRU = 0 ,
  ECHO_STORE_FWD = 1 , ECHO_OFF = 2 , ECHO_PATH_THRU = 0 , ECHO_STORE_FWD = 1 ,
  ECHO_OFF = 2 , ECHO_STORE_FWD = 0 , ECHO_PATH_THRU = 1 , ECHO_CTRL_DISABLED = 0 ,
  ECHO_PATH_THRU = 1 , ECHO_STORE_FWD = 2 , ECHO_OFF = 3
}
 

Functions

void median_blur (ap_uint< 32 > *pi_rank, ap_uint< 32 > *pi_size, stream< NetworkWord > &siSHL_This_Data, stream< NetworkWord > &soTHIS_Shl_Data, stream< NetworkMetaStream > &siNrc_meta, stream< NetworkMetaStream > &soNrc_meta, ap_uint< 32 > *po_rx_ports, stream< DmCmd > &soMemWrCmdP0, stream< DmSts > &siMemWrStsP0, stream< Axis< 512 > > &soMemWriteP0, membus_t *lcl_mem0, membus_t *lcl_mem1)
 Main process of the MedianBlur Application directives. More...
 
void pPortAndDestionation (ap_uint< 32 > *pi_rank, ap_uint< 32 > *pi_size, ap_uint< 32 > *po_rx_ports)
 
void storeWordToArray (uint64_t input, ap_uint< 8 > img[1024 *1024/((64/8))], unsigned int *processed_word, unsigned int *image_loaded)
 Store a net word to local memory. More...
 
void storeWordToAxiStream (NetworkWord word, stream< ap_uint< 8 >> &img_in_axi_stream, unsigned int *processed_word_rx, unsigned int *processed_bytes_rx, stream< bool > &sImageLoaded)
 Store a net word to a local AXI stream. More...
 
void pRXPathDDROLD (stream< NetworkWord > &siSHL_This_Data, stream< NetworkMetaStream > &siNrc_meta, stream< NetworkMetaStream > &sRxtoTx_Meta, stream< DmCmd > &soMemWrCmdP0, stream< DmSts > &siMemWrStsP0, stream< Axis< 512 > > &soMemWriteP0, NetworkMetaStream meta_tmp, unsigned int *processed_bytes_rx, stream< bool > &sImageLoaded)
 Receive Path - From SHELL to THIS. More...
 
void pRXPathNetToStream (stream< NetworkWord > &siSHL_This_Data, stream< NetworkMetaStream > &siNrc_meta, stream< NetworkMetaStream > &sRxtoTx_Meta, stream< ap_uint< 512 >> &img_in_axi_stream, stream< bool > &sMemBurstRx)
 Receive Path - From SHELL to THIS. More...
 
void pRXPathStreamToDDR (stream< ap_uint< 512 >> &img_in_axi_stream, stream< bool > &sMemBurstRx, stream< DmCmd > &soMemWrCmdP0, stream< DmSts > &siMemWrStsP0, stream< Axis< 512 > > &soMemWriteP0, stream< bool > &sImageLoaded)
 Receive Path - From SHELL to THIS. More...
 
void pRXPath (stream< NetworkWord > &siSHL_This_Data, stream< NetworkMetaStream > &siNrc_meta, stream< NetworkMetaStream > &sRxtoTx_Meta, stream< ap_uint< 8 >> &img_in_axi_stream, NetworkMetaStream meta_tmp, unsigned int *processed_word_rx, unsigned int *processed_bytes_rx, stream< bool > &sImageLoaded)
 Receive Path - From SHELL to THIS. More...
 
void pProcPath (stream< NetworkWord > &sRxpToTxp_Data, membus_t *lcl_mem0, membus_t *lcl_mem1, stream< bool > &sImageLoaded)
 Processing Path - Main processing FSM for Vitis kernels. More...
 
void pTXPath (stream< NetworkWord > &soTHIS_Shl_Data, stream< NetworkMetaStream > &soNrc_meta, stream< NetworkWord > &sRxpToTxp_Data, stream< NetworkMetaStream > &sRxtoTx_Meta, unsigned int *processed_word_tx, ap_uint< 32 > *pi_rank, ap_uint< 32 > *pi_size)
 Transmit Path - From THIS to SHELL. More...
 
void median_blur_accel (xf::cv::Mat< XF_8UC1, 1024, 1024, XF_NPPC1 > &imgInput, xf::cv::Mat< XF_8UC1, 1024, 1024, XF_NPPC1 > &imgOutput)
 Top-level accelerated function of the MedianBlur Application with xf::cv I/F. More...
 
void medianBlurAccelArray (ap_uint< 8 > *img_in, ap_uint< 64 > *img_out, int rows, int cols)
 Top-level accelerated function of the MedianBlur Application with array I/F. More...
 
void medianBlurAccelStream (hls::stream< ap_uint< 8 >> &img_in_axi_stream, hls::stream< ap_uint< 64 >> &img_out_axi_stream, int rows, int cols)
 Top-level accelerated function of the MedianBlur Application with array I/F. More...
 
void medianBlurAccelMem (membus_t *img_inp, membus_t *img_out, int rows, int cols)
 Top-level accelerated function of the MedianBlur Application with array I/F. More...
 

Variables

uint8_t enqueueRxToStrFSM = 0
 
uint8_t enqueueStrToDdrFSM = 0
 
uint8_t enqueueFSM = 0
 
uint8_t dequeueFSM = 0
 
uint8_t MedianBlurFSM = 0
 
unsigned int sRxpToTxp_DataCounter = 0
 

Detailed Description

This is a subgroup of MedianBlur accelerated function with only synthesizable (HLS) functions/classes.

Macro Definition Documentation

◆ BPERMDW_512

#define BPERMDW_512   (MEMDW_512/8)

Definition at line 117 of file median_blur.hpp.

◆ BYTE_PER_MEM_WORD

#define BYTE_PER_MEM_WORD   BPERMDW_512

Definition at line 129 of file median_blur.hpp.

◆ CHECK_CHUNK_SIZE

#define CHECK_CHUNK_SIZE   0x1000

This define configures tha AXI burst size of DDRM memory-mapped interfaces AXI4 allows 4KiB, but Role's AXI interconnect is configured at max 1KiB 0x40->64, 0x400->1024B(1KiB), 0x1000->4KiB.

Definition at line 128 of file median_blur.hpp.

◆ CYCLES_UNTIL_TIMEOUT

#define CYCLES_UNTIL_TIMEOUT   0x0100

Definition at line 144 of file median_blur.hpp.

◆ Data_t_in

#define Data_t_in   ap_axiu<INPUT_PTR_WIDTH, 0, 0, 0>

Definition at line 101 of file median_blur.hpp.

◆ Data_t_out

#define Data_t_out   ap_axiu<OUTPUT_PTR_WIDTH, 0, 0, 0>

Definition at line 102 of file median_blur.hpp.

◆ DDR_LATENCY

#define DDR_LATENCY   (52/4)

Definition at line 148 of file median_blur.hpp.

◆ DEFAULT_RX_PORT

#define DEFAULT_RX_PORT   2718

Definition at line 94 of file median_blur.hpp.

◆ DEFAULT_TX_PORT

#define DEFAULT_TX_PORT   2718

Definition at line 93 of file median_blur.hpp.

◆ ENABLE_DDR

#define ENABLE_DDR

Definition at line 55 of file median_blur.hpp.

◆ EXTRA_DDR_LATENCY_DUE_II

#define EXTRA_DDR_LATENCY_DUE_II   (64 + 8)

Definition at line 149 of file median_blur.hpp.

◆ FSM_CHK_PROC_BYTES

#define FSM_CHK_PROC_BYTES   10

Definition at line 78 of file median_blur.hpp.

◆ FSM_CHK_SKIP

#define FSM_CHK_SKIP   9

Definition at line 77 of file median_blur.hpp.

◆ FSM_CHK_WRT_CHNK_TO_DDR_PND

#define FSM_CHK_WRT_CHNK_TO_DDR_PND   11

Definition at line 79 of file median_blur.hpp.

◆ FSM_DONE

#define FSM_DONE   1

Definition at line 90 of file median_blur.hpp.

◆ FSM_IDLE

#define FSM_IDLE   8

Definition at line 76 of file median_blur.hpp.

◆ FSM_WR_PAT_CMD

#define FSM_WR_PAT_CMD   12

Definition at line 80 of file median_blur.hpp.

◆ FSM_WR_PAT_DATA

#define FSM_WR_PAT_DATA   14

Definition at line 82 of file median_blur.hpp.

◆ FSM_WR_PAT_LOAD

#define FSM_WR_PAT_LOAD   13

Definition at line 81 of file median_blur.hpp.

◆ FSM_WR_PAT_STS_A

#define FSM_WR_PAT_STS_A   15

Definition at line 83 of file median_blur.hpp.

◆ FSM_WR_PAT_STS_B

#define FSM_WR_PAT_STS_B   16

Definition at line 84 of file median_blur.hpp.

◆ FSM_WR_PAT_STS_C

#define FSM_WR_PAT_STS_C   17

Definition at line 85 of file median_blur.hpp.

◆ FSM_WRITE_NEW_DATA

#define FSM_WRITE_NEW_DATA   0

Definition at line 89 of file median_blur.hpp.

◆ fsmStateDDRdef

#define fsmStateDDRdef   uint8_t

Definition at line 141 of file median_blur.hpp.

◆ GRAY

#define GRAY   1

Definition at line 60 of file xf_config_params.h.

◆ KWPERMDW_512

#define KWPERMDW_512   (BPERMDW_512/sizeof(TYPE))

Definition at line 118 of file median_blur.hpp.

◆ LOAD_IN_STREAM

#define LOAD_IN_STREAM   2

Definition at line 70 of file median_blur.hpp.

◆ MAX_NB_OF_ELMT_PERDW

#define MAX_NB_OF_ELMT_PERDW   (BPERDW/sizeof(mat_elmt_t))

Definition at line 109 of file median_blur.hpp.

◆ MAX_NB_OF_ELMT_READ

#define MAX_NB_OF_ELMT_READ   16

Definition at line 105 of file median_blur.hpp.

◆ MAX_NB_OF_WORDS_READ

#define MAX_NB_OF_WORDS_READ   (MAX_NB_OF_ELMT_READ*sizeof(mat_elmt_t)/BPERDW)

Definition at line 108 of file median_blur.hpp.

◆ MEDIANBLUR_RETURN_RESULTS

#define MEDIANBLUR_RETURN_RESULTS   3

Definition at line 71 of file median_blur.hpp.

◆ MEDIANBLUR_RETURN_RESULTS_ABSORB_DDR_LAT

#define MEDIANBLUR_RETURN_RESULTS_ABSORB_DDR_LAT   4

Definition at line 72 of file median_blur.hpp.

◆ MEDIANBLUR_RETURN_RESULTS_FWD

#define MEDIANBLUR_RETURN_RESULTS_FWD   6

Definition at line 74 of file median_blur.hpp.

◆ MEDIANBLUR_RETURN_RESULTS_UNPACK

#define MEDIANBLUR_RETURN_RESULTS_UNPACK   5

Definition at line 73 of file median_blur.hpp.

◆ MEMDW_512

#define MEMDW_512   512

Definition at line 116 of file median_blur.hpp.

◆ NO

#define NO   1

Definition at line 56 of file xf_config_params.h.

◆ PacketFsmType

#define PacketFsmType   uint8_t

Definition at line 86 of file median_blur.hpp.

◆ PortFsmType

#define PortFsmType   uint8_t

Definition at line 91 of file median_blur.hpp.

◆ PORTS_OPENED

#define PORTS_OPENED   0x1F

Definition at line 99 of file median_blur.hpp.

◆ PROCESSING_PACKET

#define PROCESSING_PACKET   1

Definition at line 69 of file median_blur.hpp.

◆ RGB

#define RGB   0

Definition at line 59 of file xf_config_params.h.

◆ RO

#define RO   0

Definition at line 57 of file xf_config_params.h.

◆ ROLE_IS_MEDIANBLUR

#define ROLE_IS_MEDIANBLUR

Definition at line 66 of file median_blur.hpp.

◆ TOTMEMDW_512

#define TOTMEMDW_512   (1 + (IMGSIZE - 1) / BPERMDW_512)

Definition at line 121 of file median_blur.hpp.

◆ TRANSFERS_PER_CHUNK

#define TRANSFERS_PER_CHUNK   (CHECK_CHUNK_SIZE/BYTE_PER_MEM_WORD)

Definition at line 130 of file median_blur.hpp.

◆ TRANSFERS_PER_CHUNK_DIVEND

#define TRANSFERS_PER_CHUNK_DIVEND   (TOTMEMDW_512-(TOTMEMDW_512/TRANSFERS_PER_CHUNK)*TRANSFERS_PER_CHUNK)

Definition at line 131 of file median_blur.hpp.

◆ TRANSFERS_PER_CHUNK_LAST_BURST

#define TRANSFERS_PER_CHUNK_LAST_BURST   TRANSFERS_PER_CHUNK

Definition at line 57 of file median_blur.cpp.

◆ TYPICAL_DDR_LATENCY

#define TYPICAL_DDR_LATENCY   4

Definition at line 145 of file median_blur.hpp.

◆ WAIT_FOR_META

#define WAIT_FOR_META   0

Definition at line 68 of file median_blur.hpp.

◆ WAIT_FOR_TX

#define WAIT_FOR_TX   7

Definition at line 75 of file median_blur.hpp.

◆ WINDOW_SIZE

#define WINDOW_SIZE   9

Definition at line 62 of file xf_config_params.h.

Typedef Documentation

◆ mat_elmt_t

typedef uint8_t mat_elmt_t

Definition at line 106 of file median_blur.hpp.

◆ membus_512_t

typedef ap_uint< 512 > membus_512_t

Definition at line 119 of file median_blur.hpp.

◆ membus_t

typedef membus_512_t membus_t

Definition at line 120 of file median_blur.hpp.

Enumeration Type Documentation

◆ EchoCtrl

enum EchoCtrl

SHELL/MMIO/EchoCtrl - Config Register

Enumerator
ECHO_PATH_THRU 
ECHO_STORE_FWD 
ECHO_OFF 
ECHO_PATH_THRU 
ECHO_STORE_FWD 
ECHO_OFF 
ECHO_PATH_THRU 
ECHO_STORE_FWD 
ECHO_OFF 
ECHO_PATH_THRU 
ECHO_STORE_FWD 
ECHO_OFF 
ECHO_PATH_THRU 
ECHO_STORE_FWD 
ECHO_OFF 
ECHO_PATH_THRU 
ECHO_STORE_FWD 
ECHO_OFF 
ECHO_PATH_THRU 
ECHO_STORE_FWD 
ECHO_OFF 
ECHO_STORE_FWD 
ECHO_PATH_THRU 
ECHO_CTRL_DISABLED 
ECHO_PATH_THRU 
ECHO_STORE_FWD 
ECHO_OFF 

Definition at line 60 of file median_blur.hpp.

60  {
61  ECHO_PATH_THRU = 0,
62  ECHO_STORE_FWD = 1,
63  ECHO_OFF = 2
64 };
ECHO_STORE_FWD
@ ECHO_STORE_FWD
Definition: median_blur.hpp:62
ECHO_OFF
@ ECHO_OFF
Definition: median_blur.hpp:63
ECHO_PATH_THRU
@ ECHO_PATH_THRU
Definition: median_blur.hpp:61

Function Documentation

◆ median_blur()

void median_blur ( ap_uint< 32 > *  pi_rank,
ap_uint< 32 > *  pi_size,
stream< NetworkWord > &  siSHL_This_Data,
stream< NetworkWord > &  soTHIS_Shl_Data,
stream< NetworkMetaStream > &  siNrc_meta,
stream< NetworkMetaStream > &  soNrc_meta,
ap_uint< 32 > *  po_rx_ports,
stream< DmCmd > &  soMemWrCmdP0,
stream< DmSts > &  siMemWrStsP0,
stream< Axis< 512 > > &  soMemWriteP0,
membus_t *  lcl_mem0,
membus_t *  lcl_mem1 
)

Main process of the MedianBlur Application directives.

Deprecated:
This functions is using deprecated AXI stream interface
Returns
Nothing.

Definition at line 1146 of file median_blur.cpp.

1179 {
1180 
1181 
1182 //-- DIRECTIVES FOR THE BLOCK ---------------------------------------------
1183 //#pragma HLS INTERFACE ap_ctrl_none port=return
1184 
1185 //#pragma HLS INTERFACE ap_stable port=piSHL_This_MmioEchoCtrl
1186 
1187 #pragma HLS INTERFACE axis register both port=siSHL_This_Data
1188 #pragma HLS INTERFACE axis register both port=soTHIS_Shl_Data
1189 
1190 #pragma HLS INTERFACE axis register both port=siNrc_meta
1191 #pragma HLS INTERFACE axis register both port=soNrc_meta
1192 
1193 #pragma HLS INTERFACE ap_ovld register port=po_rx_ports name=poROL_NRC_Rx_ports
1194 
1195 #if HLS_VERSION < 20211
1196 #pragma HLS INTERFACE ap_stable register port=pi_rank name=piFMC_ROL_rank
1197 #pragma HLS INTERFACE ap_stable register port=pi_size name=piFMC_ROL_size
1198 #elif HLS_VERSION >= 20211
1199  #pragma HLS stable variable=pi_rank
1200  #pragma HLS stable variable=pi_size
1201 #else
1202  printf("ERROR: Invalid HLS_VERSION=%s\n", HLS_VERSION);
1203  exit(-1);
1204 #endif
1205 
1206 #ifdef ENABLE_DDR
1207 
1208 // Bundling: SHELL / Role / Mem / Mp0 / Read Interface
1209 // #pragma HLS INTERFACE axis register both port=soMemRdCmdP0
1210 // #pragma HLS INTERFACE axis register both port=siMemRdStsP0
1211 // #pragma HLS INTERFACE axis register both port=siMemReadP0
1212 
1213 // #pragma HLS DATA_PACK variable=soMemRdCmdP0 instance=soMemRdCmdP0
1214 // #pragma HLS DATA_PACK variable=siMemRdStsP0 instance=siMemRdStsP0
1215 
1216 // Bundling: SHELL / Role / Mem / Mp0 / Write Interface
1217 #pragma HLS INTERFACE axis register both port=soMemWrCmdP0
1218 #pragma HLS INTERFACE axis register both port=siMemWrStsP0
1219 #pragma HLS INTERFACE axis register both port=soMemWriteP0
1220 
1221 #if HLS_VERSION <= 20201
1222 #pragma HLS DATA_PACK variable=soMemWrCmdP0 instance=soMemWrCmdP0
1223 #pragma HLS DATA_PACK variable=siMemWrStsP0 instance=siMemWrStsP0
1224 #elif HLS_VERSION >= 20211
1225 #pragma HLS aggregate variable=soMemWrCmdP0 compact=bit
1226 #pragma HLS aggregate variable=siMemWrStsP0 compact=bit
1227 #else
1228  printf("ERROR: Invalid HLS_VERSION=%s\n", HLS_VERSION);
1229  exit(-1);
1230 #endif
1231 
1232 const unsigned int ddr_mem_depth = TOTMEMDW_512;
1233 const unsigned int ddr_latency = DDR_LATENCY;
1234 
1235 
1236 // When max burst size is 1KB, with 512bit bus we get 16 burst transactions
1237 // When max burst size is 4KB, with 512bit bus we get 64 burst transactions
1238 const unsigned int max_axi_rw_burst_length = 64;
1239 
1240 // Mapping LCL_MEM0 interface to moMEM_Mp1 channel
1241 #pragma HLS INTERFACE m_axi depth=ddr_mem_depth port=lcl_mem0 bundle=moMEM_Mp1\
1242  max_read_burst_length=max_axi_rw_burst_length max_write_burst_length=max_axi_rw_burst_length offset=direct \
1243  num_read_outstanding=16 num_write_outstanding=16 latency=ddr_latency
1244 
1245 // Mapping LCL_MEM1 interface to moMEM_Mp1 channel
1246 #pragma HLS INTERFACE m_axi depth=ddr_mem_depth port=lcl_mem1 bundle=moMEM_Mp1 \
1247  max_read_burst_length=max_axi_rw_burst_length max_write_burst_length=max_axi_rw_burst_length offset=direct \
1248  num_read_outstanding=16 num_write_outstanding=16 latency=ddr_latency
1249 
1250 #endif
1251 
1252  #pragma HLS DATAFLOW
1253 
1254  //-- LOCAL VARIABLES ------------------------------------------------------
1255  NetworkMetaStream meta_tmp = NetworkMetaStream();
1256  static stream<NetworkWord> sRxpToTxp_Data("sRxpToTxP_Data"); // FIXME: works even with no static
1257  static stream<NetworkMetaStream> sRxtoTx_Meta("sRxtoTx_Meta");
1258  static unsigned int processed_word_rx;
1259  static unsigned int processed_bytes_rx;
1260  static unsigned int processed_word_tx = 0;
1261  static stream<bool> sImageLoaded("sImageLoaded");
1262  static bool skip_read;
1263  static bool write_chunk_to_ddr_pending;
1264  static bool ready_to_accept_new_data;
1265  static bool signal_init;
1266  const int tot_transfers = TOT_TRANSFERS;
1267 #ifdef ENABLE_DDR
1268  static stream<ap_uint<MEMDW_512>> img_in_axi_stream ("img_in_axi_stream");
1269  const unsigned int img_in_axi_stream_depth = TRANSFERS_PER_CHUNK; // the AXI burst size
1270  static stream<bool> sMemBurstRx("sMemBurstRx");
1271 
1272 #else
1273  const int img_in_axi_stream_depth = MIN_RX_LOOPS;
1274  const int img_out_axi_stream_depth = MIN_TX_LOOPS;
1275 #ifdef USE_HLSLIB_DATAFLOW
1276  static hlslib::Stream<Data_t_in, MIN_RX_LOOPS> img_in_axi_stream ("img_in_axi_stream");
1277  static hlslib::Stream<Data_t_out, MIN_TX_LOOPS> img_out_axi_stream ("img_out_axi_stream");
1278 #else
1279  static stream<ap_uint<INPUT_PTR_WIDTH>> img_in_axi_stream ("img_in_axi_stream");
1280  static stream<ap_uint<OUTPUT_PTR_WIDTH>> img_out_axi_stream ("img_out_axi_stream");
1281 #endif
1282 #endif
1283 
1284 
1285 //-- DIRECTIVES FOR THIS PROCESS ------------------------------------------
1286 #pragma HLS stream variable=sRxtoTx_Meta depth=tot_transfers
1287 #pragma HLS reset variable=enqueueFSM
1288 #pragma HLS reset variable=dequeueFSM
1289 #pragma HLS reset variable=MedianBlurFSM
1290 #pragma HLS reset variable=processed_word_rx
1291 #pragma HLS reset variable=processed_word_tx
1292 #pragma HLS reset variable=processed_bytes_rx
1293 //#pragma HLS reset variable=image_loaded
1294 #pragma HLS stream variable=sImageLoaded depth=1
1295 #pragma HLS reset variable=skip_read
1296 #pragma HLS reset variable=write_chunk_to_ddr_pending
1297 //#pragma HLS stream variable=sWriteChunkToDdrPending depth=2
1298 #pragma HLS reset variable=ready_to_accept_new_data
1299 #pragma HLS reset variable=signal_init
1300 
1301 #ifdef ENABLE_DDR
1302 #pragma HLS stream variable=img_in_axi_stream depth=img_in_axi_stream_depth
1303 #pragma HLS stream variable=sProcessed_bytes_rx depth=img_in_axi_stream_depth
1304 #else
1305 #pragma HLS stream variable=img_in_axi_stream depth=img_in_axi_stream_depth
1306 #pragma HLS stream variable=img_out_axi_stream depth=img_out_axi_stream_depth
1307 #endif
1308 
1309 
1310 #ifdef USE_HLSLIB_DATAFLOW
1326  // Dataflow functions running in parallel
1327  HLSLIB_DATAFLOW_INIT();
1328 
1329  HLSLIB_DATAFLOW_FUNCTION(pRXPath,
1330  siSHL_This_Data,
1331  siNrc_meta,
1332  sRxtoTx_Meta,
1333  img_in_axi_stream,
1334  meta_tmp,
1335  &processed_word_rx,
1336  &processed_bytes_rx,
1337  //&image_loaded
1338  sImageLoaded
1339  );
1340 
1341  HLSLIB_DATAFLOW_FUNCTION(pProcPath,
1342  sRxpToTxp_Data,
1343 #ifdef ENABLE_DDR
1344  lcl_mem0,
1345  lcl_mem1,
1346 #else
1347  img_in_axi_stream,
1348  img_out_axi_stream,
1349 #endif
1350  &image_loaded
1351  );
1352 
1353  HLSLIB_DATAFLOW_FUNCTION(pTXPath,
1354  soTHIS_Shl_Data,
1355  soNrc_meta,
1356  sRxpToTxp_Data,
1357  sRxtoTx_Meta,
1358  &processed_word_tx,
1359  pi_rank,
1360  pi_size);
1361 
1362  HLSLIB_DATAFLOW_FINALIZE();
1363 
1364 #else // !USE_HLSLIB_DATAFLOW
1365 
1366  pPortAndDestionation(
1367  pi_rank,
1368  pi_size,
1369  po_rx_ports
1370  );
1371 
1372 #ifdef ENABLE_DDR
1373  /*
1374  pRXPathDDR(
1375  siSHL_This_Data,
1376  siNrc_meta,
1377  sRxtoTx_Meta,
1378  //---- P0 Write Path (S2MM) -----------
1379  soMemWrCmdP0,
1380  siMemWrStsP0,
1381  soMemWriteP0,
1382  // ---- P1 Memory mapped --------------
1383  meta_tmp,
1384  &processed_bytes_rx,
1385  sImageLoaded
1386  );
1387  */
1388  pRXPathNetToStream(
1389  siSHL_This_Data,
1390  siNrc_meta,
1391  sRxtoTx_Meta,
1392  img_in_axi_stream,
1393  sMemBurstRx
1394  );
1395 
1396  pRXPathStreamToDDR(
1397  img_in_axi_stream,
1398  sMemBurstRx,
1399  //---- P0 Write Path (S2MM) -----------
1400  soMemWrCmdP0,
1401  siMemWrStsP0,
1402  soMemWriteP0,
1403  //---- P1 Memory mapped ---------------
1404  //&processed_bytes_rx,
1405  sImageLoaded
1406  );
1407 
1408 
1409 
1410  #else // !ENABLE_DDR
1411 
1412  pRXPath(
1413  siSHL_This_Data,
1414  siNrc_meta,
1415  sRxtoTx_Meta,
1416  img_in_axi_stream,
1417  meta_tmp,
1418  &processed_word_rx,
1419  &processed_bytes_rx,
1420  sImageLoaded
1421  );
1422 
1423 #endif // ENABLE_DDR
1424 
1425  pProcPath(
1426  sRxpToTxp_Data,
1427 #ifdef ENABLE_DDR
1428  lcl_mem0,
1429  lcl_mem1,
1430 #else
1431  img_in_axi_stream,
1432  img_out_axi_stream,
1433 #endif
1434  sImageLoaded
1435  );
1436 
1437  pTXPath(
1438  soTHIS_Shl_Data,
1439  soNrc_meta,
1440  sRxpToTxp_Data,
1441  sRxtoTx_Meta,
1442  &processed_word_tx,
1443  pi_rank,
1444  pi_size
1445  );
1446 
1447 #endif // USE_HLSLIB_DATAFLOW
1448 }
TRANSFERS_PER_CHUNK
#define TRANSFERS_PER_CHUNK
Definition: harris.hpp:133
MIN_TX_LOOPS
#define MIN_TX_LOOPS
Definition: mceuropeanengine.hpp:88
MIN_RX_LOOPS
#define MIN_RX_LOOPS
Definition: mceuropeanengine.hpp:87
TOT_TRANSFERS
#define TOT_TRANSFERS
Definition: config.h:70
pPortAndDestionation
void pPortAndDestionation(ap_uint< 32 > *pi_rank, ap_uint< 32 > *pi_size, ap_uint< 32 > *po_rx_ports)
Definition: median_blur.cpp:63
pTXPath
void pTXPath(stream< NetworkWord > &soTHIS_Shl_Data, stream< NetworkMetaStream > &soNrc_meta, stream< NetworkWord > &sRxpToTxp_Data, stream< NetworkMetaStream > &sRxtoTx_Meta, unsigned int *processed_word_tx, ap_uint< 32 > *pi_rank, ap_uint< 32 > *pi_size)
Transmit Path - From THIS to SHELL.
Definition: median_blur.cpp:1020
pRXPath
void pRXPath(stream< NetworkWord > &siSHL_This_Data, stream< NetworkMetaStream > &siNrc_meta, stream< NetworkMetaStream > &sRxtoTx_Meta, stream< ap_uint< 8 >> &img_in_axi_stream, NetworkMetaStream meta_tmp, unsigned int *processed_word_rx, unsigned int *processed_bytes_rx, stream< bool > &sImageLoaded)
Receive Path - From SHELL to THIS.
Definition: median_blur.cpp:751
pRXPathNetToStream
void pRXPathNetToStream(stream< NetworkWord > &siSHL_This_Data, stream< NetworkMetaStream > &siNrc_meta, stream< NetworkMetaStream > &sRxtoTx_Meta, stream< ap_uint< 512 >> &img_in_axi_stream, stream< bool > &sMemBurstRx)
Receive Path - From SHELL to THIS.
Definition: median_blur.cpp:432
pProcPath
void pProcPath(stream< NetworkWord > &sRxpToTxp_Data, membus_t *lcl_mem0, membus_t *lcl_mem1, stream< bool > &sImageLoaded)
Processing Path - Main processing FSM for Vitis kernels.
Definition: median_blur.cpp:818
pRXPathStreamToDDR
void pRXPathStreamToDDR(stream< ap_uint< 512 >> &img_in_axi_stream, stream< bool > &sMemBurstRx, stream< DmCmd > &soMemWrCmdP0, stream< DmSts > &siMemWrStsP0, stream< Axis< 512 > > &soMemWriteP0, stream< bool > &sImageLoaded)
Receive Path - From SHELL to THIS.
Definition: median_blur.cpp:530
DDR_LATENCY
#define DDR_LATENCY
Definition: memtest.hpp:98
ENABLE_DDR
#define ENABLE_DDR
Definition: memtest.hpp:42
TOTMEMDW_512
#define TOTMEMDW_512
Definition: memtest.hpp:93
lcl_mem0
membus_t lcl_mem0[16384]
Definition: test_memtest.cpp:87
lcl_mem1
membus_t lcl_mem1[16384]
Definition: test_memtest.cpp:88
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◆ median_blur_accel()

void median_blur_accel ( xf::cv::Mat< XF_8UC1, 1024, 1024, XF_NPPC1 > &  imgInput,
xf::cv::Mat< XF_8UC1, 1024, 1024, XF_NPPC1 > &  imgOutput 
)

Top-level accelerated function of the MedianBlur Application with xf::cv I/F.

Returns
Nothing.

Definition at line 66 of file xf_median_blur_accel.cpp.

67  {
68 
69  // Run xfOpenCV kernel:
70  xf::cv::medianBlur<WINDOW_SIZE, XF_BORDER_REPLICATE, TYPE, HEIGHT, WIDTH, NPC1>(imgInput, imgOutput);
71 
72 }
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◆ medianBlurAccelArray()

void medianBlurAccelArray ( ap_uint< 8 > *  img_in,
ap_uint< 64 > *  img_out,
int  rows,
int  cols 
)

Top-level accelerated function of the MedianBlur Application with array I/F.

Returns
Nothing.

Definition at line 83 of file xf_median_blur_accel.cpp.

84  {
85 // clang-format off
86 // #pragma HLS INTERFACE m_axi port=img_in offset=slave bundle=gmem0 depth=__XF_DEPTH
87 // #pragma HLS INTERFACE m_axi port=img_out offset=slave bundle=gmem1 depth=__XF_DEPTH
88 // #pragma HLS INTERFACE s_axilite port=rows bundle=control
89 // #pragma HLS INTERFACE s_axilite port=cols bundle=contro
90 // #pragma HLS INTERFACE s_axilite port=return bundle=control
91 // clang-format on
92 
93  const int pROWS = HEIGHT;
94  const int pCOLS = WIDTH;
95  const int pNPC1 = NPIX;
96 
97  xf::cv::Mat<XF_8UC1, HEIGHT, WIDTH, NPIX> imgInput(rows, cols);
98 // clang-format off
99  #pragma HLS stream variable=imgInput.data depth=2
100  // clang-format on
101 
102  xf::cv::Mat<XF_8UC1, HEIGHT, WIDTH, NPIX> imgOutput(rows, cols);
103 // clang-format off
104  #pragma HLS stream variable=imgOutput.data depth=2
105 // clang-format on
106 
107 // clang-format off
108  #pragma HLS DATAFLOW
109  // clang-format on
110  xf::cv::Array2xfMat<INPUT_PTR_WIDTH, TYPE, HEIGHT, WIDTH, NPC1>(img_in, imgInput);
111  xf::cv::medianBlur<WINDOW_SIZE, XF_BORDER_REPLICATE, TYPE, HEIGHT, WIDTH, NPC1>(imgInput, imgOutput);
112  xf::cv::xfMat2Array<OUTPUT_PTR_WIDTH, XF_8UC1, HEIGHT, WIDTH, NPIX>(imgOutput, img_out);
113 }
WIDTH
#define WIDTH
Definition: xf_gammacorrection_config.h:64
NPIX
#define NPIX
Definition: xf_gammacorrection_config.h:61
HEIGHT
#define HEIGHT
Definition: xf_gammacorrection_config.h:65
test_harris_standalone.rows
rows
Definition: test_harris_standalone.py:167
test_harris_standalone.cols
cols
Definition: test_harris_standalone.py:167
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◆ medianBlurAccelMem()

void medianBlurAccelMem ( membus_t *  img_inp,
membus_t *  img_out,
int  rows,
int  cols 
)

Top-level accelerated function of the MedianBlur Application with array I/F.

Returns
Nothing.

Definition at line 222 of file xf_median_blur_accel.cpp.

224  {
225  // clang-format on
226  #pragma HLS INLINE off
227 
228  xf::cv::Mat<TYPE, HEIGHT, WIDTH, NPIX> imgInput(rows, cols);
229  // clang-format off
230  #pragma HLS stream variable=imgInput.data depth=2
231  // clang-format on
232 
233  #ifndef FAKE_MedianBlur
234  xf::cv::Mat<TYPE, HEIGHT, WIDTH, NPIX> imgOutput(rows, cols);
235  // clang-format off
236  #pragma HLS stream variable=imgOutput.data depth=2
237  // clang-format on
238  #endif
239 
240  // clang-format off
241  #pragma HLS DATAFLOW
242  // clang-format on
243 
244  // Feed a cv matrix from ddr memory
245  xf::cv::Array2xfMat<MEMDW_512, XF_8UC1, HEIGHT, WIDTH, NPIX>(img_inp, imgInput);
246 
247  #ifdef FAKE_MedianBlur
248 
249  // Feed ddr memory from a cv matrix
250  xf::cv::xfMat2Array<MEMDW_512, XF_8UC1, HEIGHT, WIDTH, NPIX>(imgInput, img_out);
251  #else
252 
253  xf::cv::medianBlur<WINDOW_SIZE, XF_BORDER_REPLICATE, TYPE, HEIGHT, WIDTH, NPC1>(imgInput, imgOutput);
254 
255  // Feed ddr memory from a cv matrix
256  xf::cv::xfMat2Array<MEMDW_512, XF_8UC1, HEIGHT, WIDTH, NPIX>(imgOutput, img_out);
257 
258  #endif
259 
260 
261 }
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◆ medianBlurAccelStream()

void medianBlurAccelStream ( hls::stream< ap_uint< 8 >> &  img_in_axi_stream,
hls::stream< ap_uint< 64 >> &  img_out_axi_stream,
int  rows,
int  cols 
)

Top-level accelerated function of the MedianBlur Application with array I/F.

Returns
Nothing.

Definition at line 127 of file xf_median_blur_accel.cpp.

130  {
131  // clang-format on
132  #pragma HLS INLINE off
133 
134  xf::cv::Mat<TYPE, HEIGHT, WIDTH, NPIX> imgInput(rows, cols);
135  // clang-format off
136  #pragma HLS stream variable=imgInput.data depth=2
137  // clang-format on
138 
139  xf::cv::Mat<TYPE, HEIGHT, WIDTH, NPIX> imgOutput(rows, cols);
140  // clang-format off
141  #pragma HLS stream variable=imgOutput.data depth=2
142  // clang-format on
143 
144  // clang-format off
145  #pragma HLS DATAFLOW
146  // clang-format on
147 
148  accel_utils accel_utils_obj;
149 
150  int dstMat_cols_align_npc = ((imgInput.cols + (NPIX - 1)) >> XF_BITSHIFT(NPIX)) << XF_BITSHIFT(NPIX);
151 
152  accel_utils_obj.hlsStrm2xfMat<INPUT_PTR_WIDTH, TYPE, HEIGHT, WIDTH, NPIX, (HEIGHT * WIDTH) / NPIX>(img_in_axi_stream, imgInput, dstMat_cols_align_npc);
153 
154  xf::cv::medianBlur<WINDOW_SIZE, XF_BORDER_REPLICATE, TYPE, HEIGHT, WIDTH, NPC1>(imgInput, imgOutput);
155 
156  int srcMat_cols_align_npc = ((imgOutput.cols + (NPIX - 1)) >> XF_BITSHIFT(NPIX)) << XF_BITSHIFT(NPIX);
157 
158  accel_utils_obj.xfMat2hlsStrm<OUTPUT_PTR_WIDTH, TYPE, HEIGHT, WIDTH, NPIX, HEIGHT*((WIDTH + NPIX - 1) / NPIX)>(imgOutput, img_out_axi_stream,
159  srcMat_cols_align_npc);
160 }
INPUT_PTR_WIDTH
#define INPUT_PTR_WIDTH
Definition: mceuropeanengine.hpp:71
OUTPUT_PTR_WIDTH
#define OUTPUT_PTR_WIDTH
Definition: mceuropeanengine.hpp:75
TYPE
#define TYPE
Definition: xf_median_blur_config.h:89
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◆ pPortAndDestionation()

void pPortAndDestionation ( ap_uint< 32 > *  pi_rank,
ap_uint< 32 > *  pi_size,
ap_uint< 32 > *  po_rx_ports 
)

Definition at line 63 of file median_blur.cpp.

68 {
69  //-- DIRECTIVES FOR THIS PROCESS ------------------------------------------
70 #pragma HLS inline off
71 #pragma HLS pipeline II=1 //TODO: check not necessary
72  *po_rx_ports = PORTS_OPENED;
73 }
PORTS_OPENED
#define PORTS_OPENED
Definition: harris.hpp:102
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◆ pProcPath()

void pProcPath ( stream< NetworkWord > &  sRxpToTxp_Data,
membus_t *  lcl_mem0,
membus_t *  lcl_mem1,
stream< bool > &  sImageLoaded 
)

Processing Path - Main processing FSM for Vitis kernels.

Parameters
[out]sRxpToTxp_Data
[in]img_in_axi_stream
[in]img_out_axi_stream
[out]processed_word_rx
[in]sImageLoaded
Returns
Nothing.

Definition at line 818 of file median_blur.cpp.

837 {
838  //-- DIRECTIVES FOR THIS PROCESS ------------------------------------------
839  #pragma HLS INLINE off
840  #pragma HLS pipeline II=1
841 
842  //-- LOCAL VARIABLES ------------------------------------------------------
843  NetworkWord newWord;
844  uint16_t Thresh = 442;
845  float K = 0.04;
846  uint16_t k = K * (1 << 16); // Convert to Q0.16 format
847  static bool accel_called;
848  static unsigned int processed_word_proc;
849  static unsigned int timeoutCntAbs;
850  static unsigned int cnt_i;
851  static membus_t tmp;
852  ap_uint<OUTPUT_PTR_WIDTH> raw64;
853  Data_t_out temp;
854  #ifdef ENABLE_DDR
855  //static stream<ap_uint<OUTPUT_PTR_WIDTH>> img_out_axi_stream ("img_out_axi_stream");
856  //#pragma HLS stream variable=img_out_axi_stream depth=9
857  static unsigned int ddr_addr_out;
858  #pragma HLS reset variable=ddr_addr_out
859  #endif
860 
861  #pragma HLS reset variable=accel_called
862  #pragma HLS reset variable=processed_word_proc
863  #pragma HLS reset variable=timeoutCntAbs
864  #pragma HLS reset variable=cnt_i
865  #pragma HLS reset variable=tmp
866  #pragma HLS reset variable=raw64
867  #pragma HLS reset variable=temp
868 
869  switch(MedianBlurFSM)
870  {
871  case WAIT_FOR_META:
872  printf("DEBUG in pProcPath: WAIT_FOR_META\n");
873  if (!sImageLoaded.empty())
874  {
875  if (sImageLoaded.read() == true) {
876  MedianBlurFSM = PROCESSING_PACKET;
877  accel_called = false;
878  processed_word_proc = 0;
879  #ifdef ENABLE_DDR
880  ddr_addr_out = 0;
881  timeoutCntAbs = 0;
882  cnt_i = 0;
883  #endif
884  }
885  }
886  break;
887 
888  case PROCESSING_PACKET:
889  printf("DEBUG in pProcPath: PROCESSING_PACKET\n");
890  #ifndef ENABLE_DDR
891  if ( !img_in_axi_stream.empty() && !img_out_axi_stream.full() )
892  {
893  #endif
894  if (accel_called == false) {
895  #ifdef ENABLE_DDR
896  medianBlurAccelMem(lcl_mem0, lcl_mem1, WIDTH, HEIGHT);
897  #else // ! ENABLE_DDR
898  #ifdef FAKE_MedianBlur
899  fakeMedianBlurAccelStream(img_in_axi_stream, img_out_axi_stream, MIN_RX_LOOPS, MIN_TX_LOOPS);
900  #else // !FAKE_MedianBlur
901  medianBlurAccelStream(img_in_axi_stream, img_out_axi_stream, WIDTH, HEIGHT);
902  #endif // FAKE_MedianBlur
903  #endif // ENABLE_DDR
904  accel_called = true;
905  MedianBlurFSM = MEDIANBLUR_RETURN_RESULTS;
906  }
907  #ifndef ENABLE_DDR
908  }
909  #endif
910  break;
911 
912  #ifdef ENABLE_DDR
913  case MEDIANBLUR_RETURN_RESULTS:
914  printf("DEBUG in pProcPath: MEDIANBLUR_RETURN_RESULTS, ddr_addr_out=%u\n", ddr_addr_out);
915  if (accel_called == true) {
916 
917  printf("DEBUG in pProcPath: Accumulated %u net words (%u B) to complete a single DDR word\n",
918  KWPERMDW_512, BPERMDW_512);
919  tmp = lcl_mem1[ddr_addr_out];
920  ddr_addr_out++;
921  MedianBlurFSM = MEDIANBLUR_RETURN_RESULTS_ABSORB_DDR_LAT;
922  timeoutCntAbs = 0;
923  }
924  break;
925 
926  case MEDIANBLUR_RETURN_RESULTS_ABSORB_DDR_LAT:
927  printf("DEBUG in pProcPath: MEDIANBLUR_RETURN_RESULTS_ABSORB_DDR_LAT [%u out of %u]\n", timeoutCntAbs, DDR_LATENCY);
928  if (timeoutCntAbs++ == DDR_LATENCY) {
929  MedianBlurFSM = MEDIANBLUR_RETURN_RESULTS_FWD; //MEDIANBLUR_RETURN_RESULTS_UNPACK;
930  cnt_i = 0;
931  }
932  break;
933  /*
934  case MEDIANBLUR_RETURN_RESULTS_UNPACK:
935  printf("DEBUG in pProcPath: MEDIANBLUR_RETURN_RESULTS_UNPACK, cnt_i=%u\n", cnt_i);
936  //for (unsigned int cnt_i=0; cnt_i<(MEMDW_512/OUTPUT_PTR_WIDTH); cnt_i++) {
937  #if OUTPUT_PTR_WIDTH == 64
938  raw64(0 ,63) = tmp(cnt_i*OUTPUT_PTR_WIDTH , cnt_i*OUTPUT_PTR_WIDTH+63);
939  #endif
940  if ( !img_out_axi_stream.full() ) {
941  img_out_axi_stream.write(raw64);
942  }
943  if (cnt_i == (MEMDW_512/OUTPUT_PTR_WIDTH) - 1) {
944  MedianBlurFSM = MEDIANBLUR_RETURN_RESULTS_FWD;
945  }
946  cnt_i++;
947  //}
948  break;
949  */
950  case MEDIANBLUR_RETURN_RESULTS_FWD:
951  printf("DEBUG in pProcPath: MEDIANBLUR_RETURN_RESULTS_FWD\n");
952  //if ( !img_out_axi_stream.empty() && !sRxpToTxp_Data.full() ) {
953  if ( (cnt_i <= (MEMDW_512/OUTPUT_PTR_WIDTH) - 1) && !sRxpToTxp_Data.full() ) {
954 
955  //temp.data = img_out_axi_stream.read();
956  temp.data(0 ,63) = tmp(cnt_i*OUTPUT_PTR_WIDTH , cnt_i*OUTPUT_PTR_WIDTH+63);
957  if (processed_word_proc++ == MIN_TX_LOOPS-1) {
958  temp.last = 1;
959  MedianBlurFSM = WAIT_FOR_META;
960  }
961  else {
962  temp.last = 0;
963  }
964  //TODO: find why Vitis kernel does not set keep and last by itself
965  temp.keep = 255;
966  newWord = NetworkWord(temp.data, temp.keep, temp.last);
967  sRxpToTxp_Data.write(newWord);
968  cnt_i++;
969  }
970  else {
971  MedianBlurFSM = MEDIANBLUR_RETURN_RESULTS;
972  }
973 
974  break;
975 
976  #else // ! ENABLE_DDR
977  case MEDIANBLUR_RETURN_RESULTS:
978  printf("DEBUG in pProcPath: MEDIANBLUR_RETURN_RESULTS\n");
979  if ( !img_out_axi_stream.empty() && !sRxpToTxp_Data.full() )
980  {
981 
982  temp.data = img_out_axi_stream.read();
983  if ( img_out_axi_stream.empty() )
984  //if (processed_word_proc++ == MIN_TX_LOOPS-1)
985  {
986  temp.last = 1;
987  MedianBlurFSM = WAIT_FOR_META;
988  accel_called = false;
989  }
990  else
991  {
992  temp.last = 0;
993  }
994  //TODO: find why Vitis kernel does not set keep and last by itself
995  temp.keep = 255;
996  newWord = NetworkWord(temp.data, temp.keep, temp.last);
997  sRxpToTxp_Data.write(newWord);
998  }
999  break;
1000  #endif // ENABLE_DDR
1001  } // end switch
1002 
1003 }
BPERMDW_512
#define BPERMDW_512
Definition: harris.hpp:120
KWPERMDW_512
#define KWPERMDW_512
Definition: harris.hpp:121
MEDIANBLUR_RETURN_RESULTS_ABSORB_DDR_LAT
#define MEDIANBLUR_RETURN_RESULTS_ABSORB_DDR_LAT
Definition: median_blur.hpp:72
MedianBlurFSM
uint8_t MedianBlurFSM
Definition: median_blur.cpp:53
MEDIANBLUR_RETURN_RESULTS_FWD
#define MEDIANBLUR_RETURN_RESULTS_FWD
Definition: median_blur.hpp:74
MEDIANBLUR_RETURN_RESULTS
#define MEDIANBLUR_RETURN_RESULTS
Definition: median_blur.hpp:71
fakeMedianBlurAccelStream
void fakeMedianBlurAccelStream(hls::stream< ap_axiu< 8, 0, 0, 0 > > &img_in_axi_stream, hls::stream< ap_axiu< 64, 0, 0, 0 > > &img_out_axi_stream, unsigned int min_rx_loops, unsigned int min_tx_loops)
medianBlurAccelMem
void medianBlurAccelMem(membus_t *img_inp, membus_t *img_out, int rows, int cols)
Top-level accelerated function of the MedianBlur Application with array I/F.
Definition: xf_median_blur_accel.cpp:222
medianBlurAccelStream
void medianBlurAccelStream(hls::stream< ap_uint< 8 >> &img_in_axi_stream, hls::stream< ap_uint< 64 >> &img_out_axi_stream, int rows, int cols)
Top-level accelerated function of the MedianBlur Application with array I/F.
Definition: xf_median_blur_accel.cpp:127
MEMDW_512
#define MEMDW_512
Definition: memtest.hpp:90
Data_t_out
#define Data_t_out
Definition: memtest.cpp:30
membus_t
membus_512_t membus_t
Definition: memtest.hpp:92
PROCESSING_PACKET
#define PROCESSING_PACKET
Definition: memtest.hpp:73
WAIT_FOR_META
#define WAIT_FOR_META
Definition: memtest.hpp:71
test_harris_standalone.tmp
tmp
Definition: test_harris_standalone.py:101
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◆ pRXPath()

void pRXPath ( stream< NetworkWord > &  siSHL_This_Data,
stream< NetworkMetaStream > &  siNrc_meta,
stream< NetworkMetaStream > &  sRxtoTx_Meta,
stream< ap_uint< 8 >> &  img_in_axi_stream,
NetworkMetaStream  meta_tmp,
unsigned int *  processed_word_rx,
unsigned int *  processed_bytes_rx,
stream< bool > &  sImageLoaded 
)

Receive Path - From SHELL to THIS.

Parameters
[in]siSHL_This_Data
[in]siNrc_meta
[out]sRxtoTx_Meta
[out]img_in_axi_stream
[out]meta_tmp
[out]processed_word
[out]sImageLoaded
Returns
Nothing.

Definition at line 751 of file median_blur.cpp.

766 {
767  //-- DIRECTIVES FOR THIS PROCESS ------------------------------------------
768  #pragma HLS INLINE off
769  #pragma HLS pipeline II=1
770 
771  //-- LOCAL VARIABLES ------------------------------------------------------
772  static NetworkWord netWord;
773 
774  switch(enqueueFSM)
775  {
776  case WAIT_FOR_META:
777  printf("DEBUG in pRXPath: enqueueFSM - WAIT_FOR_META, *processed_word_rx=%u, *processed_bytes_rx=%u\n",
778  *processed_word_rx, *processed_bytes_rx);
779  if ( !siNrc_meta.empty() && !sRxtoTx_Meta.full() )
780  {
781  meta_tmp = siNrc_meta.read();
782  meta_tmp.tlast = 1; //just to be sure...
783  sRxtoTx_Meta.write(meta_tmp);
784  enqueueFSM = PROCESSING_PACKET;
785  }
786  break;
787 
788  case PROCESSING_PACKET:
789  printf("DEBUG in pRXPath: enqueueFSM - PROCESSING_PACKET, *processed_word_rx=%u, *processed_bytes_rx=%u\n",
790  *processed_word_rx, *processed_bytes_rx);
791  if ( !siSHL_This_Data.empty() && !img_in_axi_stream.full())
792  {
793  //-- Read incoming data chunk
794  netWord = siSHL_This_Data.read();
795  storeWordToAxiStream(netWord, img_in_axi_stream, processed_word_rx, processed_bytes_rx,
796  sImageLoaded);
797  if(netWord.tlast == 1)
798  {
799  enqueueFSM = WAIT_FOR_META;
800  }
801  }
802  break;
803  }
804 }
enqueueFSM
uint8_t enqueueFSM
Definition: median_blur.cpp:51
storeWordToAxiStream
void storeWordToAxiStream(NetworkWord word, stream< ap_uint< 8 >> &img_in_axi_stream, unsigned int *processed_word_rx, unsigned int *processed_bytes_rx, stream< bool > &sImageLoaded)
Store a net word to a local AXI stream.
Definition: median_blur.cpp:105
NetworkMetaStream::tlast
ap_uint< 1 > tlast
Definition: network.hpp:111
NetworkWord::tlast
ap_uint< 1 > tlast
Definition: network.hpp:51
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◆ pRXPathDDROLD()

void pRXPathDDROLD ( stream< NetworkWord > &  siSHL_This_Data,
stream< NetworkMetaStream > &  siNrc_meta,
stream< NetworkMetaStream > &  sRxtoTx_Meta,
stream< DmCmd > &  soMemWrCmdP0,
stream< DmSts > &  siMemWrStsP0,
stream< Axis< 512 > > &  soMemWriteP0,
NetworkMetaStream  meta_tmp,
unsigned int *  processed_bytes_rx,
stream< bool > &  sImageLoaded 
)

Receive Path - From SHELL to THIS.

Parameters
[in]siSHL_This_Data
[in]siNrc_meta
[out]sRxtoTx_Meta
[out]img_in_axi_stream
[out]meta_tmp
[out]processed_word
[out]sImageLoaded
Returns
Nothing.

Definition at line 178 of file median_blur.cpp.

191 {
192  //-- DIRECTIVES FOR THIS PROCESS ------------------------------------------
193  #pragma HLS INLINE off
194  #pragma HLS pipeline II=1
195  #pragma HLS interface ap_ctrl_none port=return
196 
197  //-- LOCAL VARIABLES ------------------------------------------------------
198  static NetworkWord netWord;
199 
200  static ap_uint<MEMDW_512> v = 0;
201  const unsigned int loop_cnt = (MEMDW_512/BITS_PER_10GBITETHRNET_AXI_PACKET);
202  const unsigned int bytes_per_loop = (BYTES_PER_10GBITETHRNET_AXI_PACKET*loop_cnt);
203  static unsigned int cur_transfers_per_chunk;
204  static unsigned int cnt_wr_stream, cnt_wr_img_loaded;
205  static stream<ap_uint<MEMDW_512>> img_in_axi_stream ("img_in_axi_stream");
206  const unsigned int img_in_axi_stream_depth = TRANSFERS_PER_CHUNK; // the AXI burst size
207  #pragma HLS stream variable=img_in_axi_stream depth=img_in_axi_stream_depth
208  static unsigned int ddr_addr_in;
209 
210  // FIXME: Initialize to zero
211  static ap_uint<32> patternWriteNum;
212  static ap_uint<32> timeoutCnt;
213 
214  static Axis<MEMDW_512> memP0;
215  static DmSts memWrStsP0;
216 
217  #pragma HLS reset variable=cur_transfers_per_chunk
218  #pragma HLS reset variable=cnt_wr_stream
219  #pragma HLS reset variable=cnt_wr_img_loaded
220  #pragma HLS reset variable=ddr_addr_in
221  #pragma HLS reset variable=patternWriteNum
222  #pragma HLS reset variable=timeoutCnt
223  #pragma HLS reset variable=memP0
224  #pragma HLS reset variable=memWrStsP0
225 
226  switch(enqueueFSM)
227  {
228  case WAIT_FOR_META:
229  printf("DEBUG in pRXPathDDR: enqueueFSM - WAIT_FOR_META, *processed_bytes_rx=%u\n",
230  *processed_bytes_rx);
231 
232  printf("TOTMEMDW_512=%u\n", TOTMEMDW_512);
233  printf("TRANSFERS_PER_CHUNK=%u\n", TRANSFERS_PER_CHUNK);
234  printf("TRANSFERS_PER_CHUNK_DIVEND=%u\n", TRANSFERS_PER_CHUNK_DIVEND);
235  printf("TRANSFERS_PER_CHUNK_LAST_BURST=%u\n", TRANSFERS_PER_CHUNK_LAST_BURST);
236  //exit(-1);
237 
238  if ( !siNrc_meta.empty() && !sRxtoTx_Meta.full() )
239  {
240  meta_tmp = siNrc_meta.read();
241  meta_tmp.tlast = 1; //just to be sure...
242  sRxtoTx_Meta.write(meta_tmp);
243  if ((*processed_bytes_rx) == 0) {
244  memP0.tdata = 0;
245  memP0.tlast = 0;
246  memP0.tkeep = 0;
247  patternWriteNum = 0;
248  timeoutCnt = 0;
249  cur_transfers_per_chunk = 0;
250  netWord.tlast = 0;
251  netWord.tkeep = 0x0;
252  netWord.tdata = 0x0;
253  ddr_addr_in = 0;
254  cnt_wr_stream = 0;
255  v = 0;
256  memWrStsP0.tag = 0;
257  memWrStsP0.interr = 0;
258  memWrStsP0.decerr = 0;
259  memWrStsP0.slverr = 0;
260  memWrStsP0.okay = 0;
261  }
262  enqueueFSM = PROCESSING_PACKET;
263  }
264  break;
265 
266  case PROCESSING_PACKET:
267  printf("DEBUG in pRXPathDDR: enqueueFSM - PROCESSING_PACKET, *processed_bytes_rx=%u\n",
268  *processed_bytes_rx);
269  if ( !siSHL_This_Data.empty() )
270  {
271  //-- Read incoming data chunk
272  netWord = siSHL_This_Data.read();
273  printf("DEBUG in pRXPathDDR: Data write = {D=0x%16.16llX, K=0x%2.2X, L=%d} \n",
274  netWord.tdata.to_long(), netWord.tkeep.to_int(), netWord.tlast.to_int());
275  //enqueueFSM = LOAD_IN_STREAM;
276  if ((netWord.tkeep >> cnt_wr_stream) == 0) {
277  printf("WARNING: value with tkeep=0 at cnt_wr_stream=%u\n", cnt_wr_stream);
278  //continue;
279  }
280  v(cnt_wr_stream*64, (cnt_wr_stream+1)*64-1) = netWord.tdata(0,63);
281  if ((cnt_wr_stream++ == loop_cnt-1) || (netWord.tlast == 1)) {
282  if ( !img_in_axi_stream.full() ) {
283  // std::cout << std::hex << v << std::endl; // print hexadecimal value
284  img_in_axi_stream.write(v);
285  }
286  enqueueFSM = FSM_CHK_PROC_BYTES;
287  cnt_wr_stream = 0;
288  }
289  }
290  break;
291 
292  case FSM_CHK_PROC_BYTES:
293  printf("DEBUG in pRXPathDDR: enqueueFSM - FSM_CHK_PROC_BYTES, processed_bytes_rx=%u\n", *processed_bytes_rx);
294  if (*processed_bytes_rx < IMGSIZE-bytes_per_loop) {
295  (*processed_bytes_rx) += bytes_per_loop;
296  }
297  else {
298  printf("DEBUG in pRXPathDDR: WARNING - you've reached the max depth of img. Will put *processed_bytes_rx = 0.\n");
299  *processed_bytes_rx = 0;
300  }
301  enqueueFSM = FSM_WR_PAT_CMD;
302  break;
303 
304 case FSM_WR_PAT_CMD:
305  printf("DEBUG in pRXPathDDR: enqueueFSM - FSM_WR_PAT_CMD\n");
306  if ( !soMemWrCmdP0.full() ) {
307  //-- Post a memory write command to SHELL/Mem/Mp0
308  if (*processed_bytes_rx == 0){
309  cur_transfers_per_chunk = TRANSFERS_PER_CHUNK_LAST_BURST;
310  }
311  else {
312  cur_transfers_per_chunk = TRANSFERS_PER_CHUNK;
313  }
314  if (patternWriteNum == 0) { // Write cmd only the fitst time of every burst
315  soMemWrCmdP0.write(DmCmd(ddr_addr_in * BPERMDW_512, cur_transfers_per_chunk*BPERMDW_512)); // Byte-addresable
316  }
317  ddr_addr_in++;
318  enqueueFSM = FSM_WR_PAT_LOAD;
319  }
320  break;
321 
322 case FSM_WR_PAT_LOAD:
323  printf("DEBUG in pRXPathDDR: enqueueFSM - FSM_WR_PAT_LOAD\n");
324  // -- Assemble a 512-bit memory word with input values from stream
325  if (patternWriteNum++ == cur_transfers_per_chunk - 1) {
326  patternWriteNum = 0;
327  enqueueFSM = FSM_WR_PAT_DATA;
328  }
329  else {
330  if(netWord.tlast == 1) {
331  enqueueFSM = WAIT_FOR_META;
332  }
333  else {
334  enqueueFSM = PROCESSING_PACKET;
335  }
336  }
337  break;
338 
339 case FSM_WR_PAT_DATA:
340  printf("DEBUG in pRXPathDDR: enqueueFSM - FSM_WR_PAT_DATA\n");
341  if (!soMemWriteP0.full()) {
342  //-- Write a memory word to DRAM
343  if (!img_in_axi_stream.empty()) {
344  memP0.tdata = img_in_axi_stream.read();
345  }
346  ap_uint<8> keepVal = 0xFF;
347  memP0.tkeep = (ap_uint<64>) (keepVal, keepVal, keepVal, keepVal, keepVal, keepVal, keepVal, keepVal);
348  if (patternWriteNum++ == cur_transfers_per_chunk - 1) {
349  printf("DEBUG: (patternWriteNum == cur_transfers_per_chunk -1) \n");
350  memP0.tlast = 1;
351  cnt_wr_img_loaded = 0;
352  timeoutCnt = 0;
353  patternWriteNum = 0;
354  enqueueFSM = FSM_WR_PAT_STS_A;
355  }
356  else {
357  memP0.tlast = 0;
358  }
359  soMemWriteP0.write(memP0);
360  }
361  break;
362 
363 case FSM_WR_PAT_STS_A:
364  printf("DEBUG in pRXPathDDR: enqueueFSM - FSM_WR_PAT_STS_A\n");
365  if (!siMemWrStsP0.empty()) {
366  printf(" 1 \n");
367  //-- Get the memory write status for Mem/Mp0
368  siMemWrStsP0.read(memWrStsP0);
369  enqueueFSM = FSM_WR_PAT_STS_B;
370  }
371  else {
372  if (timeoutCnt++ >= CYCLES_UNTIL_TIMEOUT) {
373  memWrStsP0.tag = 0;
374  memWrStsP0.interr = 0;
375  memWrStsP0.decerr = 0;
376  memWrStsP0.slverr = 0;
377  memWrStsP0.okay = 0;
378  enqueueFSM = FSM_WR_PAT_STS_B;
379  }
380  }
381  break;
382 
383 case FSM_WR_PAT_STS_B:
384  printf("DEBUG in pRXPathDDR: enqueueFSM - FSM_WR_PAT_STS_B\n");
385  if ((memWrStsP0.tag == 0x0) && (memWrStsP0.okay == 1)) {
386  if ((*processed_bytes_rx) == 0) {
387  if (!sImageLoaded.full()) {
388  if (cnt_wr_img_loaded++ >= 1) {
389  sImageLoaded.write(false);
390  enqueueFSM = FSM_WR_PAT_STS_C;
391  }
392  else {
393  sImageLoaded.write(true);
394  }
395  }
396  }
397  else {
398  enqueueFSM = FSM_WR_PAT_STS_C;
399  }
400  }
401  else {
402  ; // TODO: handle errors on memWrStsP0
403  }
404  break;
405 
406 case FSM_WR_PAT_STS_C:
407  printf("DEBUG in pRXPathDDR: enqueueFSM - FSM_WR_PAT_STS_C\n");
408  if(netWord.tlast == 1) {
409  enqueueFSM = WAIT_FOR_META;
410  }
411  else {
412  enqueueFSM = PROCESSING_PACKET;
413  }
414  break;
415 }
416 
417 }
timeoutCnt
ap_uint< 32 > timeoutCnt
Definition: mem_test_flash.cpp:34
patternWriteNum
ap_uint< 32 > patternWriteNum
Definition: mem_test_flash.cpp:31
DmSts::okay
ap_uint< 1 > okay
Definition: memory_utils.hpp:84
DmSts::decerr
ap_uint< 1 > decerr
Definition: memory_utils.hpp:82
DmSts::slverr
ap_uint< 1 > slverr
Definition: memory_utils.hpp:83
DmSts::tag
ap_uint< 4 > tag
Definition: memory_utils.hpp:80
DmSts::interr
ap_uint< 1 > interr
Definition: memory_utils.hpp:81
IMGSIZE
#define IMGSIZE
Definition: xf_gammacorrection_config.h:67
TRANSFERS_PER_CHUNK_DIVEND
#define TRANSFERS_PER_CHUNK_DIVEND
Definition: harris.hpp:134
FSM_WR_PAT_STS_B
#define FSM_WR_PAT_STS_B
Definition: harris.hpp:87
FSM_WR_PAT_LOAD
#define FSM_WR_PAT_LOAD
Definition: harris.hpp:84
FSM_WR_PAT_CMD
#define FSM_WR_PAT_CMD
Definition: harris.hpp:83
FSM_WR_PAT_DATA
#define FSM_WR_PAT_DATA
Definition: harris.hpp:85
FSM_CHK_PROC_BYTES
#define FSM_CHK_PROC_BYTES
Definition: harris.hpp:81
FSM_WR_PAT_STS_A
#define FSM_WR_PAT_STS_A
Definition: harris.hpp:86
FSM_WR_PAT_STS_C
#define FSM_WR_PAT_STS_C
Definition: harris.hpp:88
BITS_PER_10GBITETHRNET_AXI_PACKET
#define BITS_PER_10GBITETHRNET_AXI_PACKET
Definition: mceuropeanengine.hpp:81
BYTES_PER_10GBITETHRNET_AXI_PACKET
#define BYTES_PER_10GBITETHRNET_AXI_PACKET
Definition: mceuropeanengine.hpp:82
TRANSFERS_PER_CHUNK_LAST_BURST
#define TRANSFERS_PER_CHUNK_LAST_BURST
Definition: median_blur.cpp:57
CYCLES_UNTIL_TIMEOUT
#define CYCLES_UNTIL_TIMEOUT
Definition: memtest.hpp:96
Axis::tkeep
ap_uint<(D+7)/8 > tkeep
Definition: axi_utils.hpp:49
Axis::tlast
ap_uint< 1 > tlast
Definition: axi_utils.hpp:50
Axis::tdata
ap_uint< D > tdata
Definition: axi_utils.hpp:48
NetworkWord::tdata
ap_uint< 64 > tdata
Definition: network.hpp:49
NetworkWord::tkeep
ap_uint< 8 > tkeep
Definition: network.hpp:50

◆ pRXPathNetToStream()

void pRXPathNetToStream ( stream< NetworkWord > &  siSHL_This_Data,
stream< NetworkMetaStream > &  siNrc_meta,
stream< NetworkMetaStream > &  sRxtoTx_Meta,
stream< ap_uint< 512 >> &  img_in_axi_stream,
stream< bool > &  sMemBurstRx 
)

Receive Path - From SHELL to THIS.

Parameters
[in]siSHL_This_Data
[in]siNrc_meta
[out]sRxtoTx_Meta
[out]meta_tmp
Returns
Nothing.

Definition at line 432 of file median_blur.cpp.

439 {
440  //-- DIRECTIVES FOR THIS PROCESS ------------------------------------------
441  #pragma HLS INLINE off
442  #pragma HLS pipeline II=1
443  //#pragma HLS interface ap_ctrl_none port=return
444 
445  //-- LOCAL VARIABLES ------------------------------------------------------
446  static NetworkWord netWord;
447  const unsigned int loop_cnt = (MEMDW_512/BITS_PER_10GBITETHRNET_AXI_PACKET);
448  NetworkMetaStream meta_tmp;
449  static ap_uint<MEMDW_512> v = 0;
450  static unsigned int cnt_wr_stream = 0, cnt_wr_burst = 0;
451  static unsigned int processed_net_bytes_rx = 0;
452 // static stream<ap_uint<MEMDW_512>> img_in_axi_stream ("img_in_axi_stream");
453 // const unsigned int img_in_axi_stream_depth = TRANSFERS_PER_CHUNK; // the AXI burst size
454 // #pragma HLS stream variable=img_in_axi_stream depth=img_in_axi_stream_depth
455 
456  #pragma HLS reset variable=cnt_wr_stream
457  #pragma HLS reset variable=cnt_wr_burst
458 
459  switch(enqueueRxToStrFSM)
460  {
461  case WAIT_FOR_META:
462  printf("DEBUG in pRXPathNetToStream: enqueueRxToStrFSM - WAIT_FOR_META\n");
463 
464  if ( !siNrc_meta.empty() && !sRxtoTx_Meta.full() )
465  {
466  meta_tmp = siNrc_meta.read();
467  meta_tmp.tlast = 1; //just to be sure...
468  sRxtoTx_Meta.write(meta_tmp);
469  enqueueRxToStrFSM = PROCESSING_PACKET;
470  }
471  break;
472 
473  case PROCESSING_PACKET:
474  printf("DEBUG in pRXPathNetToStream: enqueueRxToStrFSM - PROCESSING_PACKET, processed_net_bytes_rx=%u\n", processed_net_bytes_rx);
475  if ( !siSHL_This_Data.empty() && !img_in_axi_stream.full())
476  {
477  //-- Read incoming data chunk
478  netWord = siSHL_This_Data.read();
479  printf("DEBUG in pRXPathNetToStream: Data write = {D=0x%16.16llX, K=0x%2.2X, L=%d} \n",
480  netWord.tdata.to_long(), netWord.tkeep.to_int(), netWord.tlast.to_int());
481  //enqueueRxToStrFSM = LOAD_IN_STREAM;
482  if ((netWord.tkeep >> cnt_wr_stream) == 0) {
483  printf("WARNING: value with tkeep=0 at cnt_wr_stream=%u\n", cnt_wr_stream);
484  //continue;
485  }
486  v(cnt_wr_stream*64, (cnt_wr_stream+1)*64-1) = netWord.tdata(0,63);
487  if ((cnt_wr_stream++ == loop_cnt-1) || (netWord.tlast == 1)) {
488  // std::cout << std::hex << v << std::endl; // print hexadecimal value
489  std::cout << "DEBUG in pRXPathNetToStream: Pushing to img_in_axi_stream :" << std::hex << v << std::endl;
490  img_in_axi_stream.write(v);
491  if ((cnt_wr_burst++ == TRANSFERS_PER_CHUNK-1) ||
492  ((processed_net_bytes_rx == IMGSIZE-BYTES_PER_10GBITETHRNET_AXI_PACKET) &&
493  (netWord.tlast == 1))) {
494  if (!sMemBurstRx.full()) {
495  sMemBurstRx.write(true);
496  }
497  cnt_wr_burst = 0;
498  }
499  if (netWord.tlast == 1) {
500  enqueueRxToStrFSM = WAIT_FOR_META;
501  }
502  cnt_wr_stream = 0;
503  }
504  if (processed_net_bytes_rx == IMGSIZE-BYTES_PER_10GBITETHRNET_AXI_PACKET) {
505  processed_net_bytes_rx = 0;
506  }
507  else {
508  processed_net_bytes_rx += BYTES_PER_10GBITETHRNET_AXI_PACKET;
509  }
510  }
511  break;
512  }
513 }
enqueueRxToStrFSM
uint8_t enqueueRxToStrFSM
Definition: median_blur.cpp:49
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◆ pRXPathStreamToDDR()

void pRXPathStreamToDDR ( stream< ap_uint< 512 >> &  img_in_axi_stream,
stream< bool > &  sMemBurstRx,
stream< DmCmd > &  soMemWrCmdP0,
stream< DmSts > &  siMemWrStsP0,
stream< Axis< 512 > > &  soMemWriteP0,
stream< bool > &  sImageLoaded 
)

Receive Path - From SHELL to THIS.

Parameters
[in]siSHL_This_Data
[in]siNrc_meta
[out]sRxtoTx_Meta
[out]img_in_axi_stream
[out]processed_word
[out]sImageLoaded
Returns
Nothing.

Definition at line 530 of file median_blur.cpp.

540 {
541  //-- DIRECTIVES FOR THIS PROCESS ------------------------------------------
542  #pragma HLS INLINE off
543  #pragma HLS pipeline II=1
544  //#pragma HLS interface ap_ctrl_none port=return
545 
546  //-- LOCAL VARIABLES ------------------------------------------------------
547  static ap_uint<MEMDW_512> v = 0;
548  const unsigned int loop_cnt = (MEMDW_512/BITS_PER_10GBITETHRNET_AXI_PACKET);
549  const unsigned int bytes_per_loop = (BYTES_PER_10GBITETHRNET_AXI_PACKET*loop_cnt);
550  static unsigned int cur_transfers_per_chunk;
551  static unsigned int cnt_wr_stream, cnt_wr_img_loaded;
552 // static stream<ap_uint<MEMDW_512>> img_in_axi_stream ("img_in_axi_stream");
553 // const unsigned int img_in_axi_stream_depth = TRANSFERS_PER_CHUNK; // the AXI burst size
554 // #pragma HLS stream variable=img_in_axi_stream depth=img_in_axi_stream_depth
555  static unsigned int ddr_addr_in;
556 
557  // FIXME: Initialize to zero
558  static ap_uint<32> patternWriteNum;
559  static ap_uint<32> timeoutCnt;
560 
561  static Axis<MEMDW_512> memP0;
562  static DmSts memWrStsP0;
563  static unsigned int processed_bytes_rx;
564 
565  #pragma HLS reset variable=cur_transfers_per_chunk
566  #pragma HLS reset variable=cnt_wr_stream
567  #pragma HLS reset variable=cnt_wr_img_loaded
568  #pragma HLS reset variable=ddr_addr_in
569  #pragma HLS reset variable=patternWriteNum
570  #pragma HLS reset variable=timeoutCnt
571  #pragma HLS reset variable=memP0
572  #pragma HLS reset variable=memWrStsP0
573 
574  switch(enqueueStrToDdrFSM)
575  {
576  case WAIT_FOR_META:
577  printf("DEBUG in pRXPathStreamToDDR: enqueueStrToDdrFSM - WAIT_FOR_META, processed_bytes_rx=%u\n",
578  processed_bytes_rx);
579 
580  if ( !img_in_axi_stream.empty() )
581  {
582  if ((processed_bytes_rx) == 0) {
583  memP0.tdata = 0;
584  memP0.tlast = 0;
585  memP0.tkeep = 0;
586  patternWriteNum = 0;
587  timeoutCnt = 0;
588  cur_transfers_per_chunk = 0;
589  ddr_addr_in = 0;
590  cnt_wr_stream = 0;
591  v = 0;
592  memWrStsP0.tag = 0;
593  memWrStsP0.interr = 0;
594  memWrStsP0.decerr = 0;
595  memWrStsP0.slverr = 0;
596  memWrStsP0.okay = 0;
597  }
598  enqueueStrToDdrFSM = FSM_CHK_PROC_BYTES;
599  }
600  break;
601 
602  case FSM_CHK_PROC_BYTES:
603  printf("DEBUG in pRXPathStreamToDDR: enqueueStrToDdrFSM - FSM_CHK_PROC_BYTES, processed_bytes_rx=%u\n", processed_bytes_rx);
604  if (processed_bytes_rx < IMGSIZE-bytes_per_loop) {
605  (processed_bytes_rx) += bytes_per_loop;
606  }
607  else {
608  printf("DEBUG in pRXPathStreamToDDR: WARNING - you've reached the max depth of img. Will put processed_bytes_rx = 0.\n");
609  processed_bytes_rx = 0;
610  }
611  enqueueStrToDdrFSM = FSM_WR_PAT_CMD;
612  break;
613 
614 case FSM_WR_PAT_CMD:
615  printf("DEBUG in pRXPathStreamToDDR: enqueueStrToDdrFSM - FSM_WR_PAT_CMD\n");
616  if ( !soMemWrCmdP0.full() ) {
617  //-- Post a memory write command to SHELL/Mem/Mp0
618  if (processed_bytes_rx == 0){
619  cur_transfers_per_chunk = TRANSFERS_PER_CHUNK_LAST_BURST;
620  }
621  else {
622  cur_transfers_per_chunk = TRANSFERS_PER_CHUNK;
623  }
624  if (patternWriteNum == 0) { // Write cmd only the fitst time of every burst
625  soMemWrCmdP0.write(DmCmd(ddr_addr_in * BPERMDW_512, cur_transfers_per_chunk*BPERMDW_512)); // Byte-addresable
626  }
627  ddr_addr_in++;
628  enqueueStrToDdrFSM = FSM_WR_PAT_LOAD;
629  }
630  break;
631 
632 case FSM_WR_PAT_LOAD:
633  printf("DEBUG in pRXPathStreamToDDR: enqueueStrToDdrFSM - FSM_WR_PAT_LOAD\n");
634  // -- Assemble a 512-bit memory word with input values from stream
635  if (patternWriteNum++ >= cur_transfers_per_chunk - 1) {
636  if (!sMemBurstRx.empty()) {
637  if (sMemBurstRx.read() == true) {
638  patternWriteNum = 0;
639  enqueueStrToDdrFSM = FSM_WR_PAT_DATA;
640  }
641  }
642  }
643  else {
644  if((processed_bytes_rx) == 0) {
645  enqueueStrToDdrFSM = WAIT_FOR_META;
646  }
647  else {
648  enqueueStrToDdrFSM = FSM_CHK_PROC_BYTES;
649  }
650  }
651  break;
652 
653 case FSM_WR_PAT_DATA:
654  printf("DEBUG in pRXPathStreamToDDR: enqueueStrToDdrFSM - FSM_WR_PAT_DATA\n");
655  if (!soMemWriteP0.full()) {
656  //-- Write a memory word to DRAM
657  if (!img_in_axi_stream.empty()) {
658  memP0.tdata = img_in_axi_stream.read();
659  ap_uint<8> keepVal = 0xFF;
660  memP0.tkeep = (ap_uint<64>) (keepVal, keepVal, keepVal, keepVal, keepVal, keepVal, keepVal, keepVal);
661  if (patternWriteNum++ == cur_transfers_per_chunk - 1) {
662  printf("DEBUG: (patternWriteNum == cur_transfers_per_chunk -1) \n");
663  memP0.tlast = 1;
664  cnt_wr_img_loaded = 0;
665  timeoutCnt = 0;
666  patternWriteNum = 0;
667  enqueueStrToDdrFSM = FSM_WR_PAT_STS_A;
668  }
669  else {
670  memP0.tlast = 0;
671  }
672  std::cout << "DEBUG in pRXPathStreamToDDR: Pushing to soMemWriteP0 :" << std::hex << memP0.tdata << std::endl;
673  soMemWriteP0.write(memP0);
674  }
675  }
676  break;
677 
678 case FSM_WR_PAT_STS_A:
679  printf("DEBUG in pRXPathStreamToDDR: enqueueStrToDdrFSM - FSM_WR_PAT_STS_A\n");
680  if (!siMemWrStsP0.empty()) {
681  printf(" 1 \n");
682  //-- Get the memory write status for Mem/Mp0
683  siMemWrStsP0.read(memWrStsP0);
684  enqueueStrToDdrFSM = FSM_WR_PAT_STS_B;
685  }
686  else {
687  if (timeoutCnt++ >= CYCLES_UNTIL_TIMEOUT) {
688  memWrStsP0.tag = 0;
689  memWrStsP0.interr = 0;
690  memWrStsP0.decerr = 0;
691  memWrStsP0.slverr = 0;
692  memWrStsP0.okay = 0;
693  enqueueStrToDdrFSM = FSM_WR_PAT_STS_B;
694  }
695  }
696  break;
697 
698 case FSM_WR_PAT_STS_B:
699  printf("DEBUG in pRXPathStreamToDDR: enqueueStrToDdrFSM - FSM_WR_PAT_STS_B\n");
700  if ((memWrStsP0.tag == 0x0) && (memWrStsP0.okay == 1)) {
701  if ((processed_bytes_rx) == 0) {
702  if (!sImageLoaded.full()) {
703  if (cnt_wr_img_loaded++ >= 1) {
704  sImageLoaded.write(false);
705  enqueueStrToDdrFSM = FSM_WR_PAT_STS_C;
706  }
707  else {
708  sImageLoaded.write(true);
709  }
710  }
711  }
712  else {
713  enqueueStrToDdrFSM = FSM_WR_PAT_STS_C;
714  }
715  }
716  else {
717  ; // TODO: handle errors on memWrStsP0
718  }
719  break;
720 
721 case FSM_WR_PAT_STS_C:
722  printf("DEBUG in pRXPathStreamToDDR: enqueueStrToDdrFSM - FSM_WR_PAT_STS_C\n");
723  if((processed_bytes_rx) == 0) {
724  enqueueStrToDdrFSM = WAIT_FOR_META;
725  }
726  else {
727  enqueueStrToDdrFSM = FSM_CHK_PROC_BYTES;
728  }
729  break;
730 }
731 
732 }
enqueueStrToDdrFSM
uint8_t enqueueStrToDdrFSM
Definition: median_blur.cpp:50
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◆ pTXPath()

void pTXPath ( stream< NetworkWord > &  soTHIS_Shl_Data,
stream< NetworkMetaStream > &  soNrc_meta,
stream< NetworkWord > &  sRxpToTxp_Data,
stream< NetworkMetaStream > &  sRxtoTx_Meta,
unsigned int *  processed_word_tx,
ap_uint< 32 > *  pi_rank,
ap_uint< 32 > *  pi_size 
)

Transmit Path - From THIS to SHELL.

Parameters
[out]soTHIS_Shl_Data
[out]soNrc_meta
[in]sRxpToTxp_Data
[in]sRxtoTx_Meta
[in]pi_rank
[in]pi_size
Returns
Nothing.

Definition at line 1020 of file median_blur.cpp.

1029 {
1030  //-- DIRECTIVES FOR THIS PROCESS ------------------------------------------
1031  #pragma HLS INLINE off
1032  #pragma HLS pipeline II=1
1033 
1034  //-- STATIC DATAFLOW VARIABLES ------------------------------------------
1035  static NodeId dst_rank;
1036 
1037  //-- LOCAL VARIABLES ------------------------------------------------------
1038  NetworkWord netWordTx;
1039  NetworkMeta meta_in = NetworkMeta();
1040  NetworkMetaStream meta_out_stream = NetworkMetaStream();
1041 
1042  #pragma HLS reset variable=dst_rank
1043  #pragma HLS reset variable=netWordTx
1044 
1045  switch(dequeueFSM)
1046  {
1047  default:
1048  case WAIT_FOR_META:
1049  printf("DEBUG in pTXPath: dequeueFSM=%d - WAIT_FOR_META, *processed_word_tx=%u\n",
1050  dequeueFSM, *processed_word_tx);
1051  //-- Forward incoming chunk to SHELL
1052  if (*processed_word_tx == MIN_TX_LOOPS) {
1053  *processed_word_tx = 0;
1054  }
1055  /*
1056  printf("!sRxpToTxp_Data.empty()=%d\n", !sRxpToTxp_Data.empty());
1057  printf("!sRxtoTx_Meta.empty()=%d\n", !sRxtoTx_Meta.empty());
1058  printf("!soTHIS_Shl_Data.full()=%d\n", !soTHIS_Shl_Data.full());
1059  printf("!soNrc_meta.full()=%d\n", !soNrc_meta.full());
1060  */
1061 
1062  if (( !sRxpToTxp_Data.empty() && !sRxtoTx_Meta.empty()
1063  && !soTHIS_Shl_Data.full() && !soNrc_meta.full() ))
1064  {
1065  netWordTx = sRxpToTxp_Data.read();
1066 
1067  // in case MTU=8 ensure tlast is set in WAIT_FOR_META and don't visit PROCESSING_PACKET
1068  if (PACK_SIZE == 8)
1069  {
1070  netWordTx.tlast = 1;
1071  }
1072  soTHIS_Shl_Data.write(netWordTx);
1073 
1074  meta_in = sRxtoTx_Meta.read().tdata;
1075  //NetworkMetaStream meta_out_stream = NetworkMetaStream();
1076  meta_out_stream.tlast = 1;
1077  meta_out_stream.tkeep = 0xFF; //just to be sure
1078 
1079  meta_out_stream.tdata.dst_rank = meta_in.src_rank; //dst_rank; //(*pi_rank + 1) % *pi_size;
1080  //meta_out_stream.tdata.dst_port = DEFAULT_TX_PORT;
1081  meta_out_stream.tdata.src_rank = (NodeId) *pi_rank;
1082 
1083  // Forcing the SHELL to wait for tlast
1084  meta_out_stream.tdata.len = 0;
1085 
1086  //meta_out_stream.tdata.src_port = DEFAULT_RX_PORT;
1087  //printf("rank: %d; size: %d; \n", (int) *pi_rank, (int) *pi_size);
1088  //printf("meat_out.dst_rank: %d\n", (int) meta_out_stream.tdata.dst_rank);
1089  meta_out_stream.tdata.dst_port = meta_in.src_port;
1090  meta_out_stream.tdata.src_port = meta_in.dst_port;
1091 
1092 
1093  //meta_out_stream.tdata.len = meta_in.len;
1094  soNrc_meta.write(meta_out_stream);
1095 
1096  (*processed_word_tx)++;
1097  printf("DEBUGGGG: Checking netWordTx.tlast...\n");
1098  if(netWordTx.tlast != 1)
1099  {
1100  dequeueFSM = PROCESSING_PACKET;
1101  }
1102  }
1103  break;
1104 
1105  case PROCESSING_PACKET:
1106  printf("DEBUG in pTXPath: dequeueFSM=%d - PROCESSING_PACKET, *processed_word_tx=%u\n",
1107  dequeueFSM, *processed_word_tx);
1108  if( !sRxpToTxp_Data.empty() && !soTHIS_Shl_Data.full())
1109  {
1110  printf("DEBUGGGG: Reading sRxpToTxp_Data %u\n", sRxpToTxp_DataCounter++);
1111  netWordTx = sRxpToTxp_Data.read();
1112 
1113  (*processed_word_tx)++;
1114 
1115  // This is a normal termination of the axi stream from vitis functions
1116  if ((netWordTx.tlast == 1) || (((*processed_word_tx)*8) % PACK_SIZE == 0))
1117  {
1118  netWordTx.tlast = 1; // in case it is the 2nd or
1119  printf("DEBUGGGG: A netWordTx.tlast=1 ... sRxpToTxp_Data.empty()==%u \n", sRxpToTxp_Data.empty());
1120  dequeueFSM = WAIT_FOR_META;
1121  }
1122 
1123  // This is our own termination based on the custom MTU we have set in PACK_SIZE.
1124  // TODO: We can map PACK_SIZE to a dynamically assigned value either through MMIO or header
1125  // in order to have a functional bitstream for any MTU size
1126  //if (((*processed_word_tx)*8) % PACK_SIZE == 0)
1127  //{
1128  // printf("DEBUGGGG: B (*processed_word_tx)*8) % PACK_SIZE == 0 ...\n");
1129  // netWordTx.tlast = 1;
1130  // dequeueFSM = WAIT_FOR_META;
1131  //}
1132 
1133  soTHIS_Shl_Data.write(netWordTx);
1134  }
1135  break;
1136  }
1137 }
sRxpToTxp_DataCounter
unsigned int sRxpToTxp_DataCounter
Definition: median_blur.cpp:1006
dequeueFSM
uint8_t dequeueFSM
Definition: median_blur.cpp:52
PACK_SIZE
#define PACK_SIZE
Definition: config.h:51
NodeId
ap_uint< 8 > NodeId
Definition: network.hpp:82
NetworkMetaStream::tkeep
ap_uint< 8 > tkeep
Definition: network.hpp:110
NetworkMetaStream::tdata
NetworkMeta tdata
Definition: network.hpp:109
NetworkMeta::len
NetworkDataLength len
Definition: network.hpp:99
NetworkMeta::dst_rank
NodeId dst_rank
Definition: network.hpp:95
NetworkMeta::src_rank
NodeId src_rank
Definition: network.hpp:97
NetworkMeta::src_port
NrcPort src_port
Definition: network.hpp:98
NetworkMeta::dst_port
NrcPort dst_port
Definition: network.hpp:96
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◆ storeWordToArray()

void storeWordToArray ( uint64_t  input,
ap_uint< 8 >  img[1024 *1024/((64/8))],
unsigned int *  processed_word,
unsigned int *  image_loaded 
)

Store a net word to local memory.

Returns
Nothing.

Definition at line 81 of file median_blur.cpp.

83 {
84  #pragma HLS INLINE
85 
86  img[*processed_word] = (ap_uint<INPUT_PTR_WIDTH>) input;
87  printf("DEBUG in storeWordToArray: input = %u = 0x%16.16llX \n", input, input);
88  printf("DEBUG in storeWordToArray: img[%u]= %u = 0x%16.16llX \n", *processed_word,
89  (uint64_t)img[*processed_word], (uint64_t)img[*processed_word]);
90  if (*processed_word < IMG_PACKETS-1) {
91  *processed_word++;
92  }
93  else {
94  printf("DEBUG in storeWordToArray: WARNING - you've reached the max depth of img[%u]. Will put *processed_word = 0.\n", *processed_word);
95  *processed_word = 0;
96  *image_loaded = 1;
97  }
98 }
IMG_PACKETS
#define IMG_PACKETS
Definition: xf_gammacorrection_config.h:69
test.input
string input
Definition: test.py:9

◆ storeWordToAxiStream()

void storeWordToAxiStream ( NetworkWord  word,
stream< ap_uint< 8 >> &  img_in_axi_stream,
unsigned int *  processed_word_rx,
unsigned int *  processed_bytes_rx,
stream< bool > &  sImageLoaded 
)

Store a net word to a local AXI stream.

Returns
Nothing.

Definition at line 105 of file median_blur.cpp.

117 {
118  #pragma HLS INLINE
119  Data_t_in v;
120  const unsigned int loop_cnt = (BITS_PER_10GBITETHRNET_AXI_PACKET/INPUT_PTR_WIDTH);
121  const unsigned int bytes_per_loop = (BYTES_PER_10GBITETHRNET_AXI_PACKET/loop_cnt);
122  unsigned int bytes_with_keep = 0;
123  //v = word.tdata;
124  for (unsigned int i=0; i<loop_cnt; i++) {
125  //#pragma HLS PIPELINE
126  //#pragma HLS UNROLL factor=loop_cnt
127  //printf("DEBUG: Checking: word.tkeep=%u >> %u = %u\n", word.tkeep.to_int(), i, (word.tkeep.to_int() >> i));
128  if ((word.tkeep >> i) == 0) {
129  printf("WARNING: value with tkeep=0 at i=%u\n", i);
130  continue;
131  }
132  v.data = (ap_uint<INPUT_PTR_WIDTH>)(word.tdata >> i*8);
133  v.keep = word.tkeep;
134  v.last = word.tlast;
135  //printf("DEBUG in storeWordToAxiStream: word = %u = 0x%16.16llX \n", v.data, v.data);
136  img_in_axi_stream.write(v.data);
137  bytes_with_keep += bytes_per_loop;
138  }
139  /*
140  if (*processed_word_rx < IMG_PACKETS-1) {
141  (*processed_word_rx)++;
142  }
143  else {
144  printf("DEBUG in storeWordToAxiStream: WARNING - you've reached the max depth of img. Will put *processed_word_rx = 0.\n");
145  *processed_word_rx = 0;
146  }*/
147  if (*processed_bytes_rx < IMGSIZE-BYTES_PER_10GBITETHRNET_AXI_PACKET) {
148  (*processed_bytes_rx) += bytes_with_keep;
149  if (!sImageLoaded.full()) {
150  sImageLoaded.write(false);
151  }
152  }
153  else {
154  printf("DEBUG in storeWordToAxiStream: WARNING - you've reached the max depth of img. Will put *processed_bytes_rx = 0.\n");
155  *processed_bytes_rx = 0;
156  if (!sImageLoaded.full()) {
157  sImageLoaded.write(true);
158  }
159  }
160 }
Data_t_in
#define Data_t_in
Definition: memtest.cpp:29
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Variable Documentation

◆ dequeueFSM

uint8_t dequeueFSM = 0

Definition at line 52 of file median_blur.cpp.

◆ enqueueFSM

uint8_t enqueueFSM = 0

Definition at line 51 of file median_blur.cpp.

◆ enqueueRxToStrFSM

uint8_t enqueueRxToStrFSM = 0

Definition at line 49 of file median_blur.cpp.

◆ enqueueStrToDdrFSM

uint8_t enqueueStrToDdrFSM = 0

Definition at line 50 of file median_blur.cpp.

◆ MedianBlurFSM

uint8_t MedianBlurFSM = 0

Definition at line 53 of file median_blur.cpp.

◆ sRxpToTxp_DataCounter

unsigned int sRxpToTxp_DataCounter = 0

Definition at line 1006 of file median_blur.cpp.