- Generated on Sat Jul 15 2023 05:03:06 for cloudFPGA (cF) API by
1.9.1
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cloudFPGA (cF) API
1.0
The documentation of the source code of cloudFPGA (cF)
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| ▼cF | This is the main cloudFPGA module |
| ▼cFSphere | The cloudFPGA Sphere or cFSphere is what constitutes the core of a cloudFPGA system. It is composed of several major software components, each of them being provided as a standalone cF repository |
| ▼cFDK | This is the cloudFPGA Development Kit (cFDK). The documentation of cFDK is available at https://pages.github.ibm.com/cloudFPGA/Doc/pages/cfdk.html |
| ▼SHELL Library | This is the SHELL library of cloudFPGA platform with its three basic components, i.e. NTS, FMC, NAL. The documentation of the SHELL library is available at https://pages.github.ibm.com/cloudFPGA/Doc/pages/cfdk.html#shell-library |
| FMC | FPGA Management Core (FMC). The FMC is the core of the cloudFPGA Shell-Role-Architecture. The FMC controls the FPGA and exposes the management functionality via a RESTful HTTP API. Its tasks and responsibilities are sometimes complex and depend on the current situation and environment. In order to unbundle all these dependencies and to allow future extensions easily, the FMC contains a small Instruction-Set-Architecture (ISA). A detailed documentation of the FMC can be found at https://pages.github.ibm.com/cloudFPGA/Doc/pages/cfdk.html#fpga-management-core-fmc |
| MEM | Memory Sub-System (MEM). This component implements the dynamic memory controllers for the FPGA module FMKU2595 equipped with a XCKU060. This memory sub-system implements two DDR4 memory channels (MC0 and MC1 ), each with a capacity of 8GB. By convention, the memory channel #0 (MC0) is dedicated to the network transport and session (NTS) stack, and the memory channel #1 (MC1) is reserved for the user application. The documentation of MEM is available at https://pages.github.ibm.com/cloudFPGA/Doc/pages/cfdk.html#memory-sub-system-mem |
| NAL | Network Abstraction Layer (NAL). The NAL separates the privileged management traffic from the unprivileged Role traffic. It also abstracts the details of port opening, connection handling and IP Address translation. The documentation of NAL is available at https://pages.github.ibm.com/cloudFPGA/Doc/pages/cfdk.html#network-abstraction-layer-nal |
| ▼NTS | Network Transport Stack (NTS). This component implements the TCP/IP Network and Transport Stack used by the cloudFPGA platform. The documentation of NTS is available at https://pages.github.ibm.com/cloudFPGA/Doc/pages/cfdk.html#network-transport-stack-nts |
| ▼ARP | Address Resolution Protocol (ARS) server of the Network Transport Stack (NTS) |
| ARP_TEST | Testbench for the Address Resolution Protocol (ARS) server of the Network Transport Stack (NTS) |
| ▼ICMP | Internet Control Message Protocol server (ICMP) of the Network Transport Stack (NTS) |
| ICMP_TEST | Testbench for the Internet Control Message Protocol server (ICMP) of the Network Transport Stack (NTS) |
| ▼IPRX | IP Receiver packet handler (IPRX) of the Network Transport Stack (NTS) |
| IPRX_TEST | Testbench for the IP Receiver packet handler (IPRX) of the Network Transport Stack (NTS) |
| ▼IPTX | IP Transmitter packet handler (IPTX) of the Network Transport Stack (NTS) |
| IPTX_TEST | Testbench for the IP Transmitter packet handler (IPTX) of the Network Transport Stack (NTS) |
| ▼RLB | Ready Logic Barrier (RLB) for the Network Transport Stack (NTS) |
| RLB_TEST | Testbench for the Ready Logic Barrier (RLB) for the Network Transport Stack (NTS) |
| ▼TOE | TCP Offload Engine (TOE) of the Network Transport Stack (NTS) |
| TOE_TEST | Testbench for the TCP Offload Engine (TOE) of the Network Transport Stack (NTS) |
| ▼TOECAM | Content-Addressable Memory (CAM) for the TCP Offload Engine (TOE) of the Network Transport Stack (NTS) |
| TOECAM_TEST | Testbench for the Content-Addressable Memory (CAM) for the TCP Offload Engine (TOE) of the Network Transport Stack (NTS) |
| ▼UOE | UDP Offload Engine (UOE) of the Network Transport Stack (NTS) |
| UOE_TEST | Testbench for the UDP Offload Engine (UOE) of the Network Transport Stack (NTS) |
| SimNts | Support and utilities for the simulation of the Network Transport Stack (NTS) |
| ▼SRA | Shell-Role-Architecture (SRA). To abstract the details of the hardware from the user and to assert certain levels of security, cloudFPGA uses a Shell-Role-Architecture (SRA). The documentation of SRA is available at https://pages.github.ibm.com/cloudFPGA/Doc/pages/cfdk.html#sras |
| Themisto | This SRA type enables node2node communication within cloudFPGA. The network data streams have now a parallel meta stream to select the destinations or to see the source, respectively. The dual memory port is stream based. The documentation of Themisto is available at https://pages.github.ibm.com/cloudFPGA/Doc/pages/cfdk.html#the-themisto-sra |
| Kale | This version of the cF shell is used for the testing and the bring-up of a cloudFPGA (cF) module. The documentation of Kale is available at https://pages.github.ibm.com/cloudFPGA/Doc/pages/cfdk.html#the-shell-kale |
| cFSP | CFSP is the cloudFPGA Support Package and it includes a support library for accessing the data and control paths of a cloudFPGA instance |
| ▼cFp | CloudFPGA Projects (cFp). This is a group with existing projects developed with cFDK and can be used as templates for new projects |
| ▼cFp_Zoo | This project is based on Themisto Shell and it features several domain-specific accelerators |
| ▼cF Vitis Vision | This is the accelerated functions of Vitis Vision sub-library from Vitis Open Source Library |
| ▼Harris | This is the Harris accelerated function from Vitis Vision Open Source Library |
| Harris Testbench | This is a subgroup of Harris accelerated function with only testbench-related functions/classes/ |
| Harris Vivado HLS | This is a subgroup of Harris accelerated function with only synthesizable (Vivado HLS) functions/classes |
| Harris Host | This is a subgroup of Harris accelerated function with only host code software |
| ▼Gammacorrection | This is the Gammacorrection accelerated function from Vitis Vision Open Source Library |
| Gammacorrection Testbench | This is a subgroup of Gammacorrection accelerated function with only testbench-related functions/classes/ |
| Gammacorrection Vivado HLS | This is a subgroup of Gammacorrection accelerated function with only synthesizable (Vivado HLS) functions/classes |
| Gammacorrection Host | This is a subgroup of Gammacorrection accelerated function with only host code software |
| ▼MedianBlur | This is the MedianBlur accelerated function from Vitis Vision Open Source Library |
| MedianBlur Testbench | This is a subgroup of MedianBlur accelerated function with only testbench-related functions/classes |
| MedianBlur HLS | This is a subgroup of MedianBlur accelerated function with only synthesizable (HLS) functions/classes |
| MedianBlur Host | This is a subgroup of MedianBlur accelerated function with only host code software |
| ▼Sobel | This is the Sobel accelerated function from Vitis Vision Open Source Library |
| Sobel Testbench | This is a subgroup of Sobel accelerated function with only testbench-related functions/classes |
| Sobel HLS | This is a subgroup of Sobel accelerated function with only synthesizable (HLS) functions/classes |
| Sobel Host | This is a subgroup of Sobel accelerated function with only host code software |
| ▼WarpTransform | This is the WarpTransform accelerated function from Vitis Vision Open Source Library |
| WarpTransform Testbench | This is a subgroup of WarpTransform accelerated function with only testbench-related functions/classes |
| WarpTransform HLS | This is a subgroup of WarpTransform accelerated function with only synthesizable (HLS) functions/classes |
| WarpTransform Host | This is a subgroup of WarpTransform accelerated function with only host code software |
| ▼cF Vitis Quantitative Finance | This is the accelerated functions of Vitis Quantitative Finance sub-library from Vitis Open Source Library |
| ▼MCEuropeanEngine | This is the MCEuropeanEngine accelerated function from Vitis Quantitative Finance Open Source Library |
| MCEuropeanEngine Testbench | This is a subgroup of MCEuropeanEngine accelerated function with only testbench-related functions/classes/ |
| MCEuropeanEngine Vivado HLS | This is a subgroup of MCEuropeanEngine accelerated function with only synthesizable (Vivado HLS) functions/classes |
| MCEuropeanEngine Host | This is a subgroup of MCEuropeanEngine accelerated function with only host code software |
| ▼cF IBMZRL essentials | This is a set of projects developed by IBM Research Zurich Lab. The group contains educational projects and platform-stressing ones |
| ▼Uppercase | This is the Uppercase educational example. The FPGA accepts a string and returns the upper-case converted one |
| Uppercase Testbench | This is a subgroup of Uppercase accelerated function with only testbench-related functions/classes |
| Uppercase HLS | This is a subgroup of Uppercase accelerated function with only synthesizable (HLS) functions/classes |
| Uppercase Host | This is a subgroup of Uppercase accelerated function with only host code software |
| ▼Memtest | This is the Memtest platform stressing project. The FPGA tests its DRAM memory |
| Memtest Testbench | This is a subgroup of Memtest accelerated function with only testbench-related functions/classes |
| Memtest HLS | This is a subgroup of Memtest accelerated function with only synthesizable (HLS) functions/classes |
| Memtest Host | This is a subgroup of Memtest accelerated function with only host code software |
| cFp_HelloThemisto | This is the root of the current 'cFp_HelloThemisto' project |
| ▼cFp_HelloKale | This is the root of the current 'cFp_HelloKale' project |
| tcp_app_flash | This module implements a set of TCP-oriented tests and functions |
| tcp_shell_if | This module handles the control flow interface between the SHELL and the ROLE |
| udp_app_flash | This module implements a set of UDP-oriented tests and functions |
| udp_shell_if | This module handles the control flow interface between the SHELL and the ROLE |
1.9.1